Gate driving circuit, driving method, display panel and display device

Abstract

The embodiment of the invention discloses a gate driving circuit, a driving method, a display panel and a display device, and the circuit comprises a pull-up node control circuit which controls the potential of a pull-up node; the pull-down node control circuit is used for controlling the potential of a pull-down node under the control of the pull-up node voltage signal, the control voltage signal and the fixed voltage signal; a first electrode of a pull-down node control transistor in the pull-down node control circuit is electrically connected with a pull-down node; a control voltage signal received by the grid electrode of the pull-down node control transistor is smaller than a fixed voltage signal received by the drain electrode, or the fixed voltage signal received by the grid electrode of the pull-down node control transistor is smaller than the control voltage signal received by the drain electrode; and the gate drive output circuit is used for controlling a gate drive signal output end to output a gate drive signal under the control of the pull-up node voltage signal and the pull-down node voltage signal. According to the embodiment of the invention, the transistor size in the pull-down node control circuit can be reduced, and the occupied area of the whole gate driving unit is reduced.

Description

Technical Field

[0001] Embodiments of the present invention relate to the field of display technology, and in particular to a gate driving circuit, a driving method, a display panel, and a display device. Background Art

[0002] In the related art, a gate driving circuit (also referred to as a GOA (Gate Driver On Array) circuit) includes a plurality of cascaded gate driving units, and a driving signal output end of each level of the gate driving unit corresponds to a gate line respectively, so as to realize line-by-line scanning of the display panel.

[0003] In the current gate drive unit, the transistor responsible for controlling the pull-up node potential needs to consider its driving capability, and is generally designed to be larger in area, which causes the gate drive circuit to occupy a larger space in the display panel border area, affecting the narrow border design of the panel. Summary of the invention

[0004] The present invention provides a gate drive circuit, a drive method, a display panel and a display device to reduce the requirements on the current driving capability of transistors in the gate drive circuit, reduce the size of the transistors, and help reduce the occupied area of ​​the gate drive circuit in the frame area to achieve a narrow frame.

[0005] In one aspect, an embodiment of the present invention provides a gate driving circuit, comprising a plurality of gate driving units; the gate driving units include:

[0006] A pull-up node control circuit, used for controlling the potential of the pull-up node;

[0007] A pull-down node control circuit, used to control the potential of the pull-down node under the control of the voltage signal of the pull-up node, the control voltage signal and the fixed voltage signal;

[0008] The pull-down node control circuit includes a pull-down node control transistor, a first electrode of the pull-down node control transistor is electrically connected to the pull-down node;

[0009] The gate of the pull-down node control transistor receives the control voltage signal, the second electrode receives the fixed voltage signal, and during at least part of the time, the control voltage signal V and the fixed voltage signal VDC satisfy: V<VDC; or, the gate of the pull-down node control transistor receives the fixed voltage signal, the second electrode receives the control voltage signal, and during at least part of the time, the fixed voltage signal VDC and the control voltage signal V satisfy: VDC<V;

[0010] The gate drive output circuit is used to control the gate drive signal outputted from the gate drive signal output terminal under the control of the voltage signal of the pull-up node and the voltage signal of the pull-down node.

[0011] On the other hand, an embodiment of the present invention further provides a driving method of a gate driving circuit, which is applied to any gate driving circuit provided by an embodiment of the present invention, wherein the driving process of the gate driving circuit includes a first output stage and a second output stage;

[0012] The drive methods include:

[0013] In the first output stage, the pull-up node control circuit controls the potential of the pull-up node to be an effective level; the gate drive output circuit controls the gate drive signal outputted from the gate drive signal output terminal to be a first gate drive signal under the control of the voltage signal of the pull-up node;

[0014] In the second output stage, the pull-down node control circuit controls the potential of the pull-down node to be a valid level under the control of the voltage signal of the pull-up node, the control voltage signal and the fixed voltage signal; the gate drive output circuit controls the gate drive signal output from the gate drive signal output end to be a second gate drive signal under the control of the voltage signal of the pull-down node.

[0015] On the other hand, an embodiment of the present invention further provides a display device, comprising any gate driving circuit provided by the embodiment of the present invention.

[0016] In the technical solution of the embodiment of the present invention, the gate driving circuit includes multiple gate driving units; the gate driving unit includes: a pull-up node control circuit, which is used to control the potential of the pull-up node; a pull-down node control circuit, which is used to control the potential of the pull-down node under the control of the voltage signal of the pull-up node, the control voltage signal and the fixed voltage signal; the pull-down node control circuit includes a pull-down node control transistor, and the first electrode of the pull-down node control transistor is electrically connected to the pull-down node; the gate of the pull-down node control transistor receives the control voltage signal, and the second electrode receives the fixed voltage signal, and for at least part of the time, the control voltage signal V and the fixed voltage signal VDC satisfy: V<VDC; or, the gate of the pull-down node control transistor receives the fixed voltage signal, and the second electrode receives the control voltage signal, and for at least part of the time, the fixed voltage signal VDC and the control voltage signal V satisfy: VDC<V; a gate driving output circuit, which is used to control the gate driving signal outputted from the gate driving signal output terminal under the control of the voltage signal of the pull-up node and the voltage signal of the pull-down node. The embodiments of the present invention solve the problem that the gate driving circuit occupies a large space in the border area of ​​the display panel, which affects the narrow border design of the panel. By providing a lower voltage signal than the drain to the gate of the pull-down node control transistor in the pull-down node control circuit, the on-current of the pull-down node control transistor can be reduced, the current driving capability of the pull-down node control transistor can be reduced, and the size of the transistor in the pull-down node control circuit can be reduced, thereby reducing the occupied area of ​​the entire gate driving unit, and further reducing the area of ​​the border area of ​​the display panel, which helps to achieve a narrow border design. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 It is a structural schematic diagram of a gate driving unit in the related art;

[0018] Figure 2 yes Figure 1 A schematic diagram of a circuit structure of a gate driving unit shown;

[0019] Figure 3 yes Figure 2 The driving signal timing diagram of the gate driving unit shown;

[0020] Figure 4 is a schematic structural diagram of a gate driving circuit provided by an embodiment of the present invention;

[0021] Figure 5 and Figure 6 is a schematic structural diagram of two gate driving units provided by an embodiment of the present invention;

[0022] Figure 7 is a flow chart of a driving method of a gate driving circuit provided by an embodiment of the present invention;

[0023] Figure 8 yes Figure 5 and Figure 6 The driving signal timing diagram of the gate driving unit shown;

[0024] Fig. 9 and Fig.10 1 is a schematic diagram of the structure of two more gate driving units provided by an embodiment of the present invention;

[0025] Fig.11 is a flow chart of another driving method of a gate driving circuit provided by an embodiment of the present invention;

[0026] Fig.12 yes Fig. 9 and Fig.10 The driving signal timing diagram of the gate driving unit shown;

[0027] Fig.13 is a structural schematic diagram of another gate driving unit provided by an embodiment of the present invention;

[0028] Fig.14 and Fig.15 1 is a schematic diagram of the structure of two more gate driving units provided by an embodiment of the present invention;

[0029] Fig.16 is a structural schematic diagram of another gate driving unit provided by an embodiment of the present invention;

[0030] Fig.17 It is a structural schematic diagram of a display device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0031] The present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. It is to be understood that the specific embodiments described herein are only used to explain the present invention, rather than to limit the present invention. It should also be noted that, for ease of description, only parts related to the present invention, rather than all structures, are shown in the accompanying drawings.

[0032] The terms used in the embodiments of the present invention are only for the purpose of describing specific embodiments, and are not intended to limit the present invention. It should be noted that the directional words such as "upper", "lower", "left", "right" and the like described in the embodiments of the present invention are described at the angles shown in the accompanying drawings and should not be understood as limitations on the embodiments of the present invention. In addition, in the context, it is also necessary to understand that when it is mentioned that an element is formed "on" or "under" another element, it can not only be directly formed "on" or "under" another element, but also indirectly formed "on" or "under" another element through an intermediate element. The terms "first", "second", etc. are only used for descriptive purposes and do not represent any order, quantity or importance, but are only used to distinguish different components. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood in specific circumstances.

[0033] The term “including” and its variations used in the present invention are open inclusions, that is, “including but not limited to.” The term “based on” means “based at least in part on.” The term “one embodiment” means “at least one embodiment.”

[0034] It should be noted that the concepts such as "first" and "second" mentioned in the present invention are only used to distinguish the corresponding contents, and are not used to limit the order or interdependence.

[0035] It should be noted that the modifications of "one" and "plurality" mentioned in the present invention are illustrative rather than restrictive, and those skilled in the art should understand that, unless otherwise clearly indicated in the context, it should be understood as "one or more".

[0036] Figure 1 is a schematic diagram of the structure of a gate driving unit in the related art. Figure 2 yes Figure 1 A circuit structure diagram of a gate driving unit is shown in FIG. Figure 3 yes Figure 2 The driving signal timing diagram of the gate driving unit shown in FIG. Figure 1-Figure 3In the related art, the gate driving unit 100' may include a pull-up node control circuit 10', a pull-down node control circuit 20' and a gate signal output circuit 30'; the gate signal output circuit 30' includes a first output transistor T31' and a second output transistor T32'; the gate of the first output transistor T31' is connected to the pull-up node PU, the first electrode is connected to the clock signal CLK, and the second electrode is connected to the output terminal GOUT; the pull-up node control circuit 10' is used to control the potential of the pull-up node PU, that is, to control the gate potential of the first output transistor T31', thereby controlling the first output transistor T 31' is turned on, so when the clock signal CLK is a high-level signal VGH, a high-level signal VGH is output to realize the pull-up process of the output signal GOUT; the gate of the second output transistor T32' is connected to the pull-down node PD, the first electrode is connected to the output terminal GOUT, and the second electrode is connected to the low-level voltage signal VGL; the pull-down node control circuit 20' is used to control the potential of the pull-down node PD, that is, to control the gate potential of the second output transistor T32', and then control the second output transistor T32' to be turned on, so as to output the low-level voltage signal VGL, and realize the pull-down process of the output signal GOUT. It can be seen from the above that the gate driving unit 100' can actually realize output control through the cooperation of the pull-up node control circuit 10' on the pull-up node PU and the pull-down node control circuit 20' on the pull-down node PD.

[0037] For the pull-down node control circuit 20', if Figure 2 As shown, it may include a first transistor T21' and a second transistor T22', and a third transistor T13' is provided in the pull-up node control circuit 10'. These transistors are all N-type channel transistors, and the gate G and the first electrode (drain D) of the first transistor T21' are both connected to the pull-down node control signal SEL, and the second electrode (source S) of the first transistor T21' is connected to the first electrode of the second transistor T22', and the connection node forms a pull-down node PD, and the gate of the second transistor T22' is connected to the pull-up node PU, and the second electrode of the second transistor T22' is connected to the low-level voltage signal terminal VGL. The gate of the third transistor T13' is connected to the pull-down node PD, the first electrode is connected to the pull-up node PU, and the second electrode is connected to the low-level voltage signal terminal VGL.

[0038] It should be noted that the pull-down node control signal SEL is always a high-level signal, and the gate G and the second electrode, that is, the source S, form a gate-source voltage difference, which can control the first transistor T21' to remain continuously turned on. Figure 3In the stage t2 shown, the first transistor T21' is in the on state, and the pull-down node PD inputs the pull-down node control signal SEL, that is, a high-level signal, which controls the third transistor T13' to be turned on, so that the pull-up node PU passes the low-level voltage signal VGL, and the pull-up node PU controls the second transistor T22' to be turned off. In this process, the pull-down node PD is in a high-level state, which can control the second output transistor T32' to be turned on, and the pull-up node PU is in a low-level state, which can control the first output transistor T31' to be turned off, and the output signal GOUT outputs a low-level voltage signal, thereby realizing the pull-down process of the output signal GOUT.

[0039] On the contrary, during the process of pulling up the output signal GOUT, that is, Figure 3 In the stage t1 shown, the pull-down node PD is in a low level state, controlling the second output transistor T32' to be turned off, while the pull-up node PU is controlled by the pull-up node control circuit 10' and is in a high level state, controlling the first output transistor T31' to be turned on, and the output signal GOUT can output a high level signal when the clock signal CLK is at a high level, thereby realizing the pull-up process of the output signal GOUT.

[0040] It should be noted that, in the process of pulling up the output signal GOUT, since the pull-up node PU is in a high level state, the second transistor T22' will be controlled to be turned on, and at the same time, the first transistor T21' generates a gate-source voltage difference under the control of the high-level pull-down node control signal SEL, and is always in a conducting state, which will form a series path between the pull-down node control signal SEL and the low-level voltage signal terminal VGL through the first transistor T21', the pull-down node PD and the second transistor T22'. At this time, the potential of the pull-down node PD will depend on the current driving capability of the first transistor T21' and the second transistor T22'. In order to ensure that the pull-down node PD is in a low level state during the process of pulling up the output signal GOUT, and the second output transistor T32' is turned off, the second transistor T22' needs to have a stronger current driving capability. Furthermore, the current driving capability ratio of the second transistor T22' to the first transistor T21' is usually designed to be more than 10 times, otherwise the potential of the pull-down node PD cannot be pulled down, which will result in failure to turn off the second output transistor T32', affecting the high level output of the output signal GOUT.

[0041] For the above reasons, when the second transistor T22' and the first transistor T21' are specifically prepared, the size of the second transistor T22' needs to be designed to be relatively large to achieve its larger current driving capability. Obviously, this circuit design will cause the large size of the second transistor T22', that is, each gate driving unit 100' needs to be designed with at least one large-size transistor, and the gate driving circuit generally requires multiple gate driving units 100' to be cascaded, resulting in a large occupied area of ​​the entire circuit, affecting the overall area of ​​the display panel frame area, and is not conducive to achieving a narrow frame design.

[0042] In view of the above technical problems, an embodiment of the present invention provides a gate driving circuit. Figure 4 is a schematic structural diagram of a gate driving circuit provided by an embodiment of the present invention, Figure 5 and Figure 6 is a schematic diagram of the structure of two gate drive units provided in an embodiment of the present invention, referring to Figure 4-Figure 6 The gate driving circuit includes a plurality of gate driving units 100; the gate driving unit 100 includes: a pull-up node control circuit 10, used to control the potential of the pull-up node PU; a pull-down node control circuit 20, used to control the potential of the pull-down node PD under the control of the voltage signal of the pull-up node PU, the control voltage signal and the fixed voltage signal; the pull-down node control circuit 20 includes a pull-down node control transistor T21, the first electrode, i.e., the source electrode S of the pull-down node control transistor T21 is electrically connected to the pull-down node PD; the gate G of the pull-down node control transistor T21 receives the control voltage signal, and the first electrode S of the pull-down node control transistor T21 receives the control voltage signal, and the gate G ... The second electrode, i.e., the drain electrode D, receives a fixed voltage signal, and for at least part of the time, the control voltage signal V and the fixed voltage signal VDC satisfy: V<VDC; or, the gate G of the pull-down node control transistor T21 receives a fixed voltage signal, and the second electrode, i.e., the drain electrode D, receives a control voltage signal, and for at least part of the time, the fixed voltage signal VDC and the control voltage signal V satisfy: VDC<V; the gate drive output circuit 30 is used to control the gate drive signal outputted from the gate drive signal output terminal GOUT under the control of the voltage signal of the pull-up node PU and the voltage signal of the pull-down node PD.

[0043] First of all, it is known to those skilled in the art that in a display panel, taking an organic light-emitting display panel as an example, a plurality of pixel units are provided in the display area, and the pixel unit is composed of a pixel circuit and a light-emitting element. The pixel circuit drives the light-emitting element to emit light, so as to realize the display of the entire screen through the cooperation of a plurality of pixel units. The gate driving circuit provided in the embodiment of the present invention is mainly used in the display panel, and is responsible for providing a gate driving signal to the transistor in the pixel circuit of the display area, so as to control the driving and emitting process of the light-emitting element by the pixel circuit. Specifically, each gate driving unit 100 in the gate driving circuit provided in the embodiment of the present invention can be set to be responsible for providing a gate driving signal GOUT to the pixel circuit in the pixel unit of the same row, so as to realize the driving control of the pixel unit of the row, and each gate driving unit 100 is responsible for providing a gate driving signal to the pixel unit of the corresponding row in turn, thereby realizing the line-by-line scanning process, and at the same time, based on the visual residual effect of the human eye, completing the display of a frame of the picture.

[0044] In the embodiment of the present invention, the gate driving unit 100 mainly realizes the generation and output of the gate driving signal GOUT by the gate driving output circuit 30. The gate driving output circuit 30 is controlled by the voltage signals of two nodes, namely the pull-up node PU and the pull-down node PD. Specifically, the pull-up node PU is responsible for controlling the gate driving signal GOUT output by the gate driving circuit 30 to be pulled up to a high-level voltage signal, and the pull-down node PD is responsible for controlling the gate driving signal GOUT output by the gate driving circuit 30 to be pulled down to a low-level voltage signal. The pull-up node PU and the pull-down node PD are respectively provided with corresponding control circuits, namely the pull-up node control circuit 10 and the pull-down node control circuit 20 for potential control.

[0045] For the pull-down node control circuit 20, in the embodiment of the present invention, it is configured to include a pull-down node control transistor T21, which is an N-type channel transistor, and its source S is connected to the pull-down node PD. Figure 5 As shown, in a specific embodiment, the gate G of the pull-down node control transistor T21 may be set to receive a fixed voltage signal VDC, and the drain D may receive a control voltage signal V. The fixed voltage signal VDC received by the gate G is set to be smaller than the control voltage signal V received by the drain D. Compared with the gate and drain inputting the pull-down node control signal SEL at the same time, the voltage difference between the gate G and the source S may be reduced on the basis of the transistor being turned on. As can be seen from the positive correlation between the on-current of the transistor and the gate-source voltage difference, the on-current of the transistor may be reduced, thereby reducing the current driving capability of the pull-down node control transistor T21.

[0046] Similarly, if Figure 6As shown, in another specific embodiment, the gate G of the pull-down node control transistor T21 may also be configured to receive the control voltage signal V, and the drain D may receive the fixed voltage signal VDC. Thus, the control voltage signal V received by the gate G is configured to be smaller than the fixed voltage signal VDC received by the drain D. Compared with the case where the gate and the drain simultaneously input the same signal, the voltage difference between the gate G and the source S may be reduced, thereby reducing the on-current of the transistor and reducing the current driving capability of the pull-down node control transistor T21.

[0047] As described above, when setting the pull-down node control transistor T21 and Figure 5 Another pull-down node control transistor T22 is shown to be connected in series, and the source of the pull-down node control transistor T22 is connected to the low-level voltage signal VGL. When the connection node forms the pull-down node PD, when the series branch is turned on, in order to ensure that the pull-down node PD can still be at a low-level voltage, the current driving capability of the pull-down node control transistor T22 needs to be stronger than that of the pull-down node control transistor T21. In the embodiment of the present invention, by reducing the voltage of the gate input signal of the pull-down node control transistor T21, the current driving capability of the pull-down node control transistor T21 can be reduced, and the current driving capability of the pull-down node control transistor T22 is further reduced. Therefore, the size of the transistors on the series branch, especially the pull-down node control transistor T22, can be reduced during actual preparation, thereby reducing the occupied area of ​​the entire gate drive unit, and further reducing the area of ​​the display panel frame area, which helps to achieve a narrow frame design.

[0048] In the related art, the gate and drain of the pull-down node control transistor T21 simultaneously receive the pull-down node control signal SEL, the high level voltage of the SEL signal is generally 15V, the source, i.e., the voltage of the pull-down node PD is a low level voltage, which is -10V, and the threshold voltage of the transistor is 1.5V. It can be seen that when the pull-down node control transistor T21 is turned on, its gate-source voltage difference Vgs=VGH-Vth-VGL=15V-1.5V-(-10V)=23.5V. In the embodiment of the present invention, Figure 5Taking the embodiment shown as an example, the gate of the pull-down node control transistor T21 receives a fixed voltage signal VDC, which can be specifically set to 5V, the drain receives a control voltage signal V, the high level voltage is also 15V, and the source, i.e., the voltage of the pull-down node, is a low level voltage, which is also -10V. It can be seen that when the pull-down node control transistor T21 is turned on, its gate-source voltage difference Vgs=VDC-Vth-VGL=5V-1.5V-(-10V)=13.5V. By comparison, it can be seen that the gate-source voltage difference of the pull-down node control transistor T21 in the embodiment of the present invention is lower. On this basis, the pull-down node control transistor T22 does not need too high current driving capability, and the ratio of the width-to-length ratio of the pull-down node control transistor T22 to the width-to-length ratio of the pull-down node control transistor T21 can be appropriately reduced, for example, from 2.5 to 3 times to 1.6 to 2 times, thereby reducing the size of the two transistors and reducing the occupied area of ​​the gate drive unit.

[0049] It should be noted that, in the embodiment of the present invention, the control voltage signal V and the fixed voltage signal VDC are set to satisfy V<VDC for at least part of the time, or the fixed voltage signal VDC and the control voltage signal V are set to satisfy VDC<V for at least part of the time, which essentially means that the voltage signal transmitted on the control voltage signal V can change over time. In the stage where the above-mentioned pull-down node control transistor T21 and the other pull-down node control transistor T22 are both turned on to form a series path, it is ensured that the gate voltage is higher than the source voltage and appropriately lower than the voltage of the drain input signal, thereby reducing the gate-source voltage difference of the pull-down node control transistor T21, thereby reducing the conduction current, so that when the series path is turned on, because the other pull-down node control transistor T22 has a larger current driving capability, the low-level voltage signal VGL connected to its source pulls down the voltage of the pull-down node PD, thereby controlling the gate drive output circuit.

[0050] In the above technical solution, the gate drive circuit includes multiple gate drive units; the gate drive unit includes: a pull-up node control circuit, which is used to control the potential of the pull-up node; a pull-down node control circuit, which is used to control the potential of the pull-down node under the control of the voltage signal of the pull-up node, the control voltage signal and the fixed voltage signal; the pull-down node control circuit includes a pull-down node control transistor, and the source of the pull-down node control transistor is electrically connected to the pull-down node; the gate of the pull-down node control transistor receives the control voltage signal, and the drain receives the fixed voltage signal, and for at least part of the time, the control voltage signal V and the fixed voltage signal VDC satisfy: V<VDC; or, the gate of the pull-down node control transistor receives the fixed voltage signal, and the drain receives the control voltage signal, and for at least part of the time, the fixed voltage signal VDC and the control voltage signal V satisfy: VDC<V; the gate drive output circuit is used to control the gate drive signal outputted from the gate drive signal output terminal under the control of the voltage signal of the pull-up node and the voltage signal of the pull-down node. The embodiments of the present invention solve the problem that the gate driving circuit occupies a large space in the border area of ​​the display panel, which affects the narrow border design of the panel. By providing a lower voltage signal than the drain to the gate of the pull-down node control transistor in the pull-down node control circuit, the on-current of the pull-down node control transistor can be reduced, the current driving capability of the pull-down node control transistor can be reduced, and the size of the transistor in the pull-down node control circuit can be reduced, thereby reducing the occupied area of ​​the entire gate driving unit, and further reducing the area of ​​the border area of ​​the display panel, which helps to achieve a narrow border design.

[0051] It should also be noted that the gate driving circuit of the embodiment of the present invention can be specifically applied to an organic light-emitting display panel. In addition, it can also be applied to a liquid crystal display (LCD) panel, a quantum dot display (QLED) panel, and a micro light-emitting diode (Micro LED) panel, etc., without limitation here.

[0052] Continue to refer Figure 5 and Figure 6 Optionally, a plurality of gate driving units 100 are cascaded in sequence; the pull-up node control circuit 10 includes a first pull-up node control transistor T11 and a second pull-up node control transistor T12; the second electrode, i.e., the drain electrode, of the first pull-up node control transistor T11 receives the forward scanning control signal DIR1, the first electrode, i.e., the source electrode, is connected to the pull-up node PU, and the gate receives the gate driving signal G outputted from the gate driving signal output terminal of the cascaded upper-level gate driving unit 100 n-1 The second pull-up node controls the second electrode of the transistor T12, i.e., the drain electrode, to receive the reverse scan control signal DIR2, the first electrode, i.e., the source electrode, is connected to the pull-up node PU, and the gate electrode receives the gate drive signal G outputted from the gate drive signal output terminal of the next gate drive unit in the cascade. n+1; Wherein, in the same gate driving unit 100, the polarity of the forward scanning control signal DIR1 is opposite to the polarity of the reverse scanning control signal DIR2. Further, the pull-up node control circuit 10 also includes a pull-up node control transistor T13; the second electrode, i.e., the drain electrode, of the pull-up node control transistor T13 is connected to the pull-up node PU, the first electrode, i.e., the source electrode receives the first power supply signal, and the gate electrode is connected to the pull-down node PD. Wherein, the first power supply signal can specifically be a low-level voltage signal VGL.

[0053] Continue to refer Figure 5 and Figure 6 Optionally, the gate drive output circuit 30 includes a first output control transistor T31 and a second output control transistor T32; the second electrode, i.e., the drain electrode, of the first output control transistor T31 receives the clock signal CK, the first electrode, i.e., the source electrode, is connected to the gate drive signal output terminal GOUT, and the gate is connected to the pull-up node PU; the second electrode, i.e., the drain electrode, of the second output control transistor T32 is connected to the gate drive signal output terminal GOUT, the first electrode, i.e., the source electrode, receives the first power supply signal, and the gate is connected to the pull-down node PD. Similarly, the first power supply signal may specifically be a low-level voltage signal VGL.

[0054] Continue to refer Figure 5 and Figure 6 , further optionally, the gate drive output circuit 30 further includes a tank circuit 40, the tank circuit 40 is connected to the pull-up node PU, and is used to maintain the potential of the pull-up node PU. Specifically, the tank circuit 40 includes a storage capacitor C1, a first plate of the storage capacitor C1 is connected to the pull-up node PU, and a second plate is connected to the gate drive signal output terminal GOUT.

[0055] Based on the gate driving circuit provided in the above embodiment, the embodiment of the present invention provides a driving method of the gate driving circuit. Specifically, the driving process of the gate driving circuit includes a first output stage t1 and a second output stage t2. Figure 7 is a flow chart of a driving method of a gate driving circuit provided by an embodiment of the present invention, Figure 8 yes Figure 5 and Figure 6 The driving signal timing diagram of the gate driving unit shown in FIG. Figure 7 and Figure 8 , the driving method may include:

[0056] S110, in the first output stage, the pull-up node control circuit controls the potential of the pull-up node to be a valid level; the gate drive output circuit controls the gate drive signal outputted from the gate drive signal output terminal to be a first gate drive signal under the control of the voltage signal of the pull-up node;

[0057] Based on the energy storage circuit 40 provided in the gate drive output circuit 30, the first output stage t1 is specifically divided into an input stage ta and an output stage tb. In the input stage, the pull-up node control circuit charges the energy storage circuit through the pull-up node; in the output stage, the energy storage circuit self-discharges to maintain the potential of the pull-up node at an effective level, and the gate drive output circuit controls the gate drive signal outputted from the gate drive signal output terminal to be the first gate drive signal under the control of the voltage signal of the pull-up node.

[0058] Specifically, refer to Figure 5 and Figure 6 Since the first output control transistor T31 is an N-type channel transistor, the effective level of the pull-up node PU is a high level, that is, when the pull-up node PU is at a high level, the first output control transistor T31 is turned on. Figure 8 In the driving timing shown, the forward scanning control signal DIR1 is a high level signal, and the reverse scanning control signal DIR2 is a low level signal. In the input phase ta of the first output phase t1, that is, when the previous gate driving signal G n-1 When the first pull-up node control transistor T11 is turned on, the pull-up node PU is fed with the forward scanning control signal DIR1, thereby charging the storage capacitor C1. n-1 When the clock signal CK is at a low level, the storage capacitor C1 is self-discharged, so that the pull-up node PU is pulled up to a high level, that is, the effective level of the first output control transistor T31, and the first output control transistor T31 is controlled to be turned on. Therefore, in the output stage tb of the first output stage t1, the first output control transistor T31 is turned on and is responsible for outputting the clock signal CK as the first gate drive signal. At this time, when the clock signal CK is at a high level, the gate drive signal G n The output is high level.

[0059] In addition, in the first output stage t1, the high-level pull-up node PU corresponds to the pull-down node control transistor T22 that can be controlled to turn on, and the pull-down node control transistors T21 and T22 that are always in the on state form a series path. Since the current driving capability of the pull-down node control transistor T22 is set to be much greater than that of T21, the pull-down node PD approaches the low-level voltage signal VGL, that is, the pull-down node PD is at a low level, and the pull-down node PD is at an invalid level at this time, controlling the second output control transistor T32 to turn off.

[0060] S120. In the second output stage, the pull-down node control circuit controls the potential of the pull-down node to be a valid level under the control of the voltage signal of the pull-up node, the control voltage signal and the fixed voltage signal; the gate drive output circuit controls the gate drive signal outputted from the gate drive signal output terminal to be a second gate drive signal under the control of the voltage signal of the pull-down node.

[0061] refer to Figure 5 and Figure 6 Since the second output control transistor T32 is an N-type channel transistor, the effective level of the pull-down node PD is also a high level, that is, when the pull-down node PD is at a high level, the second output control transistor T32 is turned on. Figure 8 In the second output stage t2, the storage capacitor C1 is discharged, and the pull-up node PU is at a low level, thereby controlling the first output control transistor T31 to turn off. Therefore, in the second output stage t2, the pull-up node PU is at a low level, correspondingly controlling the pull-down node control transistor T22 to turn off, and the pull-down node control transistor T21, which is always in the on state, inputs its drain signal to the pull-down node PD. Figure 5 In the embodiment shown, the pull-down node PD inputs a control voltage signal V. Figure 6 In the illustrated embodiment, a fixed voltage signal VDC is input to the pull-down node PD, and both voltage signals are high-level signals, that is, the pull-down node PD is at a high level at this stage, which serves as a valid level to control the second output control transistor T32 to be turned on, responsible for outputting the low-level voltage signal VGL as the second gate drive signal.

[0062] It can be seen from the above two stages that the gate drive unit substantially realizes the above-mentioned gate drive signal G n-1 The effective pulse of the clock signal CK is used as the control pulse, and the effective pulse delayed by one pulse cycle relative to the control pulse is used as the gate drive signal G of this stage. n The output function is to drive the gate signal G n The pulse signal is relative to the previous gate drive signal G n-1 There is a delay of one pulse cycle, that is, the shift function is realized. The cascaded gate drive units 100 of each level are based on the gate drive signal G n-1 Sequential shift output can be achieved.

[0063] In addition, it should be noted that, according to the working principle of the above circuit, the forward scanning control signal DIR1 actually realizes the process of shifting and driving the gate driving units 100 of each level from the front level to the back level in sequence, that is, in the display panel, a row-by-row scanning process from top to bottom can be realized. In the pull-up node control circuit 10, a second pull-up node control transistor T12 is also provided, and its gate receives the next level gate driving signal G n+1 , the source receives the reverse scanning control signal DIR2, which is actually the process of shifting and driving from the rear stage to the front stage in sequence through the reverse scanning control signal DIR2, that is, realizing the progressive scanning process from bottom to top. When performing progressive scanning from bottom to top, the reverse scanning control signal DIR2 can be converted into a high level signal and the forward scanning control signal DIR1 can be converted into a low level signal. In the process of reverse scanning from bottom to top, its working principle is the same as that of the forward scanning process, which will not be repeated here.

[0064] In addition, it should be noted that, in the forward scanning process from top to bottom, for the first-stage gate driving unit 100, since there is no previous-stage gate driving unit 100, the gate of the first pull-up node control transistor T11 actually receives the trigger signal STV, and the gate driving signal shift output of each stage of the gate driving unit is realized through the trigger signal STV. Similarly, in the reverse scanning process from bottom to top, for the last-stage gate driving unit 100, there is no next-stage gate driving unit 100, and the gate of the first pull-up node control transistor T11 also receives the trigger signal STV, and the gate driving signal shift output of each stage of the gate driving unit is realized through the trigger signal STV.

[0065] Fig. 9 and Fig.10 is a schematic diagram of the structure of two gate drive units provided in an embodiment of the present invention, referring to Fig. 9 and Fig.10 In the gate driving unit, the pull-down node PD includes a first pull-down node PD1 and a second pull-down node PD2; the pull-down node control circuit 20 includes a first pull-down node control circuit 21 and a second pull-down node control circuit 22; the control voltage signal includes a first control voltage signal EVN and a second control voltage signal ODD; the first pull-down node control circuit 21 is used to control the potential of the first pull-down node PD1 under the control of the voltage signal of the pull-up node PU, the first control voltage signal EVN and the fixed voltage signal VDC; the second pull-down node control circuit 22 is used to control the potential of the second pull-down node PD2 under the control of the voltage signal of the pull-up node PU, the second control voltage signal ODD and the fixed voltage signal VDC.

[0066] The first pull-down node control circuit 21 includes a first pull-down node control transistor T211, a first electrode, i.e., a source electrode S, of the first pull-down node control transistor T211 is electrically connected to the first pull-down node PD1; a gate electrode G of the first pull-down node control transistor T211 receives a fixed voltage signal VDC, and a second electrode, i.e., a drain electrode D, receives a first control voltage signal EVN. Fig. 9 Or, the gate G of the first pull-down node control transistor T211 receives the first control voltage signal EVN, and the second electrode, that is, the drain D receives the fixed voltage signal VDC, such as Fig.10 shown.

[0067] The second pull-down node control circuit 22 includes a second pull-down node control transistor T212, a first electrode, i.e., a source electrode S, of the second pull-down node control transistor T212 is electrically connected to the second pull-down node PD2; a gate electrode G of the second pull-down node control transistor T212 receives a fixed voltage signal VDC, and a second electrode, i.e., a drain electrode D, receives a second control voltage signal ODD. Fig. 9 As shown, or, the gate G of the second pull-down node control transistor T212 receives the second control voltage signal ODD, and the second electrode, that is, the drain D receives the fixed voltage signal VDC, as shown in FIG. Fig.10 As shown; wherein, the first control voltage signal EVN and the second control voltage signal ODD switch between the first voltage and the second voltage over time, and one of the two is the first voltage V1, and the other is the second voltage V2, V1<V2.

[0068] The gate drive output circuit is used to control the gate drive signal outputted by the gate drive signal output terminal GOUT under the control of the voltage signal of the pull-up node PU, the voltage signal of the first pull-down node PD1 and the voltage signal of the second pull-down node PD2.

[0069] Specifically, the second output control transistor in the gate drive output circuit 30 may include a first sub-output control transistor T321 and a second sub-output control transistor T322; wherein the gate of the first sub-output control transistor T321 is electrically connected to the first pull-down node PD1, the drain is connected to the gate drive signal output terminal GOUT, and the source is connected to the first power supply signal; the gate of the second sub-output control transistor T322 is electrically connected to the second pull-down node PD2, the drain is connected to the gate drive signal output terminal GOUT, and the source is connected to the first power supply signal.

[0070] like Fig. 9 and Fig.10In the two specific embodiments shown, the first pull-down node control circuit 21 and the second pull-down node control circuit 22 are essentially set to control the potential of the first pull-down node PD1 and the second pull-down node PD2 respectively, and the two pull-down nodes are used to alternately control the pull-down process of the gate drive signal GOUT output by the gate drive output circuit 30. The alternating control principle and process are not described in detail here. It can be understood that in the first pull-down node control circuit 21 and the second pull-down node control circuit 22, the circuit structure is completely consistent. For the gate drive unit, the two pull-down node control circuits can provide a gate-source voltage difference to the first pull-down node control transistor T211 and the second pull-down node control transistor T212, and appropriately reduce the gate voltage, so as to reduce the conduction current of the two pull-down node control transistors, reduce their current driving capability, and then help reduce the current driving capability of another pull-down node control transistor connected in series with them, thereby reducing the size of the transistor and reducing the occupied area of ​​the entire gate drive unit.

[0071] Continue to refer Fig. 9 and Fig.10 , further, the fixed voltage signal VDC, the first voltage V1 and the second voltage V2 satisfy: V1<VDC<V2.

[0072] In such Fig. 9 In the illustrated embodiment, the first pull-down node control circuit 21 also includes a third pull-down node control transistor T223, and the second pull-down node control circuit 22 also includes a fourth pull-down node control transistor T224; the gates G of the first pull-down node control transistor T211 and the second pull-down node control transistor T212 both receive a fixed voltage signal VDC, the second electrode, i.e., the drain D of the first pull-down node control transistor T211 receives a first control voltage signal EVN, and the second electrode, i.e., the drain D of the second pull-down node control transistor T212 receives a second control voltage signal ODD; the second electrode, i.e., the drain of the third pull-down node control transistor T223 is connected to the first pull-down node PD1, and the second electrode, i.e., the drain of the fourth pull-down node control transistor T224 is connected to the second pull-down node PD2; the gates of the third pull-down node control transistor T223 and the fourth pull-down node control transistor T224 are both connected to the pull-up node PU, and the first electrodes, i.e., the sources, both receive the first power supply signal.

[0073] In such Fig.10In the illustrated embodiment, the first pull-down node control circuit 21 also includes a third pull-down node control transistor T223, and the second pull-down node control circuit 22 also includes a fourth pull-down node control transistor T224; the second poles, i.e., the drains, D of the first pull-down node control transistor T211 and the second pull-down node control transistor T212 both receive a fixed voltage signal VDC, the gate G of the first pull-down node control transistor T211 receives a first control voltage signal EVN, and the gate of the second pull-down node control transistor T212 receives a second control voltage signal ODD; the second pole, i.e., the drain, of the third pull-down node control transistor T223 is connected to the first pull-down node PD1, and the second pole, i.e., the drain, of the fourth pull-down node control transistor T224 is connected to the second pull-down node PD2; the gates of the third pull-down node control transistor T223 and the fourth pull-down node control transistor T224 are both connected to the pull-up node PU, and the first poles, i.e., the sources, both receive the first power supply signal.

[0074] In addition, in Fig. 9 and Fig.10 In the illustrated embodiment, the ratio of the width-to-length ratio of the third pull-down node control transistor T223 to the width-to-length ratio of the first pull-down node control transistor T211 can be set to be in the range of 1.6 to 2; and / or, the ratio of the width-to-length ratio of the fourth pull-down node control transistor T224 to the width-to-length ratio of the second pull-down node control transistor T213 can be in the range of 1.6 to 2. Thus, the third pull-down node control transistor T223 can have a higher current driving capability than the first pull-down node control transistor T211, and at the same time, it can also ensure that the third pull-down node control transistor T223 does not need to be too large in size compared to the first pull-down node control transistor T211, thereby reducing the sizes of the two transistors and reducing the occupied area of ​​the gate drive unit. Similarly, the fourth pull-down node control transistor T224 can have a higher current driving capability than the second pull-down node control transistor T212. At the same time, it can also ensure that the fourth pull-down node control transistor T224 does not need to be too large in size compared to the second pull-down node control transistor T212, thereby reducing the size of the two transistors and reducing the area occupied by the gate drive unit.

[0075] It should be noted here that if Fig. 9 and Fig.10 As shown, the first power signal can be understood as a low-level voltage signal VGL, which is responsible for pulling down the potential of the first pull-down node PD1 when the third pull-down node control transistor T223 is turned on, or pulling down the potential of the second pull-down node PD2 when the fourth pull-down node control transistor T224 is turned on.

[0076] Based on the above Fig. 9 and Fig.10 In addition to the two gate driving circuits shown in the figure, an embodiment of the present invention further provides a driving method for a gate driving circuit. Fig.11 is a flow chart of another gate driving method provided by an embodiment of the present invention, Fig.12 yes Fig. 9 and Fig.10 The driving signal timing diagram of the gate driving unit shown in FIG. Fig.11 and Fig.12 First, the driving process of the gate driving circuit may include a first display cycle T1 and a second display cycle T2; the first display cycle T1 and the second display cycle T2 both include a first output stage t1 and a second output stage t2. Among them, the first display cycle T1 can be understood as a display cycle in which the first pull-down node control circuit 21 performs a pull-down function, and the second display cycle T2 can be understood as a display cycle in which the second pull-down node control 22 performs a pull-down action. The two display cycles can be arranged alternately to achieve alternating operation and alternating rest of the two pull-down node control circuits, thereby avoiding electrical drift caused by continuous operation of the transistor.

[0077] The alternating operation process of the two pull-down node control circuits is essentially realized by the control of the first control voltage signal EVN and the second control voltage signal ODD. Fig. 9 , Fig.10 and Fig.12 , the first control voltage signal EVN and the second control voltage signal ODD switch between the first voltage V1 and the second voltage V2 over time, the first voltage V1 can be understood as a low-level voltage VGL, and the second voltage V2 can be understood as a high-level voltage VGH, and the two control voltage signals are transformed between high and low-level voltages. Since the sources of the third pull-down node control transistor T223 and the fourth pull-down node control transistor T224 receive the low-level voltage signal VGL, the pull-down node realizes a high-level voltage signal, which is mainly passed to the first pull-down node PD1 and the second pull-down node PD2 by the first pull-down node control transistor T211 and the second pull-down node control transistor T212 respectively, that is, the pull-down action of the pull-down node control circuit is mainly controlled by whether the first pull-down node control transistor T211 and the second pull-down node control transistor T212 are turned on. Taking the first pull-down node control circuit 21 performing a pull-down action as an example, when the first control voltage signal EVN is converted into a high-level voltage signal, the first pull-down node control transistor T211 will be controlled to be turned on, thereby passing a high-level voltage signal to the first pull-down node PD1 through the first pull-down node control transistor T211, so that the first pull-down node control circuit 21 can perform a pull-down action. At the same time, since the second control voltage signal ODD is a low-level voltage signal at this time, the second pull-down node control transistor T212 is turned off, so that the second pull-down node PD2 cannot pass a high-level voltage signal and cannot perform a pull-down action, that is, enters a rest state.

[0078] Based on the above circuit structure, the driving method of this embodiment may specifically include:

[0079] S210, in the first output stage of the first display cycle and the second display cycle, the pull-up node control circuit controls the potential of the pull-up node to be a valid level; the gate drive output circuit controls the gate drive signal outputted from the gate drive signal output terminal to be a first gate drive signal under the control of the voltage signal of the pull-up node.

[0080] The first display period T1 refers to the display period in which the first pull-down node control circuit 21 performs the pull-down action, and the second display period T2 refers to the display period in which the second pull-down node control circuit 22 performs the pull-down action. Moreover, as mentioned above, in the first output stage t1 of the gate driving unit, it is mainly the stage in which the pull-up node control circuit 10 inputs a high-level voltage signal VGH, i.e., an effective level, to the pull-up node PU to perform the pull-up action. In this stage, the gate driving signal G n-1 The first output control transistor T31 is turned on, and the gate drive signal output terminal GOUT outputs the clock signal CK as the first gate drive signal.

[0081] In addition, the high-level pull-up node PU will control the third pull-down node control transistor T223 and the fourth pull-down node control transistor T224 to be turned on, regardless of whether the first pull-down node control transistor T211 and the second pull-down node control transistor T212 are turned on, that is, whether in the first display period T1 or the second display period T2, since the current driving capability of the third pull-down node control transistor T223 is much greater than the current driving capability of the first pull-down node control transistor T211, and the current driving capability of the fourth pull-down node control transistor T224 is much greater than the current driving capability of the second pull-down node control transistor T212, the first pull-down node PD1 and the second pull-down node PD2 will be connected to the first power supply signal, that is, the low-level voltage signal VGL, that is, the invalid level, thereby controlling the first sub-output control transistor T321 and the second sub-output control transistor T322 to be turned off.

[0082] S221. In the second output stage of the first display cycle, the first pull-down node control circuit controls the potential of the first pull-down node to be a valid level under the control of the voltage signal of the pull-up node, the first control voltage signal and the fixed voltage signal; the gate drive output circuit controls the gate drive signal output from the gate drive signal output terminal to be a second gate drive signal under the control of the voltage signal of the first pull-down node.

[0083] In the first display period T1, that is, in the display period in which the first pull-down node control circuit 21 performs a pull-down operation, the second output stage t2 of the gate driving unit is mainly a stage in which the first pull-down node control circuit 21 inputs a high-level voltage signal VGH to the first pull-down node PD1 to perform a pull-down operation. In this stage, the third pull-down node control transistor T223 is turned off under the control of the pull-up node PU converted to a low level.

[0084] In such Fig. 9 In the embodiment shown, the gate of the first pull-down node control transistor T211 receives a fixed potential signal VDC, and the fixed potential signal VDC is greater than the low level voltage signal VGL, so that the first pull-down node control transistor T211 generates a gate-source voltage difference and is turned on. Fig.10 In the illustrated embodiment, the gate of the first pull-down node control transistor T211 receives the first control voltage signal EVN, and at this time the first control voltage signal EVN is a high-level voltage signal VGH, which is greater than the low-level voltage signal VGL, so that the first pull-down node control transistor T211 generates a gate-source voltage difference and is turned on.

[0085] The turned-on first pull-down node control transistor T211 passes the first control voltage signal EVN to the first pull-down node PD1, which is a high-level voltage signal VGH, i.e., an effective level. The high-level first pull-down node PD1 controls the first sub-output control transistor T321 to turn on, and the gate drive signal output terminal GOUT outputs the first power supply signal, i.e., a low-level voltage signal VGL, as the second gate drive signal.

[0086] S222. In the second output stage of the second display cycle, the second pull-down node control circuit controls the potential of the second pull-down node to be a valid level under the control of the voltage signal of the pull-up node, the second control voltage signal and the fixed voltage signal; the gate drive output circuit controls the gate drive signal output from the gate drive signal output terminal to be a second gate drive signal under the control of the voltage signal of the second pull-down node.

[0087] The second display period T2 means a display period in which the second pull-down node control circuit 22 performs a pull-down action. Based on this, the second output stage t2 of the gate driving unit is mainly a stage in which the second pull-down node control circuit 22 inputs a high-level voltage signal VGH to the second pull-down node PD2 to perform a pull-down action. In this stage, the fourth pull-down node control transistor T224 is turned off under the control of the pull-up node PU converted to a low level.

[0088] In such Fig. 9In the embodiment shown, the gate of the second pull-down node control transistor T212 receives a fixed potential signal VDC, and the fixed potential signal VDC is greater than the low level voltage signal VGL, so that the second pull-down node control transistor T212 generates a gate-source voltage difference and is turned on. Fig.10 In the illustrated embodiment, the gate of the second pull-down node control transistor T212 receives the second control voltage signal ODD, and at this time the second control voltage signal ODD is a high level voltage signal VGH, which is greater than the low level voltage signal VGL, so that the first pull-down node control transistor T211 generates a gate-source voltage difference and is turned on.

[0089] The turned-on second pull-down node control transistor T212 passes the second control voltage signal ODD to the second pull-down node PD2, which is a high-level voltage signal VGH, i.e., an effective level. The high-level second pull-down node PD2 controls the second sub-output control transistor T322 to be turned on, and the gate drive signal output terminal GOUT outputs the first power supply signal, i.e., a low-level voltage signal VGL, as the second gate drive signal.

[0090] Furthermore, the driving method of the above embodiment may further include:

[0091] S223, in the second output stage of the first display period, the second pull-down node control circuit controls the potential of the second pull-down node to be an invalid level under the control of the voltage signal of the pull-up node, the second control voltage signal and the fixed voltage signal;

[0092] In the first display period T1, i.e., in the display period in which the first pull-down node control circuit 21 performs a pull-down operation, the second output stage t2 of the gate driving unit is also the stage in which the second pull-down node control circuit 22 inputs a low-level voltage signal VGL to the second pull-down node PD2 to stop performing the pull-down operation. In this stage, the fourth pull-down node control transistor T224 is turned off under the control of the pull-up node PU converted to a low level.

[0093] In such Fig. 9 In the illustrated embodiment, the gate of the second pull-down node control transistor T212 receives a fixed potential signal VDC, and the fixed potential signal VDC is greater than the low level voltage signal VGL, so that the second pull-down node control transistor T212 generates a gate-source voltage difference and is turned on. The turned-on second pull-down node control transistor T212 passes the second control voltage signal ODD to the second pull-down node PD2, which is a low level voltage signal VGL, i.e., an invalid level, and controls the second sub-output control transistor T322 to be turned off.

[0094] In such Fig.10In the illustrated embodiment, the gate of the second pull-down node control transistor T212 receives the second control voltage signal ODD, and at this time the second control voltage signal ODD is a low-level voltage signal VGL, so that the second pull-down node control transistor T212 generates a gate-source voltage difference lower than the threshold voltage and is turned off. The second pull-down node PD2 is in a floating state because the second pull-down node control transistor T212 and the fourth pull-down node control transistor T224 are both turned off and cannot input the high-level voltage signal VGH, and maintains the low-level voltage signal VGL input in the previous stage, i.e., the first output stage t1, in a low-level state, i.e., an invalid level, and similarly controls the second sub-output control transistor T322 to be turned off.

[0095] S224. In the second output phase of the second display period, the first pull-down node control circuit controls the potential of the first pull-down node to be an invalid level under the control of the voltage signal of the pull-up node, the first control voltage signal and the fixed voltage signal.

[0096] The second display period T2 means a display period in which the second pull-down node control circuit 22 performs a pull-down operation. Based on this, the second output stage t2 of the gate driving unit is also a stage in which the first pull-down node control circuit 21 inputs a low-level voltage signal VGL to the first pull-down node PD1 to stop performing the pull-down operation. In this stage, the third pull-down node control transistor T223 is turned off under the control of the pull-up node PU converted to a low level.

[0097] In such Fig. 9 In the illustrated embodiment, the gate of the first pull-down node control transistor T211 receives a fixed potential signal VDC, and the fixed potential signal VDC is greater than the low level voltage signal VGL, so that the first pull-down node control transistor T211 generates a gate-source voltage difference and is turned on. The turned-on first pull-down node control transistor T211 passes the first control voltage signal EVN to the first pull-down node PD1, which is a low level voltage signal VGL, i.e., an invalid level, and controls the first sub-output control transistor T321 to be turned off.

[0098] In such Fig.10 In the illustrated embodiment, the gate of the first pull-down node control transistor T211 receives the first control voltage signal EVN, and at this time the first control voltage signal EVN is a low-level voltage signal VGL, so that the first pull-down node control transistor T211 generates a gate-source voltage difference lower than the threshold voltage and is turned off. The first pull-down node PD1 is in a floating state because the first pull-down node control transistor T211 and the third pull-down node control transistor T223 are both turned off and cannot input the high-level voltage signal VGH, and maintains the low-level voltage signal VGL input in the previous stage, i.e., the first output stage t1, in a low-level state, i.e., an invalid level, and similarly controls the first sub-output control transistor T321 to be turned off.

[0099] In summary, it can be seen that in the first output stage t1 in which the first control voltage signal EVN and the second control voltage signal ODD are switched alternately, the high-level voltage signal of the gate drive signal GOUT is controlled and output by the pull-up node control circuit 10, the low-level voltage signal is controlled and output by the first pull-down node control circuit 21, and the second pull-down node control circuit 22 does not work. Similarly, it can be seen that in the second output stage t2, after the high and low-level voltage signals of the first control voltage signal EVN and the second control voltage signal ODD are transformed, the low-level voltage signal of the gate drive signal GOUT is transformed to be controlled and output by the second pull-down node control circuit 22, and the first pull-down node control circuit 21 does not work. It can be seen that in this embodiment, by setting the first pull-down node control circuit 21 and the second pull-down node control circuit 22, and by controlling the first control voltage signal EVN and the second control voltage signal ODD, the alternating working mode of the two pull-down node control circuits is realized, thereby making the first pull-down node control transistor T211 and the second pull-down node control transistor T212 intermittently open through the control signal with variable voltage, reducing the risk of DC bias, avoiding the threshold voltage drift problem caused by the two transistors being under a fixed bias for a long time, and ensuring the accuracy and stability of the pull-down process of the gate drive signal GOUT.

[0100] In addition, for the scheme in which the first control voltage signal EVN with a variable voltage is simultaneously input into the gate and source of the first pull-down node control transistor T211, and the second control voltage signal ODD is simultaneously input into the gate and source of the second pull-down node control transistor T212, when the first pull-down node control circuit 21 is controlled to work and the second pull-down node control circuit 22 is stopped, the first pull-down node control transistor T211 will be turned on and the second pull-down node control transistor T212 will be turned off; when the first pull-down node control circuit 21 is controlled to stop and the second pull-down node control circuit 22 is operated, the first pull-down node control transistor T211 will be turned off and the second pull-down node control transistor T212 will be turned on. When any pull-down node control transistor is turned off, for example, the first pull-down node control circuit 21 is working and the second pull-down node control transistor T212 is turned off, at this time, the pull-up node PU is a low-level voltage signal VGL, and the fourth pull-down node control transistor T224 will also be turned off, which will cause the second node PD2 to be in a floating state. Under external interference, the potential of the second node PD2 will change, and there is a risk of changing to a high-level voltage signal and pulling down the gate drive signal OUT of the gate drive output circuit 30, thereby causing the second pull-down node control circuit 22 to continue to work during the stop phase, resulting in a poor stop state. In the case of Fig. 9In the illustrated embodiment, the gates of the first pull-down node control transistor T211 and the second pull-down node control transistor T212 are connected to a DC fixed voltage signal VDC, and the two pull-down node control transistors are always in an on state, during the period when the first pull-down node control circuit 21 is working, the second pull-down node control circuit 22 is stopped, and the pull-up node PU is in a low level state, that is, in the second output stage t2 of the first display period T1, even if the third pull-down node control transistor T223 and the fourth pull-down node control transistor T224 are turned off by the control of the pull-up node PU converted to a low level, the second pull-down node PD2 can still be connected to the second control voltage signal ODD in a low level state through the second pull-down node control transistor T212, and a low level voltage signal can be accurately provided to the second pull-down node PD2, thereby avoiding the problem that the pull-down node potential floats and is disturbed by the outside world, causing the second pull-down node control circuit 22 to stop in a bad state. Similarly, in the second output stage t2 of the second display cycle T2, the first pull-down node PD1 can also pass the first control voltage EVN in a low level state through the first pull-down node control transistor T211, and can accurately provide a low level voltage signal to the second pull-down node PD2, thereby avoiding the problem that the pull-down node potential floats and is affected by external interference, causing the second pull-down node control circuit 22 to stop in a bad state.

[0101] Fig.13 is a schematic diagram of the structure of another gate driving unit provided by an embodiment of the present invention, referring to Fig.13 , in such Fig.10 Based on the illustrated embodiment, optionally, the first pull-down node control circuit 21 also includes a fifth pull-down node control transistor T235; the gate of the fifth pull-down node control transistor T235 is connected to the second pull-down node PD2, the second electrode, i.e., the drain, is connected to the first pull-down node PD1, and the first electrode, i.e., the source, receives the first power signal; the second pull-down node control circuit 22 also includes a sixth pull-down node control transistor T236; the gate of the sixth pull-down node control transistor T236 is connected to the first pull-down node PD1, the second electrode, i.e., the drain, is connected to the second pull-down node PD2, and the first electrode, i.e., the source, receives the first power signal.

[0102] As mentioned above, in Fig.10 In the illustrated embodiment, the drains D of the first pull-down node control transistor T211 and the second pull-down node control transistor T212 both receive a DC fixed voltage signal VDC, while the gates receive a first control voltage signal EVN and a second control voltage signal ODD with variable voltages, respectively. Similarly, since the first control voltage signal EVN and the second control voltage signal ODD convert between the first voltage V1 and the second voltage V2, the first pull-down node control transistor T211 and the second pull-down node control transistor T212 are alternately in the on state.

[0103] In the second output stage t2 of the second display cycle T2, the first pull-down node control transistor T211 and the third pull-down node control transistor T223 are both turned off, which causes the first pull-down node PD1 to float and maintain a low level. In the second output stage t2 of the first display cycle T2, the second pull-down node control transistor T212 and the fourth pull-down node control transistor T224 are both turned off, which causes the second pull-down node PD2 to float and maintain a low level. As a result, the first pull-down node control circuit 21 and the second pull-down node control circuit 22 will continue to work under external interference when they are in the stopped working state, resulting in the problem of poor stopped state of the two node control circuits.

[0104] In this embodiment, in the second output stage t2 of the first display cycle T1, for the second pull-down node control circuit 22, the second control voltage signal ODD is a low-level voltage signal VGL, and the second pull-down node control circuit 22 stops working. The second pull-down node control transistor T212 is turned off; the pull-up node PU is a low-level voltage signal, and the fourth pull-down node control transistor T224 is also turned off. At the same time, since the first control voltage signal EVN is a high-level voltage signal VGH at this stage, the first pull-down node control circuit 21 works, the first pull-down node control transistor T211 is turned on, and the first pull-down node PD1 is connected to the first control voltage signal EVN, that is, the high-level voltage signal VGH through the first pull-down node control transistor T211. Since the gate of the fifth pull-down node control transistor T235 is electrically connected to the first pull-down node PD1, the fifth pull-down node control transistor T235 is turned on, and the second pull-down node PD2 will be connected to the first power supply signal, that is, the low-level voltage signal VGL. Therefore, when the first pull-down node PD1 is at a high level, the second pull-down node PD2 can be controlled to pass the low level voltage signal VGL, which can avoid the problem of the second pull-down node PD2 floating when the first pull-down node PD1 is at a high level voltage signal.

[0105] Similarly, in the second output stage t2 of the second display cycle T2, for the first pull-down node control circuit 21, the first control voltage signal EVN is a low-level voltage signal VGL, the first pull-down node control circuit 21 stops working, the first pull-down node control transistor T211 is turned off, the pull-up node PU is a low-level voltage signal, and the third pull-down node control transistor T223 is also turned off. At the same time, since the second control voltage signal ODD is a high-level voltage signal VGH at this stage, the second pull-down node control circuit 22 works, the second pull-down node control transistor T212 is turned on, and the second pull-down node PD2 will pass the second control voltage signal ODD, that is, a high-level voltage signal. Since the gate of the sixth pull-down node control transistor T236 is electrically connected to the second pull-down node PD2, the fifth pull-down node control transistor T235 is turned on, and the first pull-down node PD1 will pass the first power supply signal, that is, the low-level voltage signal VG. Therefore, when the second pull-down node PD2 is at a high level, the first pull-down node PD1 can be controlled to pass the low-level voltage signal VGL, which can avoid the problem of the first pull-down node PD1 floating when the second pull-down node PD2 is a high-level voltage signal.

[0106] refer to Fig. 9 , Fig.10 and Fig.13 In an embodiment of the present invention, the pull-up node control circuit 10 may further include a third pull-up node control transistor T131 and a fourth pull-up node control transistor T132; the second electrode, i.e., the drain, of the third pull-up node control transistor T131 is connected to the pull-up node PU, the first electrode, i.e., the source, receives the first power signal, and the gate is connected to the first pull-down node PD1; the second electrode, i.e., the drain, of the fourth pull-up node control transistor T132 is connected to the pull-up node PU, the first electrode, i.e., the source, receives the first power signal, and the gate is connected to the second pull-down node PD2.

[0107] Among them, the third pull-up node control transistor T131 and the fourth pull-up node control transistor T132 are mainly responsible for controlling the potential of the pull-up node PU through the potential of the pull-down node. Specifically, in the second stage t2 of the first display cycle T1, the first pull-down node PD1 is at a high level, and the third pull-up node control transistor T131 can be controlled to be turned on, thereby passing the first power supply signal, that is, the low-level voltage signal VGL, to the pull-up node PU, so that after the storage capacitor C1 is discharged, the pull-up node PU can be stabilized to a low-level state by passing the low-level voltage signal VGL. Similarly, in the second stage t2 of the second display cycle T2, the second pull-down node PD2 is at a high level, and the fourth pull-up node control transistor T132 can be controlled to be turned on, thereby passing the first power supply signal, that is, the low-level voltage signal VGL, to the pull-up node PU, so that after the storage capacitor C1 is discharged, the pull-up node PU can be stabilized to a low-level state by passing the low-level voltage signal VGL.

[0108] Fig.14 and Fig.15 is a schematic diagram of the structure of two gate drive units provided in an embodiment of the present invention, referring to Fig.14 and Fig.15 Optionally, the gate drive unit in the embodiment of the present invention may further include a reset circuit 50, which is used to control the gate drive signal output terminal GOUT and / or the pull-up node PU to reset under the control of the reset signal RESET. Specifically, the reset circuit includes an output reset transistor T51 and / or a pull-up node reset transistor T52; the first electrode, i.e., the source electrode, of the output reset transistor T51 is connected to the gate drive signal output terminal GOUT, and the first electrode, i.e., the source electrode, of the pull-up node reset transistor T52 is connected to the pull-up node PU; the second electrodes, i.e., the drain electrodes, of the output reset transistor T51 and the pull-up node reset transistor T52 both receive the first power supply signal, and the gates both receive the reset signal RESET.

[0109] The first power supply signal can be understood as a low-level voltage signal VGL. The reset circuit 50 is used to control the pull-up node PU and the gate drive signal output terminal GOUT to reset through the reset signal RESET. Specifically, when the RESET signal is at a high level, the output terminal reset transistor T51 and the pull-up node reset transistor T52 can be controlled to be turned on, thereby inputting the first power supply signal, i.e., the low-level voltage signal, into the gate drive signal output terminal GOUT and the pull-up node PU, thereby realizing the reset function.

[0110] Fig.16 is a schematic diagram of the structure of another gate driving unit provided by an embodiment of the present invention, referring to Fig.16 Optionally, the gate driving unit in the embodiment of the present invention may further include a carry signal output circuit 60, which is used to control the gate driving signal output by the carry signal output terminal Gx_OUT under the control of the voltage signal of the pull-up node PU, the voltage signal of the first pull-down node PD1 and the voltage signal of the second pull-down node PD2.

[0111] Specifically, the carry signal output circuit 60 includes a first carry control transistor T61, a second carry control transistor T62 and a third carry control transistor T63; the second electrode, i.e., the drain, of the first carry control transistor T61 receives the clock signal CK, the first electrode, i.e., the source, is connected to the carry signal output terminal Gx_OUT, and the gate is connected to the pull-up node PU; the second electrode, i.e., the drain, of the second carry control transistor T62 and the third carry control transistor T63 are both connected to the carry signal output terminal Gx_OUT, and the first electrode, i.e., the source, receives the first power supply signal; the gate of the second carry control transistor T62 is connected to the first pull-down node PD1, and the gate of the third carry control transistor T63 is connected to the second pull-down node PD2.

[0112] Among them, the first power supply signal can be understood as a low-level voltage signal VGL. Specifically, due to the same connection relationship, the first carry control transistor T61 actually has the same function as the first output control transistor T31, the second carry control transistor T62 has the same function as the first sub-output control transistor T32, and the third carry control transistor T63 has the same function as the first sub-output control transistor T32. In other words, the carry signal output circuit 60 is actually equal to the gate drive output circuit 30, and the carry signal Gx_OUT is completely consistent with the gate drive signal GOUT. The carry signal output circuit 60 is responsible for outputting the carry signal Gx_OUT as the gate drive signal GOUT of the current stage, which is provided to the input end of the next stage gate drive unit of the cascade, that is, the gate drive unit 100 of the n-1 stage outputs the carry signal Gx_OUT to the gate of the first pull-up node control transistor T11 of the n-1 stage gate drive unit 100, so as to drive the gate drive unit 100 of the next stage to work, and realize the sequential shift of the gate drive units 100 of each stage.

[0113] Based on the same inventive concept, an embodiment of the present invention further provides a display device. Fig.17 is a schematic diagram of the structure of a display device provided by an embodiment of the present invention, such as Fig.17 As shown, the display device includes a gate drive circuit (not shown) provided by any embodiment of the present invention. Therefore, the display device provided by the embodiment of the present invention has the corresponding beneficial effects of the display panel provided by the embodiment of the present invention, which will not be described in detail here. Exemplarily, the display device can be an electronic device such as a mobile phone, a computer, a smart wearable device (for example, a smart watch), and a vehicle-mounted display device, which is not limited by the embodiment of the present invention.

[0114] Note that the above are only preferred embodiments of the present invention and the technical principles used. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and that various obvious changes, readjustments, combinations and substitutions can be made by those skilled in the art without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in more detail through the above embodiments, the present invention is not limited to the above embodiments, and may include more other equivalent embodiments without departing from the concept of the present invention, and the scope of the present invention is determined by the scope of the appended claims.

Claims

1. A gate drive circuit, characterized in that: It includes a plurality of gate driving units; the gate driving unit includes: A pull-up node control circuit, used for controlling the potential of the pull-up node; A pull-down node control circuit, used to control the potential of the pull-down node under the control of the voltage signal of the pull-up node, the control voltage signal and the fixed voltage signal; The pull-down node control circuit includes a pull-down node control transistor, a first electrode of the pull-down node control transistor is electrically connected to the pull-down node; The gate of the pull-down node control transistor receives the control voltage signal, the second electrode receives the fixed voltage signal, and during at least part of the time, the control voltage signal V and the fixed voltage signal VDC satisfy: V<VDC; or, the gate of the pull-down node control transistor receives the fixed voltage signal, the second electrode receives the control voltage signal, and during at least part of the time, the fixed voltage signal VDC and the control voltage signal V satisfy: VDC<V; The gate drive output circuit is used to control the gate drive signal outputted from the gate drive signal output terminal under the control of the voltage signal of the pull-up node and the voltage signal of the pull-down node.

2. The gate driving circuit according to claim 1, characterized in that: The pull-down node includes a first pull-down node and a second pull-down node; the pull-down node control circuit includes a first pull-down node control circuit and a second pull-down node control circuit; the control voltage signal includes a first control voltage signal and a second control voltage signal; The first pull-down node control circuit is used to control the potential of the first pull-down node under the control of the voltage signal of the pull-up node, the first control voltage signal and the fixed voltage signal; The second pull-down node control circuit is used to control the potential of the second pull-down node under the control of the voltage signal of the pull-up node, the second control voltage signal and the fixed voltage signal; The first pull-down node control circuit includes a first pull-down node control transistor, a first electrode of the first pull-down node control transistor is electrically connected to the first pull-down node; a gate of the first pull-down node control transistor receives the first control voltage signal, and a second electrode receives the fixed voltage signal, or a gate of the first pull-down node control transistor receives the fixed voltage signal, and a second electrode receives the first control voltage signal; The second pull-down node control circuit includes a second pull-down node control transistor, a first electrode of the second pull-down node control transistor is electrically connected to the second pull-down node; a gate of the second pull-down node control transistor receives the second control voltage signal, and a second electrode receives the fixed voltage signal, or a gate of the second pull-down node control transistor receives the fixed voltage signal, and a second electrode receives the second control voltage signal; wherein the first control voltage signal and the second control voltage signal switch between a first voltage and a second voltage over time, and one of the two is the first voltage V1, and the other is the second voltage V2, V1<V2; The gate drive output circuit is used to control the gate drive signal outputted from the gate drive signal output terminal under the control of the voltage signal of the pull-up node, the voltage signal of the first pull-down node and the voltage signal of the second pull-down node.

3. The gate driving circuit according to claim 2, characterized in that: The fixed voltage signal VDC, the first voltage V1 and the second voltage V2 satisfy: V1<VDC<V2.

4. The gate driving circuit according to claim 2, characterized in that: The first pull-down node control circuit further includes a third pull-down node control transistor, and the second pull-down node control circuit further includes a fourth pull-down node control transistor; The gates of the first pull-down node control transistor and the second pull-down node control transistor both receive the fixed voltage signal, the second electrode of the first pull-down node control transistor receives the first control voltage signal, and the second electrode of the second pull-down node control transistor receives the second control voltage signal; A second electrode of the third pull-down node control transistor is connected to the first pull-down node, and a second electrode of the fourth pull-down node control transistor is connected to the second pull-down node; The gates of the third pull-down node control transistor and the fourth pull-down node control transistor are both connected to the pull-up node, and the first electrodes receive the first power signal.

5. The gate driving circuit according to claim 2, characterized in that: The first pull-down node control circuit further includes a third pull-down node control transistor, and the second pull-down node control circuit further includes a fourth pull-down node control transistor; The second electrodes of the first pull-down node control transistor and the second pull-down node control transistor both receive the fixed voltage signal, the gate of the first pull-down node control transistor receives the first control voltage signal, and the gate of the second pull-down node control transistor receives the second control voltage signal; A second electrode of the third pull-down node control transistor is connected to the first pull-down node, and a second electrode of the fourth pull-down node control transistor is connected to the second pull-down node; The gates of the third pull-down node control transistor and the fourth pull-down node control transistor are both connected to the pull-up node, and the first electrodes receive the first power signal.

6. The gate driving circuit according to claim 5, characterized in that: The first pull-down node control circuit further includes a fifth pull-down node control transistor; the gate of the fifth pull-down node control transistor is connected to the second pull-down node, the second electrode is connected to the first pull-down node, and the first electrode receives the first power supply signal; The second pull-down node control circuit further includes a sixth pull-down node control transistor; The gate of the sixth pull-down node control transistor is connected to the first pull-down node, the second electrode is connected to the second pull-down node, and the first electrode receives the first power signal.

7. The gate drive circuit according to claim 4 or 5, characterized in that: The ratio of the width-to-length ratio of the third pull-down node control transistor to the width-to-length ratio of the first pull-down node control transistor is in the range of 1.6 to 2; and / or, The ratio of the width to length ratio of the fourth pull-down node control transistor to the width to length ratio of the second pull-down node control transistor is in the range of 1.6-2.

8. The gate driving circuit according to claim 2, characterized in that: A plurality of the gate driving units are cascaded in sequence; The pull-up node control circuit includes a first pull-up node control transistor and a second pull-up node control transistor; The second electrode of the first pull-up node control transistor receives a forward scanning control signal, the first electrode is connected to the pull-up node, and the gate receives a gate driving signal output by the gate driving signal output terminal of the gate driving unit of the previous stage of the cascade connection; The second electrode of the second pull-up node control transistor receives a reverse scan control signal, the first electrode is connected to the pull-up node, and the gate receives a gate drive signal output by the gate drive signal output terminal of the next stage of the gate drive unit in cascade connection; Wherein, in the same gate driving unit, the polarity of the forward scanning control signal is opposite to the polarity of the reverse scanning control signal.

9. The gate driving circuit according to claim 8, characterized in that: The pull-up node control circuit also includes a third pull-up node control transistor and a fourth pull-up node control transistor; The second electrode of the third pull-up node control transistor is connected to the pull-up node, the first electrode receives the first power supply signal, and the gate is connected to the first pull-down node; The second electrode of the fourth pull-up node control transistor is connected to the pull-up node, the first electrode receives the first power signal, and the gate is connected to the second pull-down node.

10. The gate driving circuit according to claim 1, characterized in that: The gate drive output circuit includes a first output control transistor and a second output control transistor; The second electrode of the first output control transistor receives the clock signal, the first electrode is connected to the gate drive signal output terminal, and the gate is connected to the pull-up node; The second electrode of the second output control transistor is connected to the gate drive signal output terminal, the first electrode receives the first power supply signal, and the gate is connected to the pull-down node.

11. The gate driving circuit according to claim 1, characterized in that: The gate drive output circuit further includes an energy storage circuit, which is connected to the pull-up node and is used to maintain the potential of the pull-up node.

12. The gate driving circuit according to claim 11, characterized in that: The energy storage circuit includes a storage capacitor, a first plate of the storage capacitor is connected to the pull-up node, and a second plate of the storage capacitor is connected to the gate drive signal output terminal.

13. The gate driving circuit according to claim 1, characterized in that: It also includes a reset circuit, which is used to control the gate drive signal output terminal and / or the pull-up node to reset under the control of a reset signal.

14. The gate driving circuit according to claim 13, characterized in that: The reset circuit includes an output reset transistor and / or a pull-up node reset transistor; The first electrode of the output reset transistor is connected to the gate drive signal output terminal, and the first electrode of the pull-up node reset transistor is connected to the pull-up node; the second electrodes of the output reset transistor and the pull-up node reset transistor both receive the first power supply signal, and the gates both receive the reset signal.

15. The gate driving circuit according to claim 2, characterized in that: It also includes a carry signal output circuit for controlling the gate drive signal output by the carry signal output terminal under the control of the voltage signal of the pull-up node, the voltage signal of the first pull-down node and the voltage signal of the second pull-down node.

16. The gate driving circuit according to claim 15, characterized in that: The carry signal output circuit includes a first carry control transistor, a second carry control transistor and a third carry control transistor; The second electrode of the first carry control transistor receives the clock signal, the first electrode is connected to the carry signal output terminal, and the gate is connected to the pull-up node; The second electrodes of the second carry control transistor and the third carry control transistor are both connected to the carry signal output terminal, and the first electrodes both receive the first power supply signal; the gate of the second carry control transistor is connected to the first pull-down node, and the gate of the third carry control transistor is connected to the second pull-down node.

17. A driving method for a gate driving circuit, characterized in that: Applicable to the gate driving circuit according to any one of claims 1 to 16, wherein the driving process of the gate driving circuit includes a first output stage and a second output stage; The driving method comprises: In the first output stage, the pull-up node control circuit controls the potential of the pull-up node to be an effective level; the gate drive output circuit controls the gate drive signal outputted from the gate drive signal output terminal to be a first gate drive signal under the control of the voltage signal of the pull-up node; In the second output stage, the pull-down node control circuit controls the potential of the pull-down node to be a valid level under the control of the voltage signal of the pull-up node, the control voltage signal and the fixed voltage signal; the gate drive output circuit controls the gate drive signal output from the gate drive signal output end to be a second gate drive signal under the control of the voltage signal of the pull-down node.

18. The driving method according to claim 17, characterized in that: The pull-down node includes a first pull-down node and a second pull-down node; the pull-down node control circuit includes a first pull-down node control circuit and a second pull-down node control circuit; the control voltage signal includes a first control voltage signal and a second control voltage signal; The first pull-down node control circuit is used to control the potential of the first pull-down node under the control of the voltage signal of the pull-up node, the first control voltage signal and the fixed voltage signal; The second pull-down node control circuit is used to control the potential of the second pull-down node under the control of the voltage signal of the pull-up node, the second control voltage signal and the fixed voltage signal; The first pull-down node control circuit includes a first pull-down node control transistor, a first electrode of the first pull-down node control transistor is electrically connected to the first pull-down node; a gate of the first pull-down node control transistor receives the first control voltage signal, and a second electrode receives the fixed voltage signal, or a gate of the first pull-down node control transistor receives the fixed voltage signal, and a second electrode receives the control voltage signal; The second pull-down node control circuit includes a second pull-down node control transistor, a first electrode of the second pull-down node control transistor is electrically connected to the second pull-down node; a gate of the second pull-down node control transistor receives the second control voltage signal, and a second electrode receives the fixed voltage signal, or a gate of the second pull-down node control transistor receives the fixed voltage signal, and a second electrode receives the control voltage signal; wherein the first control voltage signal and the second control voltage signal switch between a first voltage and a second voltage over time, and one of the two is the first voltage V1, and the other is the second voltage V2, V1<V2; The gate drive output circuit is used to control the gate drive signal outputted from the gate drive signal output terminal under the control of the voltage signal of the pull-up node, the voltage signal of the first pull-down node and the voltage signal of the second pull-down node; The driving process of the gate driving circuit includes a first display cycle and a second display cycle; the first display cycle and the second display cycle both include the first output stage and the second output stage; The driving method comprises: In the first output stage of the first display period and the second display period, the pull-up node control circuit controls the potential of the pull-up node to be a valid level; the gate drive output circuit controls the gate drive signal outputted from the gate drive signal output terminal to be a first gate drive signal under the control of the voltage signal of the pull-up node; In the second output stage of the first display period, the first pull-down node control circuit controls the potential of the first pull-down node to be a valid level under the control of the voltage signal of the pull-up node, the first control voltage signal and the fixed voltage signal; the gate drive output circuit controls the gate drive signal outputted from the gate drive signal output terminal to be a second gate drive signal under the control of the voltage signal of the first pull-down node; In the second output stage of the second display cycle, the second pull-down node control circuit controls the potential of the second pull-down node to be a valid level under the control of the voltage signal of the pull-up node, the second control voltage signal and the fixed voltage signal; the gate drive output circuit controls the gate drive signal output from the gate drive signal output end to be a second gate drive signal under the control of the voltage signal of the second pull-down node.

19. The driving method according to claim 18, characterized in that: The driving method further comprises: In the second output stage of the first display period, the second pull-down node control circuit controls the potential of the second pull-down node to be an invalid level under the control of the voltage signal of the pull-up node, the second control voltage signal and the fixed voltage signal; In the second output phase of the second display period, the first pull-down node control circuit controls the potential of the first pull-down node to an invalid level under the control of the voltage signal of the pull-up node, the first control voltage signal and the fixed voltage signal.

20. The driving method according to claim 17, characterized in that: The gate drive output circuit further includes a tank circuit, wherein the tank circuit is connected to the pull-up node; The first output stage includes an input stage and an output stage; the driving method further includes: In the input stage, the pull-up node control circuit charges the energy storage circuit through the pull-up node; In the output stage, the energy storage circuit is self-discharged to maintain the potential of the pull-up node at an effective level, and the gate drive output circuit controls the gate drive signal output from the gate drive signal output end to be the first gate drive signal under the control of the voltage signal of the pull-up node.

21. A display panel, characterized in that: Comprising the gate drive circuit as described in any one of claims 1-16.

22. A display device, characterized in that: Comprising the display panel as claimed in claim 21.

Images