Low dielectric film based on layered compound and preparation method and application thereof

Abstract

The invention relates to the technical field of integrated circuit manufacturing, and discloses a low-dielectric film based on a layered compound and a preparation method and application thereof. The invention provides a layered compound: [Mx (OH) y] z + [(An-) z / n]. MH2O or [M1x1M2x2 (OH) y] z + [(An-) z / n]. MH2O, where [Mx (OH) y] z + or [M1x1M2x2 (OH) y] z + constitutes a positively charged laminate, an anion An-can be inserted by the expanded interlayer spacing; the invention further discloses a preparation method of the low-dielectric film based on the layered compound. The film has excellent dielectric properties (klt; 1.9), a low dielectric loss (lt; 0.02), the insulation property is good, and meanwhile, the excellent Young's modulus (YMgt; 20 GPa), the mechanical strength meets the requirements of a rear-end interconnection medium, and the material has a wide practical application prospect in the chip rear-end interconnection industry; meanwhile, the material can be used as a transistor insulating layer material, interface traps of a thin film transistor insulating layer and an active layer are reduced, and the carrier mobility and on-off ratio of a transistor are improved.

Description

Technical Field

[0001] The invention belongs to the technical field of integrated circuit manufacturing, and relates to a low dielectric material with a layered porous structure, which can be used as an interlayer insulating film of a semiconductor element or as a substrate of a circuit component, or applied to a chip back-end interconnection medium. Background Art

[0002] With the continuous popularization of 5G technology and intelligent technology, chips are the core of future scientific and technological progress. An insulating material is needed in the back-end structure of the chip to separate the conductive parts (copper interconnects on the chip) from each other and mechanically support the chip structure. In the past, porous organic silica glass was generally used, with k = 2.4-3.0; elastic modulus 5-10GPa, which is still far from the ideal dielectric performance. With the miniaturization of integrated circuits and more dense packaging, the width and spacing of interconnects are constantly decreasing, so the parasitic effects caused by interconnect resistance (R) and capacitance (C) are becoming more and more obvious. It is urgent to develop materials with lower dielectric constants (k <2.4), high modulus (>15GPa) and high thermal stability (400°C), hydrophobicity, nano thickness, good adhesion, etc.

[0003] Porous materials have been widely studied as interconnect dielectric layers due to their excellent dielectric properties. However, due to their high degree of crystallinity and insolubility, the film-forming process is difficult and there are often grain boundary defects and intergranular cracks. Layered compounds retain their porous properties, which hinders ion conduction and produces low polarization. They also have the characteristics of low crystallinity and easy processing into films, and are expected to be used as new low-dielectric materials. 2 For example, the layers are randomly stacked along the c-axis, and there are intercalated substances (water or anions) in the interlayer channels. 2 Anion exchange is easy to occur. During the exchange process, due to the different volumes of anion space, the interlayer spacing and crystallinity will change. At present, only a few studies have reported the dielectric properties of α-phase compounds as electrode materials. There are no related literature reports on the application of α-phase compounds in ultra-low dielectric films. However, according to theoretical calculations, its static dielectric constant is ε ⊥ =3.55, ε \\ =3.30, which has great potential as a new type of interlayer dielectric. At the same time, due to its special interlayer structure, anions connect each layer to ensure stable mechanical strength. In addition, this material is different from other porous materials and has excellent thermal stability, ensuring that it can still work normally at high temperatures.

[0004] In view of the shortcomings of current interconnect media, the present invention proposes an ultra-low dielectric thin film material based on layered compounds, which combines the advantages of ultra-low dielectric, high mechanical strength, adjustable film thickness, and easy scale-up preparation. Summary of the invention

[0005] In view of the shortcomings of the prior art and based on the current requirements for the performance of the back-end interconnect dielectric layer, the present invention proposes a low dielectric film based on layered compounds and a preparation method and application thereof, which has excellent dielectric properties, low dielectric loss, good insulation, high breakdown field strength, and maintains excellent Young's modulus.

[0006] In order to achieve the above object, the present invention provides the following technical solutions: As a first aspect, a low dielectric film based on a layered compound is provided, wherein the layered compound is [M x (OH) y ] z+ [(A n- ) z / n ].mH 2 O or [M 1x1 M 2 x2 (OH) y ] z+ [(A n- ) z / n ].mH 2 O; among them, M, M 1 , M 2 A is a metal ion. n- is the interlayer anion, x, x 1 、x 2 , y, z, m, n are non-negative numbers; x (OH) y ] z+ or [M 1 x1 M 2 x2 (OH) y ] z+ Forming positively charged layers, anions are inserted into the expanded interlayer spacing, and the interlayer anions A n- The layered structure is supported by van der Waals force; the low dielectric film is formed by spin coating deposition of the layered compound.

[0007] Furthermore, the metal ion is Li + , Ca 2+ Mg 2+ 、Al 3+ , Fe 2+ 、Co 2+ 、Ni 2+ , Cu 2+ 、Zn 2+ , Mn 2+ , Y 2+ , Yb 2+ One or more of .

[0008] Furthermore, the anion is SiF 6 2- , GeF 6 2- 、TiF 6 2- 、NbOF 5 2- 、[(CH 2 ) 4 (CO 2 )] 2- 、SO 4 2- , CO 3 2- 、NO 3 - ,PO 4 3- , Cl - Br - , one or more surfactants with organic groups.

[0009] Furthermore, the surfactant with an organic group includes SDS, CTAB, SDBS, and Tween 80.

[0010] As a second aspect, the present invention provides a method for preparing a low dielectric film based on a layered compound, comprising the following steps:

[0011] The layered compound is fully dispersed in an organic solvent to prepare a spin coating solution;

[0012] A substrate is provided, and a spin coating liquid is spin-coated on the substrate.

[0013] Preferably, the spin coating speed is 1000-8000 rpm, the spin coating time is 30-60 s, and the concentration of the spin coating liquid is 0.5-15 mg / ml.

[0014] Furthermore, the layered compound is prepared by the following method: dissolving metal salt powder in an organic solvent to make the metal salt concentration be 0.02-0.1 mol / L, adding an organic base to precipitate the layered compound, and washing to obtain the layered compound;

[0015] Furthermore, the organic solvent is an alcohol solvent, the organic base is selected from aliphatic amines and aromatic amines, and the metal ion in the metal salt is selected from Li + , Ca 2+ Mg 2+ 、Al 3+ , Fe 2+ 、Co 2+ 、Ni 2+ , Cu 2+ 、Zn 2+ , Mn2+ , Y 2+ , Yb 2+ , anions are selected from SiF 6 2- , GeF 6 2- 、TiF 6 2- 、NbOF 5 2- 、[(CH 2 ) 4 (CO 2 )] 2- 、SO 4 2- , CO 3 2- 、NO 3 - ,PO 4 3- , Cl - Br - , surfactants with organic groups, the surfactants with organic groups include SDS, CTAB, SDBS, and Tween 80.

[0016] Furthermore, the film obtained by the spin coating method is subjected to supercritical CO 2 Extraction to extract the small organic molecules between the layers.

[0017] Preferably, the extraction temperature is 60-100° C., the extraction pressure is 10-14 MPa, and the extraction time is 2-4 h.

[0018] As a third aspect, the present invention provides a method for patterning the low dielectric film, wherein patterning is performed by photolithography, dry and wet etching, and deposition, and the method comprises the following steps:

[0019] coating the low dielectric film on a substrate to form a dense film layer on the substrate;

[0020] Spin coating a photoresist on the low dielectric film;

[0021] The photoresist layer is exposed through a photomask, and a specific pattern can be formed after development;

[0022] The required material can be deposited on the pattern, and a specific pattern can be formed on the low dielectric film after stripping; or the developed low dielectric film can be etched by dry or wet methods to form a groove.

[0023] As a fourth aspect, the present invention provides an application of the low dielectric film as described above: as an interlayer dielectric or a substrate of a circuit component for back-end interconnection of a chip.

[0024] As a fifth aspect, the present invention further provides a thin film transistor: comprising an active layer (03), an insulating layer (02), a gate electrode (01), a source electrode (04), and a drain electrode (05), wherein the insulating layer (02) comprises a first insulating layer (021) and a second insulating layer (022) formed by the low dielectric thin film, which are sequentially located on the gate electrode (01); the active layer (03) is located on the insulating layer (02), and the source electrode (04) and the drain electrode (05) are located on the active layer (03); or the source electrode (04) and the drain electrode (05) are located on the insulating layer (02), and then covered with a layer of the active layer (03);

[0025] Or the low dielectric film is located on the gate (01) as an insulating layer (02), the active layer (03) is located on the insulating layer (02), and the source (04) and the drain (05) are located on the active layer (03); or the source (04) and the drain (05) are located on the insulating layer (02), and then covered with an active layer (03).

[0026] The beneficial effects of the present invention are as follows:

[0027] (1) The present invention proposes a new ultra-low dielectric material based on layered compounds, which has high porosity. Supercritical extraction can replace interlayer organic small molecules, while increasing the interlayer spacing, increasing the porosity of the film, and hindering ion conduction, greatly reducing the conductivity, ensuring a low dielectric constant. In addition, the interlayer anions contain chemical bonds with low polarizability, such as Si-F bonds. The low-crystalline compound colloids are densely stacked, and the interlayer anion columns support the layered structure in the microstructure, ensuring that the film also has excellent mechanical strength. It achieves a combination of ultra-low dielectric (k<2.0), high mechanical strength (YM>20GPa), adjustable film thickness, easy to scale up and prepare, and the performance is much higher than the dielectric materials reported in the current literature. In practical applications, it also has good insulation and a certain breakdown field strength. And it can still maintain a good working state at a high temperature of 300°C, so that the film can be used as an interlayer dielectric for chip back-end interconnection.

[0028] (2) The present invention proposes a new method for preparing layered compound thin films. A simple spin coating method can prepare a continuous and dense dielectric film with adjustable thickness and smooth surface. The spin coating method can realize the preparation of wafer-scale dielectric films, which is conducive to large-scale industrial production.

[0029] (3) Patterning is achieved on the film surface by photolithography, dry and wet etching. It has broad practical application prospects in the chip back-end interconnection industry. At the same time, the present invention provides an application of ultra-low dielectric film in transistors, which reduces the interface traps between the insulating layer and the active layer of the thin film transistor and improves the carrier mobility and switching ratio of the transistor. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 A schematic diagram of the structure of a low dielectric thin film based on layered compounds and a schematic diagram of back-end interconnection of the present invention;

[0031] Figure 2 is the XRD diagram of Example 1 of the present invention;

[0032] Figure 3 The performance diagram of Example 1 of the present invention, wherein (a) and (b) are low dielectric film morphologies; (c) a diagram showing the relationship between dielectric constant and frequency of Example 1; (d) a diagram showing the relationship between dielectric loss and frequency; (e) breakdown field strength performance; (f) a diagram showing the relationship between leakage current and voltage;

[0033] Figure 4 The dielectric performance diagrams of Examples 2-5 of the present invention include (a) a diagram showing the relationship between dielectric constant and frequency; (b) a diagram showing the relationship between dielectric loss and frequency;

[0034] Figure 5 Graph showing the mechanical properties of Example 4 of the present invention, wherein (a) and (b) are Young's modulus and hardness of the film, respectively;

[0035] Figure 6 The dielectric performance diagram of Example 6 of the present invention, wherein (a) is a diagram showing the relationship between the dielectric constant and the frequency of Example 6; (b) is a diagram showing the relationship between the dielectric loss and the frequency of Example 6;

[0036] Figure 7 Graphs of dielectric properties of Example 7 of the present invention, (a) and (b) are graphs showing the relationship between dielectric constant, dielectric loss and frequency of Example 7, respectively;

[0037] Figure 8 is the XRD pattern of Example 8 of the present invention;

[0038] Fig. 9 : are performance diagrams of Example 8 of the present invention, wherein (a) and (b) are SEM images of the thin film; (c) is a diagram showing the relationship between the dielectric constant and the frequency of Example 8; (d) is a diagram showing the relationship between the dielectric loss and the frequency; (e) and (f) are Young's modulus and hardness of Example 8 of the present invention;

[0039] Fig.10 is the XRD pattern of Example 9 of the present invention;

[0040] Fig.11 The performance diagram of Example 9 of the invention, wherein (a) and (b) are the film morphology; (c) is the relationship between the dielectric constant and the frequency of Example 9; (d) is the relationship between the dielectric loss and the frequency; (e) and (f) are the Young's modulus and the hardness of Example 9 of the invention;

[0041] Fig.12 is a device structure diagram of embodiment 10 of the present invention;

[0042] Fig.13 is a device structure diagram of embodiment 11 of the present invention;

[0043] Fig.14 is a device structure diagram of embodiment 12 of the present invention;

[0044] Fig.15 This is a device structure diagram of Example 13 of the present invention. DETAILED DESCRIPTION

[0045] The present invention will be further described below in conjunction with specific embodiments. It should be understood that these embodiments are only used to illustrate the present invention and are not intended to limit the scope of the present invention. In addition, it should be understood that after reading the content taught by the present invention, those skilled in the art can make various changes or modifications to the present invention, and these equivalent forms fall within the scope limited by the appended claims of the application equally.

[0046] Unless otherwise specified, the raw materials required for preparation are all common commercially available products. The silicon wafer used in the present invention was purchased from Shanghai Zixi Electronic Technology Co., Ltd. and is highly doped p++. The silicon dioxide wafer was purchased from Hefei Kejing Material Technology Co., Ltd. and is 300nm SiO 2 , N-type doping. The coating machine was purchased from Shanghai Sanyan Technology Co., Ltd., model SYSC-100A.

[0047] Example 1 α-Ni(OH) 2 -SiF 6

[0048] (1) α-Ni(OH) 2 -SiF 6 Preparation: 1 mmol of nickel hexafluorosilicate hexahydrate NiSiF 6 .6H 2 O is added to 50ml methanol and stirred until uniform, and 2-5mmol triethylamine is added until uniformly mixed. The above process is carried out at room temperature. Finally, 4-8mmol pyrazine is added and stirred at 50-60℃ for 1-2 days. After the reaction is completed, the supernatant is removed by centrifugation (3000-10000rpm, 15-30min), and fresh methanol solution is added and soaked for 12h. Repeat the above washing process 3 times.

[0049] (2) α-Ni(OH) 2 -SiF 6 Preparation of spin coating solution: Take the above wet solid and fully disperse it in methanol solvent to prepare a 5 mg / ml spin coating solution.

[0050] (3) Surface treatment of silicon wafer: The surface of the silicon wafer is ultrasonically cleaned in acetone, isopropanol, and deionized water for 15-30 minutes, and then blown dry with high-purity nitrogen for later use.

[0051] (4) α-Ni(OH) 2 -SiF 6 Spin coating: Spin coating liquid on the silicon wafer and spin at 2000 rpm (acceleration 200 rpm / s) for 30-60s.

[0052] (5) Post-treatment: The spin-coated film is kept in a vacuum oven at 60-100°C for 6-12 hours (drying). Electrodes with different patterns are constructed on the film surface by photolithography and magnetron sputtering for subsequent dielectric performance testing. 2 Extract the organic small molecules between the layers at an extraction temperature of 60-100°C, an extraction pressure of 10-14MPa, and an extraction time of 2-4h. High temperature thermal annealing at an annealing temperature of 150°C for 3-24h.

[0053] The dielectric constant of the material is measured by LCR meter. According to the parallel plate capacitor theory, the dielectric constant of the material is k = Cs × d / (ε 0 ×S), where ε 0 represents the vacuum dielectric constant, S represents the area of ​​the top circular electrode, and d is the average thickness of the film. The thickness of the dielectric film obtained is 33nm. 6 At Hz frequency, the dielectric constant is 1.61. The dielectric loss is kept within the range of less than 0.02, and there is no obvious energy loss. Supercritical extraction can replace the interlayer organic small molecules, while increasing the interlayer spacing, increasing the porosity of the film, and ensuring a low dielectric constant. In addition, the interlayer anions contain Si-F bonds with low polarizability.

[0054] The leakage of the film was measured by a semiconductor parameter analyzer. The leakage current was less than 1nA in the bias voltage range of -2V to +2V, indicating that the dielectric has excellent insulation properties. Its breakdown field strength is 1.1MV / cm, and the dielectric layer is strong and durable.

[0055] Example 2-3

[0056] α-Ni(OH) was prepared according to the method of Example 1 2 -SiF 6 The difference is that the spin coating speed is 1000 rpm and 3000 rpm respectively (other conditions not specified are consistent with Example 1). The obtained film thickness is 39.3 nm and 26.4 nm respectively, and the dielectric properties are shown in Figure 4 , the film thickness decreases with the increase of spin coating speed, the film quality remains unchanged, and the dielectric properties measured for different film thicknesses remain consistent. This is because different spin coating speeds do not affect the composition and layered structure of the film.

[0057] Embodiment 4-5

[0058] α-Ni(OH) was prepared according to the method of Example 1 2 -SiF 6 The difference is the concentration of the spin coating solution, 4-5 are 10mg / ml and 15mg / ml respectively (other conditions not specified are consistent with Example 1). The obtained film thicknesses are 53.5nm and 61.5nm respectively, and the dielectric properties are shown in Figure 4 The film thickness increases with the increase of spin coating liquid concentration, and the dielectric constant of the film of 61.5nm is slightly higher than other values. This is because the surface roughness of the film increases slightly with the increase of film thickness, which causes the dielectric constant value measured based on the MIM structure to fluctuate.

[0059] The mechanical properties of the film were obtained by continuous depth testing with nanoindentation. The Young's modulus of Example 4 was 28.3 GPa and the hardness was 2.0 GPa, which met the requirements of the back-end interconnect medium. The low-crystalline nickel hydroxide colloid was densely packed, and the interlayer anion columns on the microstructure supported the layered structure, ensuring that the film also had excellent mechanical strength.

[0060] Embodiment 6-7

[0061] α-Ni(OH) was prepared according to the method of Example 1 2 -SiF 6 , the difference is that the thermal annealing temperature is 250°C and 300°C respectively in 6-7 (other conditions not specified are consistent with Example 1), and the dielectric properties are shown in Figure 6 , 7 After high temperature treatment, the dielectric constant increases slightly but is still within the reliable range, which is because the high temperature will compress the interlayer spacing and reduce the porosity.

[0062] Example 8 α-Co(OH) 2 -GeF 6

[0063] (1) α-Co(OH) 2 -GeF 6 Preparation: 1 mmol of cobalt hexafluorosilicate hexahydrate CoGeF 6 6H 2 O is added to 50ml methanol and stirred until uniform, and 2-5mmol triethylamine is added until uniformly mixed. The above process is carried out at room temperature. Finally, 4-8mmol pyrazine is added and stirred at 50-60℃ for 1-2 days. After the reaction is completed, the supernatant is removed by centrifugation (10000rpm, 30min), and fresh methanol solution is added and soaked for 12h. Repeat the above washing process 3 times.

[0064] (2) α-Co(OH) 2 -GeF6 Preparation of spin coating solution: fully disperse the above wet solid in methanol solvent to prepare a spin coating solution of 1-15 mg / ml.

[0065] (3) Surface treatment of silicon wafer: The surface of the silicon wafer is ultrasonically cleaned in acetone, isopropanol, and deionized water for 15-30 minutes, and then blown dry with high-purity nitrogen for later use.

[0066] (4) α-Co(OH) 2 -GeF 6 Spin coating: Add the spin coating liquid on the silicon wafer and spin at a speed of 1000-8000rpm (acceleration 200rpm / s) for 30-60s.

[0067] (5) Post-treatment: Spin-coated α-Co(OH) 2 -GeF 6 The film is kept in a vacuum oven at 60-100°C for 6-12 hours. Electrodes with different patterns are constructed on the film surface by photolithography and magnetron sputtering for subsequent dielectric performance testing. 2 Extract the organic small molecules between the layers, the extraction temperature is 60-100°C, the extraction pressure is 10-14MPa, and the extraction time is 2-4h. High temperature thermal annealing, the annealing temperature is 60-120°C, and the time is 3-24h.

[0068] The dielectric constant of the material was measured by LCR meter, and the thickness of the dielectric film was 65nm. 6 At Hz frequency, the dielectric constant is 4.11. The dielectric loss is basically kept within the range of less than 0.05, and there is no obvious energy loss. There is still room for further improvement in dielectric performance.

[0069] The mechanical properties of the membrane were obtained by continuous depth testing with nanoindentation, with a Young's modulus of 30.5 GPa and a hardness of 2.2 GPa, meeting the requirements of back-end interconnect media.

[0070] Example 9 α-Ni(OH) 2 -GeF 6

[0071] (1) α-Ni(OH) 2 -GeF 6 Preparation: 1 mmol nickel hexafluorosilicate hexahydrate NiGeF 6 6H 2O was added to 50 ml of methanol and stirred until uniform, and 2-5 mmol of triethylamine was added until uniformly mixed. The above process was carried out at room temperature. Finally, 4-8 mmol of pyrazine was added and the mixture was placed in a reactor at 150°C for 6 hours. After the reaction was completed, the supernatant was removed by centrifugation (10000 rpm, 30 min), and fresh methanol solution was added and soaked for 12 hours. The above washing process was repeated 3 times.

[0072] (2) α-Ni(OH) 2 -GeF 6 Preparation of spin coating solution: fully disperse the above wet solid in methanol solvent to prepare a 1-10 mg / ml spin coating solution.

[0073] (3) Silicon wafer surface treatment: The silicon wafer surface is ultrasonically cleaned in acetone, isopropanol, and deionized water for 15-30 minutes, and then blown dry with high-purity nitrogen for later use

[0074] (4) α-Ni(OH) 2 -GeF 6 Spin coating: Add the spin coating liquid on the silicon wafer and spin at a speed of 1000-8000rpm (acceleration 200rpm / s) for 30-60s.

[0075] (5) Post-treatment: Spin-coated α-Ni(OH) 2 -GeF 6 The film is kept in a vacuum oven at 60-100°C for 6-12 hours. Electrodes with different patterns are constructed on the film surface by photolithography and magnetron sputtering for subsequent dielectric performance testing. 2 Extract the organic small molecules between the layers, the extraction temperature is 60-100°C, the extraction pressure is 10-14MPa, and the extraction time is 2-4h. High temperature thermal annealing, the annealing temperature is 60-120°C, and the time is 3-24h.

[0076] The dielectric constant of the material was measured by LCR meter, and the thickness of the dielectric film was 50nm. 6 At Hz frequency, the dielectric constant is 1.95. The dielectric loss is basically kept within the range of less than 0.05, and there is no obvious energy loss.

[0077] The mechanical properties of the membrane were obtained by continuous depth testing with nanoindentation, with a Young's modulus of 35.8 GPa and a hardness of 1.0 GPa, meeting the requirements of back-end interconnect media.

[0078] Example 10

[0079] Thin film transistor 100, combined with Fig.12As shown, it includes an active layer 03, source and drain electrodes 04 and 05 electrically connected to the active layer 03, a first insulating layer 021 and a second insulating layer 022 corresponding to the active layer, and a gate 01. The ultra-low dielectric film is located between the active layer 03 and the first insulating layer 021 as the second insulating layer 022, and the two together constitute the insulating layer 02 of the transistor 100. The low dielectric film can reduce the energy disorder between the insulating layer and the active layer, reduce interface traps, and thus improve the electrical performance of the transistor.

[0080] The present invention provides a method for manufacturing a thin film transistor, comprising the following steps:

[0081] S1. Provide a substrate (silicon dioxide wafer), in which highly doped silicon is used as gate 01, SiO 2 As a first insulating layer 021;

[0082] S2, forming a second insulating layer 022 on the first insulating layer 021;

[0083] S3, forming an active layer 03 on the second insulating layer 022;

[0084] S4 , making source and drain electrodes 04 and 05 on the active layer 03 .

[0085] First, the SiO 2 The highly doped silicon wafer is treated to be hydrophilic, and an ultra-low dielectric film is formed on the substrate by spin coating as the second insulating layer 022. After the insulating layer 02 is made, the active layer 03 is made by atomic layer deposition or spin coating. The active layer can be made of materials such as metal oxides and organic semiconductors. Finally, source and drain electrodes 04 and 05 are made on the active layer by magnetron sputtering, electron beam evaporation, etc. The electrodes can be made of highly conductive materials such as Au, Pt, and Al.

[0086] Embodiment 11

[0087] Thin film transistor 200, combined with Fig.13 As shown, the production method comprises the following steps:

[0088] S1. Provide a substrate (silicon dioxide wafer), in which highly doped silicon is used as gate 01, SiO 2 As a first insulating layer 021;

[0089] S2, forming a second insulating layer 022 on the first insulating layer 021;

[0090] S3, forming source and drain electrodes 04 and 05 on the second insulating layer 022;

[0091] S4 , forming an active layer 03 on the source-drain electrodes 04 and 05 .

[0092] First, the SiO2 The highly doped silicon wafer is treated to be hydrophilic, and an ultra-low dielectric film is formed on the substrate by spin coating as the second insulating layer 022. After the insulating layer 02 is made, the source and drain electrodes 04 and 05 are made by magnetron sputtering, electron beam evaporation, etc. The electrodes can be highly conductive materials such as Au, Pt, Al, etc. Finally, the active layer 03 is made by atomic layer deposition or spin coating, and the active layer can be made of materials such as metal oxides and organic semiconductors.

[0093] Example 12

[0094] Thin film transistor 300, combined with Fig.14 As shown, it includes an active layer 03, source and drain electrodes 04 and 05 electrically connected to the active layer 03, an insulating layer 02 corresponding to the active layer, and a gate 01. The ultra-low dielectric film as the insulating layer 02 is located between the active layer 03 and the gate 01.

[0095] The present invention provides a method for manufacturing a thin film transistor, comprising the following steps:

[0096] S1, providing a substrate (highly doped silicon wafer), wherein the highly doped silicon is used as the gate 01;

[0097] S2, making an insulating layer 02 on the gate 01;

[0098] S3, forming an active layer 03 on the insulating layer 02;

[0099] S4 , making source and drain electrodes 04 and 05 on the active layer 03 .

[0100] First, the highly doped silicon wafer is subjected to hydrophilic treatment, and an ultra-low dielectric film is formed on the substrate by spin coating as the insulating layer 02. After the insulating layer 02 is made, the active layer 03 is made by atomic layer deposition or spin coating. The active layer can be made of materials such as metal oxides and organic semiconductors. Finally, the source and drain electrodes 04 and 05 are made on the active layer by magnetron sputtering, electron beam evaporation, etc. The electrodes can be highly conductive materials such as Au, Pt, and Al.

[0101] Embodiment 13

[0102] Thin film transistor 400, combined with Fig.15 As shown, the production method comprises the following steps:

[0103] S1, providing a substrate (highly doped silicon wafer), wherein the highly doped silicon is used as the gate 01;

[0104] S2, making an insulating layer 02 on the gate 01;

[0105] S3, making source and drain electrodes 04 and 05 on the insulating layer 02;

[0106] S4 , forming an active layer 03 on the source-drain electrodes 04 and 05 .

[0107] First, the highly doped silicon wafer is treated to be hydrophilic, and an ultra-low dielectric film is formed on the substrate by spin coating as the insulating layer 02. After the insulating layer 02 is made, the source and drain electrodes 04 and 05 are made by magnetron sputtering, electron beam evaporation, etc. The electrodes can be highly conductive materials such as Au, Pt, Al, etc. Finally, the active layer 03 is made by atomic layer deposition or spin coating, and the active layer can be made of materials such as metal oxides and organic semiconductors.

Claims

1. A low dielectric film based on a layered compound, characterized in that: The layered compound is [M x (OH) y ] z+ [(A n- ) z / n ].mH2O or [M 1x1 M 2x2 (OH) y ] z+ [(A n- ) z / n ].mH2O; Among them, M, M1, M2 are metal ions, A n- is an interlayer anion, x, x1, x2, y, z, m, n are non-negative numbers; x (OH) y ] z+ or [M 1x1 M 2x2 (OH) y ] z+ Forming positively charged layers, anions are inserted into the expanded interlayer spacing, and the interlayer anions A n- The layered structure is supported by van der Waals force; the low dielectric film is formed by spin coating deposition of the layered compound.

2. The low dielectric film according to claim 1, characterized in that: The metal ion is Li + , Ca 2+ Mg 2+ 、Al 3+ , Fe 2+ 、Co 2+ 、Ni 2+ , Cu 2+ 、Zn 2+ , Mn 2+ , Y 2+ , Yb 2+ One or more of .

3. The low dielectric film according to claim 1, characterized in that: The anion is SiF6 2- 、GeF6 2- 、TiF6 2- ,NbOF5 2- 、[(CH2)4(CO2)] 2- 、SO4 2- 、CO3 2- 、NO3 - PO4 3- , Cl - Br - , one or more surfactants with organic groups.

4. The low dielectric film according to claim 3, characterized in that: The surfactant with an organic group includes SDS, CTAB, SDBS, and Tween 80.

5. A method for preparing a low dielectric film based on a layered compound, characterized in that: The following steps are involved: The layered compound according to claim 1 is fully dispersed in an organic solvent to prepare a spin coating solution; A substrate is provided, and a spin coating liquid is spin-coated on the substrate.

6. The preparation method according to claim 5, characterized in that: The layered compound is prepared by the following method: dissolving metal salt powder in an organic solvent to make the metal salt concentration be 0.02-0.1 mol / L, adding an organic base until the layered compound is precipitated, and washing to obtain the layered compound; The organic solvent is an alcohol solvent, and the organic base is selected from aliphatic amines and aromatic amines.

7. The preparation method according to claim 5, characterized in that: The thin film obtained by the spin coating method is subjected to supercritical CO2 extraction to extract small organic molecules between the layers.

8. A method for patterning a low dielectric film according to claim 1, characterized in that: Patterning is performed by photolithography, dry and wet etching, and deposition, including the following steps: coating the low dielectric thin film on a substrate to form a dense film layer on the substrate; Spin coating a photoresist on the low dielectric film; The photoresist layer is exposed through a photomask and a specific pattern is formed after development; Deposit the required material on the pattern, and form a specific pattern on the low dielectric film after stripping; or perform dry and wet etching on the developed low dielectric film to form a groove.

9. An application of the low dielectric film according to claim 1, characterized in that: A substrate that serves as an interlayer dielectric or path component for back-end interconnection of a chip.

10. A thin film transistor, comprising an active layer (03), an insulating layer (02), a gate electrode (01), a source electrode (04), and a drain electrode (05), characterized in that: The insulating layer (02) comprises a first insulating layer (021) and a second insulating layer (022) formed by the low dielectric film according to claim 1, which are sequentially located on the gate (01); the active layer (03) is located on the insulating layer (02), and the source (04) and the drain (05) are located on the active layer (03); or the source (04) and the drain (05) are located on the insulating layer (02), and then covered with an active layer (03); Or the low dielectric film is located on the gate (01) as an insulating layer (02), the active layer (03) is located on the insulating layer (02), and the source (04) and the drain (05) are located on the active layer (03); or the source (04) and the drain (05) are located on the insulating layer (02), and then covered with an active layer (03).

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