Power semiconductor device continuous switch test circuit and method

Abstract

The invention discloses a power semiconductor device continuous switch test circuit and method, and relates to the field of power electronics, and the test circuit comprises a current generator which is used for generating a test current; the voltage balance module is used for generating test voltage; the auxiliary module is connected with the current generator and the voltage balance module and is used for providing test voltage and test current required in a continuous switching state for the power semiconductor device T1 to be tested; the capacitor discharging module is used for controlling the magnitude of voltage connected to the two ends of the power semiconductor device T1 to be tested; wherein the voltage balance module comprises a power semiconductor device Tc2 and a capacitor C1; the power semiconductor device Tc2 controls the capacitor C1 to apply voltage to the inductor L in the auxiliary module, and the voltage at the two ends of the inductor L is balanced. According to the application, the continuous switching condition simulation of the power semiconductor device T1 to be tested is met, and voltage and current stress decoupling is realized, so that a voltage source does not need higher voltage stress, and the requirement on a power supply is reduced.

Description

Technical Field

[0001] The present application relates to the field of power electronics, and in particular to a continuous switching test circuit and method for a power semiconductor device. Background Art

[0002] In power electronics applications, IGBTs are mainly in a switching state, undergoing periodic static and dynamic operation, which will lead to energy loss and device power loss, and then cause the junction temperature of the IGBT to fluctuate. In order to quickly verify the service life of the IGBT, an IGBT power cycle test can be performed. This test applies intermittent high current heating to make the chip temperature fluctuate, thereby verifying its ability to withstand electrical and thermal stress, which helps to accelerate the confirmation of the life of the IGBT.

[0003] In the equivalent test of IGBT devices, the key is to simulate the switching transient process and ensure that the effective current is consistent with the actual working condition and the switching frequency is close to the actual application. The existing series valve working condition power cycle test platform is a test platform that includes the switching transient process, which simulates the bridge arm current through PWM control and high-frequency switching. On this platform, the switching frequency of the IGBT device is very high. However, for MMC working conditions, the switching frequency of the IGBT device is low, and the main loss is the conduction loss, so the test platform needs to be able to provide high voltage and high current capabilities.

[0004] Designing a test power supply that can meet these requirements is a huge challenge. It is large in size, expensive, and almost impossible to achieve. This has also become one of the key design problems for the equivalent test of IGBT device operation under MMC conditions. Summary of the invention

[0005] The purpose of the present application is to provide a power semiconductor device continuous switching test circuit and method, which can realize the continuous switching of the power semiconductor device, and the voltage source does not need a greater voltage stress, thereby reducing the power supply requirements.

[0006] To achieve the above objectives, this application provides the following solutions:

[0007] In a first aspect, the present application provides a power semiconductor device continuous switching test circuit, comprising:

[0008] A current generator, used for generating a test current;

[0009] A voltage balancing module, used to generate a test voltage;

[0010] An auxiliary module, connected to the current generator and the voltage balancing module, for providing the power semiconductor device T1 to be tested with the required test voltage and test current in a continuous switching state;

[0011] A capacitor discharge module, used to control the voltage across the two ends of the power semiconductor device T1 to be tested;

[0012] Wherein, the voltage balancing module includes a power semiconductor device T c2 and capacitor C1; the power semiconductor device T c2 The capacitor C1 is controlled to apply a voltage to the inductor L in the auxiliary module, so as to balance the voltage across the inductor L.

[0013] In a second aspect, the present application provides a method for continuous switching test of a power semiconductor device, the method being applied to the above-mentioned continuous switching test circuit of a power semiconductor device, the method comprising:

[0014] The capacitor C2 in the capacitor discharge module is charged to a set voltage Us, and the capacitor C1 in the voltage balance module is charged to a set voltage Us1, and the power semiconductor device T0 in the current generator and the power semiconductor device T1 to be tested are turned on. At this time, the current generator, the inductor L in the auxiliary module, the power semiconductor device T1 to be tested and the power semiconductor device T4 in the auxiliary module form a loop to charge the inductor L until the current reaches the set value Is;

[0015] Turn off the power semiconductor device T0 and the power semiconductor device to be tested T1, and turn on the power semiconductor device T1 in the voltage balancing module. c0 , so that one end of the inductor L bears the voltage of the capacitor C1. At this time, the inductor L, the power semiconductor device T2 in the auxiliary module, the capacitor C2, the power semiconductor device T4, the capacitor C1 and the power semiconductor device T c0 A loop is formed, the inductor L charges the capacitor C2, and at the same time, since the voltage of the capacitor C1 is higher than that of the capacitor C2, the capacitor C1 discharges; after a dead time, the power semiconductor device T2 and the power semiconductor device T3 in the auxiliary module are turned on, and the power semiconductor device T c0 At this time, the inductor L, the power semiconductor device T2, the power semiconductor device T3 and the diode D2 in the auxiliary module form a loop, and the two ends of the power semiconductor device T1 to be tested bear the voltage of the capacitor C2; then the power semiconductor device T in the capacitor discharge module is turned on. c1 and power semiconductor devices T in the voltage balancing module c2 Until the voltage of capacitor C1 returns to the set voltage Us1, the voltage of capacitor C2 is lower than Us, and the power semiconductor device T is turned off. c1 and power semiconductor devices T c2 ;

[0016] Turn off the power semiconductor devices T2 and T3, and turn on the power semiconductor device T c0One end of the inductor L is subjected to the voltage of the capacitor C1. At this time, the inductor L, the power semiconductor device T2, the capacitor C2, the power semiconductor device T4, the capacitor C1 and the power semiconductor device T c0 The inductor L charges the capacitor C1, and C1 discharges. After a dead time, the voltage of the capacitor C2 is charged back to the set voltage Us, the power semiconductor device T1 to be tested is turned on, and the power semiconductor device T2 to be tested is turned off. c0 At this time, the inductor L, the power semiconductor device T1 to be tested, the power semiconductor device T4 and the diode D2 form a loop, and the power semiconductor device T1 to be tested is turned on under the state of being subjected to the set voltage Us. This process completes the turn-on test of the power semiconductor device T1 to be tested;

[0017] Turn on power semiconductor devices T c2 , until the capacitor C1 voltage returns to the set voltage Us1 and then turns off the power semiconductor device T c2 , turn off the power semiconductor device T1 to be tested, and turn on the power semiconductor device T c0 One end of the inductor L is subjected to the voltage of the capacitor C1. At this time, the inductor L, the power semiconductor device T2, the capacitor C2, the power semiconductor device T4, the capacitor C1 and the power semiconductor device T c0 A circuit is formed; the power semiconductor device T1 to be tested is turned off when the current flowing through it is the set value Is, and this process completes the turn-off test of the power semiconductor device T1 to be tested;

[0018] The above steps are repeated to realize a cycle, thereby realizing a continuous switching test of the power semiconductor device T1 to be tested.

[0019] According to the specific embodiments provided in this application, this application has the following technical effects:

[0020] (1) The current generator provided in the present application provides a test current to the power semiconductor device T1 to be tested by forming a loop with a switching element. The circuit is simple and can well meet the large current required by the experiment.

[0021] (2) The balanced voltage module provided by the present application is provided by a power semiconductor device T c2 The control capacitor C1 applies a voltage to the inductor L in the auxiliary module, balances the voltage across the inductor L, and reduces the energy loss caused by the discharge of the inductor L when the power semiconductor device T1 to be tested is turned off.

[0022] (3) The power semiconductor device continuous switching test circuit provided in the present application meets the simulation of the continuous switching working condition of the power semiconductor device T1 to be tested, and realizes the decoupling of voltage and current stress. Therefore, the voltage source does not need a larger voltage stress, which reduces the requirements for the power supply. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0024] Figure 1 A structural diagram of a power semiconductor device continuous switching test circuit provided in an embodiment of the present application;

[0025] Figure 2 A schematic diagram of a flow chart of a method for continuous switching testing of a power semiconductor device provided in one embodiment of the present application;

[0026] Figure 3 It is the key timing waveform diagram of the power semiconductor device in the continuous switching test circuit of the power semiconductor device. DETAILED DESCRIPTION

[0027] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0028] The existing long-term operation evaluation methods for IGBT devices include three types: DC power cycle test platform, towing test platform and full-bridge current source platform. The DC power cycle test platform is considered to be a standard IGBT device reliability test method, but it does not involve switching operations during the test process, so it is significantly different from the electrical stress in actual applications. The towing test platform is mainly used for the joint testing of multi-level sub-modules, and can simulate the current and voltage stress of MMC during steady-state operation, but it is more suitable for testing after the sub-modules are assembled, and the time and economic costs are high. In addition, the towing test platform cannot provide further IGBT device reliability evaluation, nor can it monitor the key reliability parameters of IGBT devices. As for the full-bridge current source platform, although it can generate current and voltage stress during steady-state operation of MMC, its reliability is low due to its own need for high-frequency switching operations, which limits its application in the evaluation of MMC steady-state IGBT devices.

[0029] Therefore, the present application provides a continuous switching test circuit for a power semiconductor device, which can simulate a power semiconductor device under continuous switching conditions and achieve voltage and current stress decoupling to provide high voltage and large current for the test circuit at a low cost.

[0030] In order to make the above-mentioned objects, features and advantages of the present application more obvious and easy to understand, the present application is further described in detail below in conjunction with the accompanying drawings and specific implementation methods.

[0031] In an exemplary embodiment, Figure 1 As shown, a power semiconductor device continuous switching test circuit is provided, comprising: a current generator 1, a voltage balancing module 2, an auxiliary module 3 and a capacitor discharge module 4. Among them:

[0032] The current generator 1 is used to generate a test current. The current generator 1 includes a voltage source V1, a resistor R1, a diode D1 and a power semiconductor device T0 connected in series. The voltage source V1 is controlled by the power semiconductor device T0, and forms a loop with the inductor L to charge the inductor L, so as to deliver the test current to the test circuit.

[0033] The voltage balancing module 2 is used to generate a test voltage. The voltage balancing module 2 includes a power semiconductor device T c0 , capacitor C1, voltage source V2, resistor R3, power semiconductor device T c2 Among them, the power semiconductor device T c0 The voltage of the control capacitor C1 is applied to one end of the inductor L to balance the voltage across the inductor L to reduce the discharge of the inductor L. Power semiconductor device T c2 The control voltage source V2 charges the capacitor C1.

[0034] In a specific embodiment, the positive electrode of the voltage source V2 is connected to one end of the resistor R3, and the other end of the resistor R3 is connected to the power semiconductor device T c2 The collector connection of the power semiconductor device T c2 The emitter of the capacitor C1 and the power semiconductor device T c0 The other end of the capacitor C1 is connected to the negative electrode of the voltage source V2, the negative electrode of the voltage source V1 and the auxiliary module respectively, and the power semiconductor device T c0 The emitter of is connected with the auxiliary module.

[0035] The auxiliary module 3 is connected to the current generator 1 and the voltage balancing module 2, and is used to provide the required test voltage and test current under the continuous switching state for the power semiconductor device T1 to be tested (which is connected in series with the current generator 1 in the main test loop and receives the large current generated by the current generator 1). The auxiliary module 3 includes an inductor L, a power semiconductor device T2, a power semiconductor device T3, a power semiconductor device T4 and a diode D2.

[0036] In a specific embodiment, one end of the inductor L is connected to the power semiconductor device T c0The emitter of the power semiconductor device T0 is connected to the cathode of the diode D2, the other end of the inductor L is respectively connected to the emitters of the power semiconductor device T1 to be tested and the power semiconductor device T2, the collector of the power semiconductor device T2 is respectively connected to the capacitor discharge module and the collector of the power semiconductor device T3, the emitter of the power semiconductor device T3 is respectively connected to the collector of the power semiconductor device T4, the cathode of the diode D2 and the other end of the capacitor C1, and the emitter of the power semiconductor device T4 is respectively connected to the capacitor discharge module and the power semiconductor device T1 to be tested.

[0037] The capacitor discharge module 4 is used to control the voltage of the capacitor C2, that is, the voltage across the two ends of the power semiconductor device T1 to be tested.

[0038] In a specific embodiment, one end of the capacitor C2 is connected to the emitter of the power semiconductor device T2 and the emitter of the power semiconductor device T c1 The collector connection of the power semiconductor device T c1 The emitter of is connected to one end of the resistor R2, and the other end of the resistor R2 is connected to the other end of the capacitor C2 and the emitter of the power semiconductor device T4 respectively.

[0039] In the present application, the current stress of the power semiconductor device T1 to be tested is applied through the current generator 1 , and the voltage stress is applied through the capacitor C2 .

[0040] The above-mentioned test circuit provided in the present application meets the simulation of continuous switching conditions of power semiconductor devices and realizes voltage and current stress decoupling, so the voltage source does not need a higher voltage stress, reducing the requirements for the power supply.

[0041] In an exemplary embodiment, Figure 2 As shown, a method for continuous switching test of a power semiconductor device is provided, and the method is applied to the above-mentioned continuous switching test circuit of the power semiconductor device. Figure 3 The method is a key timing waveform diagram of a power semiconductor device in a power semiconductor device continuous switching test circuit. The method comprises the following steps:

[0042] (1) In the test circuit, the capacitor C2 in the capacitor discharge module 4 is first charged to a set voltage Us, and the capacitor C1 in the voltage balancing module 2 is charged to a set voltage Us1 higher than Us. Then, the power semiconductor device T0 in the current generator 1 and the power semiconductor device T1 to be tested are turned on. At this time, the current generator 1, the inductor L in the auxiliary module 4, the power semiconductor device T1 to be tested and the power semiconductor device T4 in the auxiliary module 4 form a loop to charge the inductor L until the current reaches the set value Is.

[0043] (2) Turn off the power semiconductor devices T0 and T1, and turn on the power semiconductor device T1 in the voltage balancing module 2. c0 , so that one end of the inductor L bears the voltage of the capacitor C1. At this time, the inductor L, the power semiconductor device T2 in the auxiliary module 4, the capacitor C2, the power semiconductor device T4, the capacitor C1 and the power semiconductor device T c0 A loop is formed, and the inductor L charges the capacitor C2. At the same time, because the voltage of the capacitor C1 is higher than that of the capacitor C2, the capacitor C1 discharges. Due to the existence of the capacitor C1, the discharge amount of the inductor L is reduced compared with the absence of C1. After a dead time, the power semiconductor device T2 and the power semiconductor device T3 in the auxiliary module 4 are turned on, and the power semiconductor device T c0 At this time, the inductor L, the power semiconductor device T2, the power semiconductor device T3 and the diode D2 in the auxiliary module 4 form a loop, and the two ends of the power semiconductor device T1 to be tested bear the voltage of the capacitor C2; then the power semiconductor device T in the capacitor discharge module 4 is turned on. c1 and the power semiconductor device T in the voltage balancing module 2 c2 Until the voltage of capacitor C1 returns to the set voltage Us1, the voltage of capacitor C2 returns to slightly lower than Us, and the power semiconductor device T is turned off. c1 and power semiconductor devices T c2 .

[0044] (3) Turn off power semiconductor devices T2 and T3, and turn on power semiconductor device T c0 One end of the inductor L is subjected to the voltage of the capacitor C1. At this time, the inductor L, the power semiconductor device T2, the capacitor C2, the power semiconductor device T4, the capacitor C1 and the power semiconductor device T c0 Similarly, the inductor L charges the capacitor C1, and C1 discharges. After a dead time, the voltage of the capacitor C2 is charged back to the set voltage Us, turning on the power semiconductor device T1 to be tested, and turning off the power semiconductor device T c0 At this time, the inductor L, the power semiconductor device T1 to be tested, the power semiconductor device T4 and the diode D2 form a loop, and the power semiconductor device T1 to be tested is turned on under the state of being subjected to the set voltage Us. This process completes the turn-on test of the power semiconductor device T1 to be tested.

[0045] (4) Turn on the power semiconductor device T c2 , until the capacitor C1 voltage returns to the set voltage Us1 and then turns off the power semiconductor device T c2 , turn off the power semiconductor device T1 to be tested, and turn on the power semiconductor device T c0One end of the inductor L is subjected to the voltage of the capacitor C1. At this time, the inductor L, the power semiconductor device T2, the capacitor C2, the power semiconductor device T4, the capacitor C1 and the power semiconductor device T c0 The power semiconductor device T1 to be tested is turned off when the current flowing through it is the set value Is. This process completes the turn-off test of the power semiconductor device T1 to be tested.

[0046] The above steps are repeated to realize a cycle, thereby realizing a continuous switching test of the power semiconductor device T1 to be tested.

[0047] It can be seen from the above process that the voltage source does not need to bear the voltage setting value Us, the current stress of the power semiconductor device T1 to be tested is applied through the current generator 1, and the voltage stress is applied through the capacitor. Moreover, after each test, the system current returns to the set value Is, which can realize the continuous shutdown of the power semiconductor device T1 to be tested, and the voltage source does not need a larger voltage stress, which reduces the requirements for the power supply.

[0048] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0049] This article uses specific examples to illustrate the principles and implementation methods of this application. The description of the above embodiments is only used to help understand the method and core ideas of this application. At the same time, for those skilled in the art, according to the ideas of this application, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as limiting this application.

Claims

1. A power semiconductor device continuous switching test circuit, characterized in that: include: A current generator, used for generating a test current; A voltage balancing module, used to generate a test voltage; An auxiliary module, connected to the current generator and the voltage balancing module, for providing the power semiconductor device T1 to be tested with the required test voltage and test current in a continuous switching state; A capacitor discharge module, used to control the voltage across the two ends of the power semiconductor device T1 to be tested; Wherein, the voltage balancing module includes a power semiconductor device T c2 and capacitor C1; the power semiconductor device T c2 The capacitor C1 is controlled to apply a voltage to the inductor L in the auxiliary module, so as to balance the voltage across the inductor L.

2. The power semiconductor device continuous switching test circuit according to claim 1, characterized in that: The current generator includes a voltage source V1, a resistor R1, a diode D1 and a power semiconductor device T0 connected in series.

3. The power semiconductor device continuous switching test circuit according to claim 1, characterized in that: The voltage balancing module also includes a power semiconductor device T c0 , voltage source V2 and resistor R3 ; The positive electrode of the voltage source V2 is connected to one end of the resistor R3, and the other end of the resistor R3 is connected to the power semiconductor device T c2 The collector connection of the power semiconductor device T c2 The emitter of the capacitor C1 and the power semiconductor device T c0 The other end of the capacitor C1 is connected to the negative electrode of the voltage source V2, the negative electrode of the voltage source V1 and the auxiliary module respectively, and the power semiconductor device T c0 The emitter of is connected with the auxiliary module.

4. The power semiconductor device continuous switching test circuit according to claim 3, characterized in that: The power semiconductor device T c2 The voltage source V2 is controlled to charge the capacitor C1.

5. The power semiconductor device continuous switching test circuit according to claim 3, characterized in that: The auxiliary module includes: an inductor L, a power semiconductor device T2, a power semiconductor device T3, a power semiconductor device T4 and a diode D2; One end of the inductor L is respectively connected to the power semiconductor device T c0 The emitter of the power semiconductor device T0 is connected to the cathode of the diode D2, the other end of the inductor L is respectively connected to the emitters of the power semiconductor device T1 to be tested and the power semiconductor device T2, the collector of the power semiconductor device T2 is respectively connected to the capacitor discharge module and the collector of the power semiconductor device T3, the emitter of the power semiconductor device T3 is respectively connected to the collector of the power semiconductor device T4, the cathode of the diode D2 and the other end of the capacitor C1, and the emitter of the power semiconductor device T4 is respectively connected to the capacitor discharge module and the power semiconductor device T1 to be tested.

6. The power semiconductor device continuous switching test circuit according to claim 5, characterized in that: The capacitor discharge module includes: a capacitor C2, a power semiconductor device T c1 and resistor R2; One end of the capacitor C2 is connected to the emitter of the power semiconductor device T2 and the emitter of the power semiconductor device T c1 The collector connection of the power semiconductor device T c1 The emitter of is connected to one end of the resistor R2, and the other end of the resistor R2 is connected to the other end of the capacitor C2 and the emitter of the power semiconductor device T4 respectively.

7. The power semiconductor device continuous switching test circuit according to claim 6, characterized in that: The current stress of the power semiconductor device T1 to be tested is applied through the current generator, and the voltage stress of the power semiconductor device T1 to be tested is applied through the capacitor C2.

8. A method for testing continuous switching of a power semiconductor device, characterized in that: The method is applied to the power semiconductor device continuous switching test circuit according to any one of claims 1 to 7, and the method comprises: The capacitor C2 in the capacitor discharge module is charged to a set voltage Us, and the capacitor C1 in the voltage balance module is charged to a set voltage Us1, and the power semiconductor device T0 in the current generator and the power semiconductor device T1 to be tested are turned on. At this time, the current generator, the inductor L in the auxiliary module, the power semiconductor device T1 to be tested and the power semiconductor device T4 in the auxiliary module form a loop to charge the inductor L until the current reaches the set value Is; Turn off the power semiconductor device T0 and the power semiconductor device to be tested T1, and turn on the power semiconductor device T1 in the voltage balancing module. c0 , so that one end of the inductor L bears the voltage of the capacitor C1. At this time, the inductor L, the power semiconductor device T2 in the auxiliary module, the capacitor C2, the power semiconductor device T4, the capacitor C1 and the power semiconductor device T c0 A loop is formed, the inductor L charges the capacitor C2, and at the same time, since the voltage of the capacitor C1 is higher than that of the capacitor C2, the capacitor C1 discharges; after a dead time, the power semiconductor device T2 and the power semiconductor device T3 in the auxiliary module are turned on, and the power semiconductor device T c0 At this time, the inductor L, the power semiconductor device T2, the power semiconductor device T3 and the diode D2 in the auxiliary module form a loop, and the two ends of the power semiconductor device T1 to be tested bear the voltage of the capacitor C2; then the power semiconductor device T in the capacitor discharge module is turned on. c1 and power semiconductor devices T in the voltage balancing module c2 Until the voltage of capacitor C1 returns to the set voltage Us1, the voltage of capacitor C2 is lower than Us, and the power semiconductor device T is turned off. c1 and power semiconductor devices T c2 ; Turn off the power semiconductor devices T2 and T3, and turn on the power semiconductor device T c0 One end of the inductor L is subjected to the voltage of the capacitor C1. At this time, the inductor L, the power semiconductor device T2, the capacitor C2, the power semiconductor device T4, the capacitor C1 and the power semiconductor device T c0 The inductor L charges the capacitor C1, and C1 discharges. After a dead time, the voltage of the capacitor C2 is charged back to the set voltage Us, the power semiconductor device T1 to be tested is turned on, and the power semiconductor device T2 to be tested is turned off. c0 At this time, the inductor L, the power semiconductor device T1 to be tested, the power semiconductor device T4 and the diode D2 form a loop, and the power semiconductor device T1 to be tested is turned on under the state of being subjected to the set voltage Us. This process completes the turn-on test of the power semiconductor device T1 to be tested; Turn on power semiconductor devices T c2 , until the capacitor C1 voltage returns to the set voltage Us1 and then turns off the power semiconductor device T c2 , turn off the power semiconductor device T1 to be tested, and turn on the power semiconductor device T c0 One end of the inductor L is subjected to the voltage of the capacitor C1. At this time, the inductor L, the power semiconductor device T2, the capacitor C2, the power semiconductor device T4, the capacitor C1 and the power semiconductor device T c0 A circuit is formed; the power semiconductor device T1 to be tested is turned off when the current flowing through it is the set value Is, and this process completes the turn-off test of the power semiconductor device T1 to be tested; The above steps are repeated to realize a cycle, thereby realizing a continuous switching test of the power semiconductor device T1 to be tested.

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