Chip resource management method, electronic equipment and medium

Abstract

The invention provides a chip resource management method, electronic equipment and a medium. Determining the type of the resource of the chip; configuring the chips according to the types of the resources to obtain a configuration strategy, wherein the configuration strategy comprises permission of different chips to check the resources, a thread synchronization protocol, a resource access protocol, a communication protocol between a real-time core and a non-real-time core, a resource allocation protocol and a task scheduling protocol; testing the resource running state of the chip configured with the configuration strategy; adjusting a configuration strategy according to the test result to obtain a target configuration strategy; the overall performance of the system and the utilization rate of system resources are improved. Through effective thread scheduling, competition of the threads for shared resources can be reduced, and therefore the probability of deadlock occurrence is reduced.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of chip control, and in particular to a chip resource management method, electronic device, and medium. Background Art

[0002] In the fields of distribution network monitoring and control, multi-core heterogeneous architecture chips are used for real-time data processing and analysis to ensure the stable operation and efficient management of the power grid. While providing high-performance computing capabilities, multi-core heterogeneous architectures also have problems with thread synchronization and deadlock avoidance. In existing multi-core heterogeneous architectures, thread synchronization and deadlock issues are the main factors affecting system performance and stability. Traditional methods often rely on simple lock mechanisms to control access to shared resources. Although the lock mechanism can ensure data consistency to a certain extent, it has the following problems: In a multi-core environment, multiple threads may request access to the same resource at the same time, resulting in lock contention, thereby reducing the concurrent performance of the system. Improper use of locks may cause threads to wait for each other, resulting in deadlocks, making the system unable to continue to work normally. Summary of the invention

[0003] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0004] The purpose of the present application is to solve one of the technical problems existing in the related art to at least a certain extent. The embodiments of the present application provide a chip resource management method, an electronic device and a medium, which can reduce the competition among threads for shared resources and avoid the problem of deadlock.

[0005] An embodiment of the first aspect of the present application is a chip resource management method, comprising:

[0006] Determine the type of chip resources;

[0007] Configuring the chip according to the type of the resource to obtain a configuration strategy, wherein the configuration strategy includes: permissions of different chips to check the resource, thread synchronization protocol, resource access protocol, communication protocol between real-time core and non-real-time core, resource allocation protocol and task scheduling protocol;

[0008] Testing the resource operation status of the chip configured with the configuration strategy;

[0009] The configuration strategy is adjusted according to the test result to obtain a target configuration strategy.

[0010] According to some embodiments of the first aspect of the present application, configuring the thread synchronization protocol includes:

[0011] Selecting a target thread synchronization protocol from a plurality of candidate thread synchronization protocols, and configuring the thread synchronization protocol according to the target thread synchronization protocol;

[0012] The candidate thread synchronization protocols include a semaphore thread synchronization protocol, a mutex thread synchronization protocol, and an event thread synchronization protocol.

[0013] According to some embodiments of the first aspect of the present application, configuring the resource access protocol includes:

[0014] Allocate resources based on their priority;

[0015] Release resources according to the thread's demand for resources;

[0016] Set the maximum waiting time for resource access.

[0017] According to some embodiments of the first aspect of the present application, configuring a communication protocol between the real-time core and the non-real-time core includes:

[0018] Setting a shared memory area, wherein the shared memory area is used for data exchange between the real-time core and the non-real-time core;

[0019] Setting a message queue, wherein the message queue is used for asynchronous communication between the real-time core and the non-real-time core;

[0020] An interrupt mechanism is set, wherein the interrupt mechanism is used to trigger an interrupt signal of the real-time core when a target event is detected, and to notify the non-real-time core to process the target event through the interrupt signal.

[0021] According to some embodiments of the first aspect of the present application, configuring the resource allocation protocol includes:

[0022] Determine the maximum demand and the minimum demand of a process, and allocate resources to the process according to the maximum demand and the demand;

[0023] When it is detected that the first process owns the first resource and does not use the first resource, the second process waits for the first resource and allocates the first resource of the first process to the second process.

[0024] According to some embodiments of the first aspect of the present application, configuring the task scheduling protocol includes:

[0025] Prioritize tasks based on their deadlines;

[0026] determining a target task from a plurality of tasks according to the priority of the task;

[0027] Execute the target task.

[0028] According to some embodiments of the first aspect of the present application, configuring the task scheduling protocol includes:

[0029] When a new task enters the ready queue, the priority of the new task is higher than the priority of the current task, the resources of the current task are released, the resources of the current task are allocated to the new task, and the new task is executed.

[0030] According to some embodiments of the first aspect of the present application, the test configuring the resource operation state of the chip of the configuration strategy includes:

[0031] Testing the resource operation status of the chip configured with the configuration strategy through multiple testing methods;

[0032] Wherein, the test mode includes a first test mode, a second test mode and a third test mode;

[0033] The first test mode is used to test the access of the chip configured with the configuration strategy to the shared resources;

[0034] The second test mode is used to test the interaction between interfaces corresponding to resources;

[0035] The third test mode is used to test the response time and throughput of the chip configured with the configuration strategy under extreme load conditions.

[0036] An embodiment of the second aspect of the present application is an electronic device, comprising: a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein when the processor executes the computer program, the chip resource management method as described in the embodiment of the first aspect of the present application is implemented.

[0037] An embodiment of the third aspect of the present application is a computer storage medium storing computer executable instructions, wherein the computer executable instructions are used to execute the chip resource management method as described in the embodiment of the first aspect of the present application.

[0038] The above scheme has at least the following beneficial effects: by setting and optimizing the permissions of different chip cores to the resources, the thread synchronization protocol, the resource access protocol, the communication protocol between the real-time core and the non-real-time core, the resource allocation protocol and the configuration strategy of the task scheduling protocol, the overall performance of the system is improved, and the utilization rate of system resources is improved. Through effective thread scheduling, the competition of threads for shared resources can be reduced, thereby avoiding the problem of deadlock. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] The accompanying drawings are used to provide further understanding of the technical solution of the present application and constitute a part of the specification. Together with the embodiments of the present application, they are used to explain the technical solution of the present application and do not constitute a limitation on the technical solution of the present application.

[0040] Figure 1is a step diagram of a chip resource management method provided in an embodiment of the present application;

[0041] Figure 2 is a step diagram of configuring a thread synchronization protocol provided by an embodiment of the present application;

[0042] Figure 3 is a step diagram of configuring a resource access protocol provided by an embodiment of the present application;

[0043] Figure 4 is a step diagram of configuring a communication protocol between a real-time core and a non-real-time core provided by an embodiment of the present application;

[0044] Figure 5 is a step diagram of configuring a resource allocation protocol provided by an embodiment of the present application;

[0045] Figure 6 is a step diagram of a task selection mechanism provided by an embodiment of the present application;

[0046] Figure 7 is a step diagram of a task preemption mechanism provided by an embodiment of the present application;

[0047] Figure 8 It is a sub-step diagram of step S130 provided in an embodiment of the present application. DETAILED DESCRIPTION

[0048] In order to make the purpose, technical solution and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0049] It should be noted that, although the functional modules are divided in the device schematic diagram and the logical order is shown in the flowchart, in some cases, the steps shown or described may be performed in a different order than the module division in the device or the order in the flowchart. The terms "first", "second", etc. in the specification, claims or the above drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence.

[0050] The embodiments of the present application are further described below in conjunction with the accompanying drawings.

[0051] In the fields of distribution network monitoring and control, multi-core heterogeneous architecture chips are used for real-time data processing and analysis to ensure the stable operation and efficient management of the power grid. While providing high-performance computing capabilities, multi-core heterogeneous architectures also have problems with thread synchronization and deadlock avoidance. In existing multi-core heterogeneous architectures, thread synchronization and deadlock issues are the main factors affecting system performance and stability. Traditional methods often rely on simple lock mechanisms to control access to shared resources. Although the lock mechanism can ensure data consistency to a certain extent, it has the following problems: In a multi-core environment, multiple threads may request access to the same resource at the same time, resulting in lock contention, thereby reducing the concurrent performance of the system. Improper use of locks may cause threads to wait for each other, resulting in deadlocks, making the system unable to continue to work normally.

[0052] In order to solve the above problems, an embodiment of the present application provides a chip resource management method.

[0053] Reference Figure 1 , a chip resource management method, comprising the following steps:

[0054] Step S110, determining the type of chip resources;

[0055] Step S120, configuring the chip according to the type of the resource to obtain a configuration strategy;

[0056] Step S130, testing the resource operation status of the chip configured with the configuration strategy;

[0057] Step S140, adjusting the configuration strategy according to the test result to obtain a target configuration strategy.

[0058] The configuration strategy includes: permissions of different chip cores to the resources, thread synchronization protocol, resource access protocol, communication protocol between real-time core and non-real-time core, resource allocation protocol and task scheduling protocol.

[0059] For step S110, the type of chip resources is determined, and the chip resource types include shared resources and exclusive resources. Shared resources are resources that can be accessed by multiple threads at the same time, such as shared memory areas, network interfaces, etc. Exclusive resources are resources that can only be accessed by one thread at the same time, such as some key hardware device interfaces.

[0060] For step S120, the chip is configured according to the type of the resource to obtain a configuration strategy.

[0061] Among them, for configuring the permissions of different chips to check the resources, it includes defining access permissions for each resource and distinguishing the differences in access permissions between real-time core and non-real-time core resources. Access permissions include read permission, write permission and execute permission. Read permission allows threads to read resource data. Write permission allows threads to modify resource data. Execute permission allows threads to perform resource-related operations. With respect to permission differences, there are different access permissions for real-time core and non-real-time core resources. The real-time core will have exclusive access permissions to certain key hardware device interfaces to ensure timely response of real-time tasks.

[0062] Reference Figure 2 , configuring the thread synchronization protocol, including the following steps:

[0063] Step S210, selecting a target thread synchronization protocol from a plurality of candidate thread synchronization protocols, and configuring the thread synchronization protocol according to the target thread synchronization protocol;

[0064] The candidate thread synchronization protocols include a semaphore thread synchronization protocol, a mutex thread synchronization protocol, and an event thread synchronization protocol.

[0065] For the thread synchronization protocol of semaphores, semaphores are used to control access to shared resources to avoid data inconsistency caused by multiple threads accessing at the same time. Use semaphores to control access to shared memory areas to ensure that only one thread can read and write shared memory at the same time.

[0066] For the thread synchronization protocol of the mutex lock, the mutex lock ensures that only one thread can access a resource at the same time to avoid deadlock. Use the mutex lock to control the access to the hardware device interface to ensure that only one thread can operate the hardware device at the same time.

[0067] For the event-based thread synchronization protocol, events implement communication and synchronization between threads. After one thread completes a task, it notifies another thread to start executing. Events are used to notify the real-time core that certain data is ready and can be processed.

[0068] Reference Figure 3 , configuring the resource access protocol, including the following steps:

[0069] Step S310, allocating resources according to their priorities;

[0070] Step S320, releasing resources according to the thread's demand for resources;

[0071] Step S330, setting the maximum waiting time of the resource access process.

[0072] For resource allocation order, resources are allocated according to their priority. High-priority resources are allocated first. Key hardware device interfaces are defined as high-priority resources and are allocated to real-time cores first.

[0073] For the resource release order, release resources according to the thread's demand for resources. Release them immediately when the thread no longer needs the resources.

[0074] For the timeout mechanism, it includes setting the maximum waiting time and timeout processing.

[0075] Set a maximum waiting time for resource access. If the time is exceeded, the waiting will be abandoned to avoid the system crash caused by infinite thread waiting.

[0076] When a thread times out waiting for a resource, the following actions can be taken: retry, downgrade, and terminate the thread. For retry, the thread can retry to obtain the resource. For downgrade, the thread can lower its priority or use alternative resources. For terminate, the thread can terminate execution.

[0077] Reference Figure 4 , configuring the communication protocol between the real-time core and the non-real-time core, comprising the following steps:

[0078] Step S410, setting a shared memory area;

[0079] Step S420, setting a message queue;

[0080] Step S430, setting an interruption mechanism.

[0081] For the shared memory area, data exchange between the real-time core and the non-real-time core is realized through the shared memory area. The real-time core writes the collected data into the shared memory, and the non-real-time core reads the data from the shared memory for processing.

[0082] For the message queue, the message queue is used to realize asynchronous communication between the real-time core and the non-real-time core. The real-time core sends the task request to the message queue, and the non-real-time core reads the task request from the message queue and executes the task corresponding to the task request.

[0083] For the interrupt mechanism, the interrupt mechanism is used in the interrupt process to achieve a fast response of the real-time core to the non-real-time core. When a target event is detected, the interrupt signal of the real-time core is triggered, and the non-real-time core is notified to process the target event through the interrupt signal.

[0084] Reference Figure 5 , configuring the resource allocation protocol, comprising the following steps:

[0085] Step S510, determining the maximum demand and the minimum demand of a process, and allocating resources to the process according to the maximum demand and the demand;

[0086] Step S520: When it is detected that the first process owns the first resource and does not use the first resource, the second process waits for the first resource and allocates the first resource of the first process to the second process.

[0087] Before allocating resources, it is necessary to pre-check whether the allocation of resources will cause deadlock. If it will cause deadlock, the allocation will be rejected.

[0088] Calculate the maximum demand of each process and initialize the available resource vector. Check each process, if the process demand is less than or equal to the available resource vector, allocate resources and update the available resource vector. If all processes are allocated the required resources, the system is safe, otherwise the system is unsafe and the allocation is rejected.

[0089] The formula for calculating the demand of a process is: Need[i] = Max[i] - Allocaion[i]; where Need[i] represents the demand of process i, Max[i] represents the maximum demand of process i, and Allocaion[i] represents the amount of resources already allocated to process i.

[0090] Resource pre-allocation is to pre-allocate a certain amount of resources to each process when the system starts. Resource pre-allocation can prevent the process from being blocked due to insufficient resources during operation. Resource pre-allocation includes the following steps: determining the minimum required amount of each process; pre-allocating the minimum required amount of resources to each process.

[0091] When a process is waiting for resources, it can deprive other processes of the resources they have obtained and give priority to the waiting process. Check the resource allocation in the system. If there is a first process that has a resource, but a second process is waiting for the first resource, deprive the first process of the resource and give it to the waiting second process.

[0092] Determine whether the system is in a deadlock state by periodically testing the system. If it is in a deadlock state, take recovery measures. Use resource allocation graphs or banker's algorithm to detect whether the system is in a deadlock state. If the system is detected to be in a deadlock state, take recovery measures. Recovery measures include terminating deadlocked threads, releasing deadlocked resources, and reallocating resources.

[0093] Assume that there are two processes in the system, including process A and process B. Process A owns resource R1, process B owns resource R2, and process A waits for resource R2, while process B waits for resource R1. When the priority of process A is greater than the priority of process B, process A obtains resource R2 from process B, and process A continues to execute after obtaining resource R2.

[0094] Reference Figure 6 , configuring the task scheduling protocol to include a task selection mechanism, the task selection mechanism including the following steps:

[0095] Step S610, determining the priority of the task according to the deadline of the task;

[0096] Step S620, determining a target task from a plurality of tasks according to the priority of the task;

[0097] Step S630, executing the target task.

[0098] The earliest deadline first scheduling algorithm is used to schedule real-time systems, and tasks are scheduled according to their deadlines. In the earliest deadline first scheduling algorithm, the priority of a task is determined by its deadline. The earlier the deadline, the higher the priority. The calculation formula for the priority of a task is: Priority(T i) = Deadline(T i). Among them, Priority(T i) is the priority of task T i, and Deadline(T i) is the deadline of task T i.

[0099] At each scheduling point, the scheduler selects the task with the earliest deadline to execute. The selection formula for the next task to execute is: T next is the next task to be executed; T is the set of tasks in the ready queue; T i The i-th task in the set of tasks in the ready queue.

[0100] The scheduler allocates CPU resources to the selected task T next , the system starts executing the task.

[0101] Reference Figure 7 , configuring the task scheduling protocol to include a task preemption mechanism, the task preemption mechanism includes the following steps:

[0102] Step S710, when a new task enters the ready queue, the priority of the new task is higher than the priority of the current task, the resources of the current task are released, the resources of the current task are allocated to the new task, and the new task is executed.

[0103] If a new task enters the ready queue and the deadline of the new task is earlier than the deadline of the current task, the priority of the new task is higher than the priority of the current task, the resources of the current task are released, the resources of the current task are allocated to the new task, and the new task is executed.

[0104] The formula for the preemption condition is: Dead line (T j ) <Dead l ine(T current ).

[0105] When the current task is completed or blocked due to waiting for resources, the scheduler reselects the task.

[0106] Reference Figure 8 For step S130, the test configures the resource operation status of the chip of the configuration strategy, including the following steps:

[0107] Step S131, testing the resource operation status of the chip configured with the configuration strategy through multiple testing methods;

[0108] Wherein, the test mode includes a first test mode, a second test mode and a third test mode;

[0109] The first test mode is used to test the access of the chip configured with the configuration strategy to the shared resources;

[0110] The second test mode is used to test the interaction between interfaces corresponding to resources;

[0111] The third test mode is used to test the response time and throughput of the chip configured with the configuration strategy under extreme load conditions.

[0112] The first test method is unit testing. During the unit testing process, each thread and synchronization mechanism is unit tested to verify its functional correctness. Test whether synchronization mechanisms such as semaphores, mutexes, and events can correctly control access to shared resources.

[0113] The second test method is integration testing. During the integration test, thread synchronization and deadlock avoidance mechanisms are tested in the entire system to verify their effectiveness and reliability.

[0114] The third test method is stress testing. During stress testing, thread synchronization and deadlock avoidance mechanisms are tested under high load to verify their stability and performance. The response time and throughput of the system under high load are tested. High load conditions are simulated to test whether the system can effectively avoid deadlocks.

[0115] For step S140, the configuration strategy is adjusted according to the test result to obtain a target configuration strategy.

[0116] For example, optimizing lock usage by breaking down a large lock into small locks; breaking down a large lock into multiple small locks reduces the scope of lock contention and improves concurrency performance.

[0117] Suppose there is a shared array array, and each element in the array needs to be added. The array can be divided into multiple segments, each segment uses a lock, and the scope of lock contention can be reduced.

[0118] The following steps are iterated and looped. First, the lock of the corresponding segment is locked. Then, the shared array is rewritten, for example, the shared array is rewritten according to the formula array[i]+=1. Finally, the lock of the corresponding segment is unlocked.

[0119] Use atomic operations instead of locks to avoid thread blocking caused by locks. Atomic operations refer to the indivisibility of operations on a variable in a multi-threaded environment, that is, only one thread can operate on the variable at the same time. Suppose there is a variable count, and it is necessary to ensure that the addition operation to count is atomic in a multi-threaded environment. This can be achieved using the atomic operation atomic_add_fetch, and the calculation formula is: atomic_add_fetch(&count, 1, ATOMIC_SEQ_CST); where atomic_add_fetch is the atomic operation function provided by GCC, count is the variable to be operated, 1 is the value to be increased, and ATOMIC_SEQ_CST is the memory order, which ensures that the result of the operation is immediately visible to other threads.

[0120] Monitor the running status of thread synchronization and deadlock avoidance mechanisms during performance monitoring to detect and solve problems in a timely manner. Use performance monitoring tools to monitor system indicators such as CPU usage, memory usage, and response time. During code refactoring, refactor the code regularly to improve code readability and maintainability. Decompose complex code modules into multiple simple modules to improve code readability.

[0121] According to the test results, the permissions of different chip cores of the configuration strategy to the resources, thread synchronization protocol, resource access protocol, communication protocol between real-time core and non-real-time core, resource allocation protocol and task scheduling protocol are adjusted to obtain the target configuration strategy.

[0122] In this embodiment, by adopting a priority scheduling strategy, it can be ensured that real-time tasks are processed in a timely manner to meet the requirements of hard real-time systems, which is particularly important for real-time cores in multi-core heterogeneous architectures. Preemptive scheduling allows high-priority tasks to preempt the CPU resources of low-priority tasks, which helps to reduce the response time of critical tasks and improve the overall performance of the system. The time slice round-robin scheduling strategy can ensure fair execution between non-real-time tasks, avoid certain tasks occupying CPU resources for a long time, and thus improve the utilization of system resources. Through effective thread scheduling, the competition for shared resources among threads can be reduced, thereby reducing the probability of deadlock.

[0123] By reducing the use of locks, refining the lock granularity, and using lock optimization algorithms, we can reduce blocking between threads and improve the performance of concurrent execution. Optimizing the use of locks can reduce the risk of deadlock by reducing the number of threads blocked indefinitely due to waiting for locks. Code optimization can reduce unnecessary lock contention and context switching, thereby improving the throughput of the system and enabling the system to handle more tasks. By optimizing resource access patterns, we can use system resources more efficiently, reduce resource waste, and improve the overall efficiency of the system. We can significantly improve the stability of the system and reduce system crashes caused by improper thread scheduling or lock contention. By optimizing scheduling and code, the maintainability of the system is improved, which facilitates subsequent debugging and function expansion. The timely response of real-time tasks and the fair execution of non-real-time tasks together improve the user experience, especially in scenarios with strict requirements on response time.

[0124] An embodiment of the present application provides an electronic device, which includes a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the chip resource management method described above when executing the computer program.

[0125] The electronic device may be any intelligent terminal including a computer.

[0126] In general, for the hardware structure of the electronic device, the processor can be implemented using a general-purpose CPU (Central Processing Unit), a microprocessor, an application-specific integrated circuit (Application Specific Integrated Circuit, ASIC), or one or more integrated circuits, etc., to execute related programs to implement the technical solutions provided in the embodiments of the present application.

[0127] The memory can be implemented in the form of a read-only memory (ROM), a static storage device, a dynamic storage device, or a random access memory (RAM). The memory can store an operating system and other applications. When the technical solutions provided in the embodiments of this specification are implemented by software or firmware, the relevant program codes are stored in the memory, and the processor is called to execute the methods of the embodiments of this application.

[0128] The input / output interface is used to realize information input and output.

[0129] The communication interface is used to realize the communication interaction between this device and other devices. Communication can be achieved through wired methods (such as USB, network cable, etc.) or wireless methods (such as mobile network, WIFI, Bluetooth, etc.).

[0130] The bus transmits information between the various components of the device (such as the processor, memory, input / output interface, and communication interface). The processor, memory, input / output interface, and communication interface communicate with each other within the device through the bus.

[0131] An embodiment of the present application provides a computer storage medium, wherein the computer storage medium stores computer executable instructions, and the computer executable instructions are used to execute the chip resource management method described above.

[0132] It will be appreciated by those skilled in the art that all or some of the steps and systems in the methods disclosed above may be implemented as software, firmware, hardware, and appropriate combinations thereof. Some or all physical components may be implemented as software executed by a processor, such as a central processing unit, a digital signal processor, or a microprocessor, or as hardware, or as an integrated circuit, such as an application-specific integrated circuit. Such software may be distributed on a computer-readable medium, which may include a computer storage medium (or non-transitory medium) and a communication medium (or transient medium). As is well known to those skilled in the art, the term computer storage medium includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information, such as computer-readable instructions, data structures, program modules, or other data. Computer storage media include, but are not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital versatile disk (DVD) or other optical disk storage, magnetic cassettes, magnetic tapes, disk storage or other magnetic storage devices, or any other medium that can be used to store the desired information and can be accessed by a computer. In addition, it is well known to those of ordinary skill in the art that communication media typically contain computer-readable instructions, data structures, program modules, or other data in modulated data signals such as carrier waves or other transmission mechanisms, and may include any information delivery medium. In the above description of this specification, the description of reference terms "one embodiment / example", "another embodiment / example" or "certain embodiments / examples" and the like means that the specific features, structures, materials or characteristics described in conjunction with the embodiments or examples are included in at least one embodiment or example of the present application. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

[0133] Those skilled in the art will appreciate that all or some of the steps in the methods disclosed above, and the functional modules / units in the systems and devices may be implemented as software, firmware, hardware, or a suitable combination thereof.

[0134] The units described above as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0135] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of software functional units.

[0136] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art, or all or part of the technical solution can be embodied in the form of a software product. The computer software product is stored in a storage medium, including multiple instructions to enable a computer device (which can be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods of various embodiments of the present application. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM), random access memory (RAM), disk or optical disk, and other media that can store programs.

[0137] In the several embodiments provided in the present application, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of the above-mentioned units is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms. Although the embodiments of the present application have been shown and described, it can be understood by those of ordinary skill in the art that various changes, modifications, substitutions and variations can be made to these embodiments without departing from the principles and purposes of the present application, and the scope of the present application is defined by the claims and their equivalents.

[0138] The above is a specific description of the preferred implementation of the present application, but the present application is not limited to the embodiments. Technical personnel familiar with the field can make various equivalent modifications or substitutions without violating the spirit of the present application. These equivalent modifications or substitutions are all included in the scope defined by the claims of the present application.

Claims

1. A chip resource management method, characterized in that: include: Determine the type of chip resources; Configuring the chip according to the type of the resource to obtain a configuration strategy, wherein the configuration strategy includes: permissions of different chips to check the resource, thread synchronization protocol, resource access protocol, communication protocol between real-time core and non-real-time core, resource allocation protocol and task scheduling protocol; Testing the resource operation status of the chip configured with the configuration strategy; The configuration strategy is adjusted according to the test result to obtain a target configuration strategy.

2. The chip resource management method according to claim 1, characterized in that: Configuring the thread synchronization protocol includes: Selecting a target thread synchronization protocol from a plurality of candidate thread synchronization protocols, and configuring the thread synchronization protocol according to the target thread synchronization protocol; The candidate thread synchronization protocols include a semaphore thread synchronization protocol, a mutex thread synchronization protocol, and an event thread synchronization protocol.

3. The chip resource management method according to claim 1, characterized in that: Configuring the resource access protocol includes: Allocate resources based on their priority; Release resources according to the thread's demand for resources; Set the maximum waiting time for resource access.

4. The chip resource management method according to claim 1, characterized in that: Configuring a communication protocol between the real-time core and the non-real-time core includes: Setting a shared memory area, wherein the shared memory area is used for data exchange between the real-time core and the non-real-time core; Setting a message queue, wherein the message queue is used for asynchronous communication between the real-time core and the non-real-time core; An interrupt mechanism is set, wherein the interrupt mechanism is used to trigger an interrupt signal of the real-time core when a target event is detected, and to notify the non-real-time core to process the target event through the interrupt signal.

5. The chip resource management method according to claim 1, characterized in that: Configuring the resource allocation protocol includes: Determine the maximum demand and the minimum demand of a process, and allocate resources to the process according to the maximum demand and the demand; When it is detected that the first process owns the first resource and does not use the first resource, the second process waits for the first resource and allocates the first resource of the first process to the second process.

6. The chip resource management method according to claim 1, characterized in that: Configuring the task scheduling protocol includes: Prioritize tasks based on their deadlines; determining a target task from a plurality of tasks according to the priority of the task; Execute the target task.

7. The chip resource management method according to claim 1, characterized in that: Configuring the task scheduling protocol includes: When a new task enters the ready queue, the priority of the new task is higher than the priority of the current task, the resources of the current task are released, the resources of the current task are allocated to the new task, and the new task is executed.

8. The chip resource management method according to claim 1, characterized in that: The test configures the resource operation status of the chip of the configuration strategy, including: Testing the resource operation status of the chip configured with the configuration strategy through multiple testing methods; Wherein, the test mode includes a first test mode, a second test mode and a third test mode; The first test mode is used to test the access of the chip configured with the configuration strategy to the shared resource; The second test mode is used to test the interaction between interfaces corresponding to resources; The third test mode is used to test the response time and throughput of the chip configured with the configuration strategy under extreme load conditions.

9. An electronic device, characterized in that: include: A memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the chip resource management method according to any one of claims 1 to 8 when executing the computer program.

10. A computer storage medium, characterized in that: Computer executable instructions are stored, and the computer executable instructions are used to execute the chip resource management method according to any one of claims 1 to 8.

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