Multi-stage broadband low-noise amplifier with variable gain

Abstract

A variable-gain multistage broadband low-noise amplifier comprises N (N > = 2) stages of amplifying circuits, the first stage of amplifying circuit and the second stage of amplifying circuit are connected through a first inter-stage matching circuit, a main circuit switch and an inter-stage matching circuit are sequentially connected between the subsequent stages of amplifying circuits in series, the input end is connected with an input matching circuit in series to be connected to the first stage of amplifying circuit, and the second stage of amplifying circuit is connected with a second stage of amplifying circuit. The Nth-stage amplification circuit is connected in series with a main switch and an output matching circuit in sequence to a signal output end; from the second stage, each stage of amplifying circuit and the main switch are integrally connected with a bypass switch in parallel; a source degeneration inductance scheme is adopted for input matching, and the noise performance is optimized; the overall gain flatness is improved through inter-stage matching; a multi-stage LC structure is adopted for output matching, and broadband matching in different gain modes is achieved; according to the invention, control of each switch is realized through logic level signals, switching of multiple gain modes is realized, the designed bandwidth reaches more than 10GHz, and the overall gain flatness and the noise coefficient in different gain modes are kept consistent.

Description

Technical Field

[0001] The invention relates to the technical field of low noise amplifiers, and in particular to a multi-stage broadband low noise amplifier with variable gain. Background Art

[0002] In recent years, as communication technology continues to update and iterate, the receiver, as a basic module in the communication system, faces increasingly higher performance requirements, such as wider bandwidth, larger dynamic range, etc. In wireless communication systems, electromagnetic waves are affected by factors such as propagation paths and environmental noise. The power of electromagnetic wave signals reaching the antenna end of the receiver often varies greatly. Because the low-noise amplifier (LNA) is located at the front end of the receiver, a variable-gain LNA is required to amplify different received signals. For example, in receivers for 5G phased array applications, variable-gain low-noise amplifiers are essential; when weak RF signals enter the receiver, the low-noise amplifier needs to have the highest gain and the lowest noise figure; if the input RF signal is strong, the low-noise amplifier provides a smaller gain and high linearity to prevent the receiver from saturating.

[0003] At present, there are two methods for achieving adjustable LNA gain: first, a transistor is connected to a load network as a switch, and the load network is changed by controlling the number of transistors that are turned on, thereby adjusting the gain of the amplifier, such as the solution disclosed in Chinese patent CN116896325A: The invention provides a variable gain low noise amplifier (LNA), including a first transistor, wherein the gate terminal of the first transistor is configured to receive an input signal; a first negative feedback inductor coupled to the source terminal of the first transistor, wherein the first transistor and the first negative feedback inductor belong to a first branch of the variable gain LNA; a second transistor, wherein the gate terminal of the second transistor is configured to receive the input signal; and a second negative feedback inductor coupled to the source terminal of the second transistor, wherein the second transistor and the second negative feedback inductor belong to a second branch of the variable gain LNA; wherein the gain of the variable gain LNA is determined by controlling the conduction or shutoff of the second branch. The variable gain low noise amplifier and method provided by the invention not only slices the transistors, but also slices the negative feedback inductor, thereby ensuring that the input matching can be maintained in the best state and optimizing the input linearity in all gain modes.

[0004] Secondly, different gains are achieved by changing the bias of the amplifier tube, such as the solution disclosed in Chinese patent CN217957035U: a variable gain low noise amplifier, characterized in that it includes: an amplifier circuit, which is configured to receive a radio frequency input signal and output a radio frequency output signal, and a programmable control switch, which is connected to the amplifier circuit and is configured to adjust the gain of the low noise amplifier by adjusting the conduction and disconnection of the branch switch circuit therein; it has the advantages of low power consumption, simple structure, and programmability. By controlling the gain, the power consumption can be further controlled, thereby achieving relatively stable power output, so that the intermediate frequency circuit can achieve optimal receiving performance.

[0005] However, when the above two solutions change the LNA gain, the working state of the amplifier itself also changes. For example, when the gain is adjusted by changing the bias of the amplifier tube, the bias current of the amplifier tube is small when the gain is adjusted to a smaller gear, which will deteriorate the noise performance of the LNA. So the problem is that it is impossible to ensure that other performance indicators of the amplifier will not deteriorate significantly when the gain is changed; in addition, there are currently few reports on variable gain low noise amplifiers for broadband applications with an operating frequency band of more than 10GHz, and they are limited by the deterioration of the noise coefficient after multi-stage cascading, and there are few designs of cascaded variable gain low noise amplifiers with 3 or more stages. Summary of the invention

[0006] In order to overcome the deficiencies of the above-mentioned prior art, the purpose of the present invention is to provide a multi-stage broadband low-noise amplifier with variable gain, which controls the power switch, the main switch and the bypass switch through logic level signals, and can switch between up to 2^(N-1) gain modes; the input matching network design adopts a source degeneration inductance scheme to optimize the noise performance of the first-stage amplifier circuit; the inter-stage matching circuit improves the overall gain flatness according to the idea of ​​gain compensation; the output matching circuit adopts a multi-stage LC matching network to match different frequency points, while reducing the insertion loss, achieving good broadband output matching; thus, the variable gain multi-stage broadband low-noise amplifier has a design bandwidth of more than 10GHz.

[0007] In order to achieve the above object, the technical solution adopted by the present invention is:

[0008] A variable-gain multi-stage broadband low-noise amplifier comprises N (N≥2) stages of amplification circuits, wherein the first and second stages of amplification circuits are connected through a first inter-stage matching circuit, and the subsequent stages of amplification circuits are sequentially connected in series with a main switch and an inter-stage matching circuit; the input end is connected to the first stage of amplification circuit through a series input matching circuit, and the Nth stage of amplification circuit is sequentially connected in series with a main switch and an output matching circuit to a signal output end; starting from the second stage, each stage of amplification circuit and the main switch are connected in parallel with a bypass switch as a whole; the first stage of amplification circuit is directly connected to a power supply Vdd, and starting from the second stage, a power switch is connected in series between the amplification circuit and the power supply Vdd.

[0009] The variable-gain multi-stage broadband low-noise amplifier is manufactured using a 0.15um GaAs pHEMT process.

[0010] The first-stage amplifier circuit topology structure includes a transistor M1, a transistor M2, a transistor M3, a transistor M4, a resistor R1, a resistor R2, a resistor R3, a resistor R4, an inductor L2, an inductor L3, an inductor L4, a capacitor C2, and a microstrip line T1; the gate of the transistor M3 is connected to an input matching circuit, the source of the transistor M3 is connected in series with a microstrip line T1 with one end grounded, the drain of the transistor M3 is connected in series with an inductor L3 and then connected to the source of the transistor M4; the gate of the transistor M4 is connected in series with a resistor R4 and then leads to the input end of the bias signal Vg1, the drain of the transistor M4 is simultaneously connected in parallel with the inductor L2, the inductor L4, and the first-stage inter-matching circuit; the other end of the inductor L2 is connected to the resistor R2, and the other end of the resistor R2 is connected to the gate of the transistor M3;

[0011] The source of the transistor M1 is grounded, and the gate and drain are short-circuited. The gate of the transistor M1 is connected in parallel with a capacitor C2 with one end grounded and a resistor R1 with one end connected to the gate of the transistor M3. The gate of the transistor M2 is controlled by a voltage Vpd1, and its drain is connected to a power supply Vdd. The source is connected in series with a resistor R3, and the other end of the resistor R3 is connected to the drain of the transistor M1.

[0012] The n-th stage amplifier circuit (n≠1) is N-1 in total, and its topological structure is the same, and the number of stages can be determined according to the design target; the n-th stage amplifier circuit (n≠1) includes a transistor M7, a transistor M8, a transistor M9, a transistor M10, a transistor M11, a resistor R5, a resistor R6, a resistor R7, a resistor R8, an inductor L6, an inductor L7, an inductor L8, and a capacitor C5; the gate of the transistor M8 is connected to the n-1-th stage matching circuit and the bypass switch n-1; the drain of the transistor M8 is connected in series with the inductor L7; the source of the transistor M8 is connected in series with a transistor M7 used as a switch; wherein , the source of transistor M7 is grounded, and the gate is led out as the input end of the logic level signal Va1; the other end of inductor L7 is connected to the source of transistor M9, and the gate of transistor M9 is connected in series with a resistor R8 and then led out as the input end of bias signal Vg2, and the drain of transistor M9 is connected in parallel with inductor L6, inductor L8 and main switch n-1; the other end of inductor L6 is connected to resistor R7, and the other end of resistor R7 is connected to the gate of transistor M8; in particular, when designing the last stage of the amplifier circuit, a capacitor is connected in parallel to the signal output port, and the other end of the capacitor is connected in series with a low-value resistor with one end grounded;

[0013] The source of the transistor M10 is grounded, and the gate and drain are short-circuited. The gate of the transistor M10 is connected in parallel with a capacitor C5 whose one end is grounded and a resistor R6 whose one end is connected to the gate of the transistor M8. The gate of the transistor M11 is controlled by the voltage Vpd2, and its drain is connected to the power supply Vdd. The source is connected in series with a resistor R5, and the other end of the resistor R5 is connected to the drain of the transistor M10.

[0014] The input matching circuit includes a capacitor C1 and an inductor L1; the signal input terminal RFin is connected in series with the capacitor C1 and the inductor L1 in sequence, and the other port of the inductor L1 is connected to the gate of the transistor M3, that is, the signal input terminal of the first-stage amplifier circuit; in order to improve the noise performance of the multi-stage low-noise amplifier, the input matching network design adopts a source degeneration inductor solution to complete the 50Ω impedance matching of the input terminal.

[0015] There are a total of N-1 inter-stage matching circuits with the same topological structure, including an inductor L5 and a capacitor C4 connected in series: the other end of the inductor L5 is connected to the previous stage amplifier circuit, and the other end of the capacitor C4 is connected to the input end of the next stage amplifier circuit.

[0016] The output matching circuit includes microstrip lines T2, T3, T4, T5, and capacitors C13, C14, and C15. After the microstrip lines T2, T3, T4, and T5 are connected in series in sequence, one end of the microstrip line T2 is connected to a main switch N and a bypass switch N, one end of the microstrip line T5 is connected to a signal output port RFout, a capacitor C13 with one end grounded is connected in parallel between the microstrip line T2 and the microstrip line T3, a capacitor C14 with one end grounded is connected in parallel between the microstrip line T3 and the microstrip line T4, and a capacitor C15 with one end grounded is connected in parallel between the microstrip line T4 and the microstrip line T5. The output matching network adopts a multi-stage LC matching structure to optimize the maximum gain and gain flatness, and realize broadband output matching under different gain modes.

[0017] There are a total of N-1 main switches with the same topological structure, all of which are implemented using a transistor: one end of the main switch (i.e., the corresponding transistor) is connected to the signal output end of the previous stage amplifier circuit, and the other end is connected to the input end of the next stage matching circuit. The gate of the transistor is connected to the input end of the logic level signal, and the main switch is controlled by the logic level signal.

[0018] There are a total of N-1 bypass switches with the same topological structure, including a transistor M5, a transistor M6 and a DC blocking capacitor C6: the drain of the transistor M5 is connected to the signal output end of the previous stage matching circuit, the source of the transistor M5 is connected in series with the DC blocking capacitor C6 and then connected to the drain of the transistor M6, and the source of the transistor M6 is connected to the signal input end of the next stage matching circuit; after the gates of the transistors M5 and M6 are connected in parallel, they are led out as the input end of the logic level signal Vb1, and the bypass switch is controlled by the logic level signal.

[0019] There are a total of N-1 power switches with the same topological structure, all of which are implemented using a transistor: the drain of the power switch (i.e., the corresponding transistor) is connected to the power supply Vdd and a filter capacitor with one end grounded, the source is connected in series with a choke inductor, and the gate is led out as the input end of the logic level signal, and the power switch is controlled by the logic level signal.

[0020] Because the noise coefficient of the cascade system is mainly determined by the first stage, and the first stage amplification circuit of the variable gain multi-stage broadband low noise amplifier is fixed, the noise coefficient is theoretically not affected by the switching of the working mode; and the linearity of the cascade system is mainly determined by the final stage, by optimizing the linearity of each stage amplification circuit of the variable gain multi-stage broadband low noise amplifier, the LNA can have good linearity no matter which stage of the amplifier is the final stage; therefore, the overall noise coefficient and linearity of the multi-stage broadband low noise amplifier remain basically consistent in different gain modes.

[0021] Compared with the prior art, the present invention has the following beneficial effects:

[0022] (1) Each stage of the multi-stage broadband low-noise amplifier with variable gain described in the present invention can be biased differently according to the design target so that the single-stage small signal gain of each stage is different; the power switch, the main switch and the bypass switch are controlled by logic level signals, and the conduction or shutdown of the other stages of the amplifier circuit except the first stage of the amplifier circuit can be flexibly controlled, and switching between up to 2^(N-1) gain modes can be achieved.

[0023] (2) In each stage of the amplifier circuit of a variable gain multi-stage broadband low noise amplifier described in the present invention, the input matching network design adopts a source degeneration inductance scheme to optimize the noise performance of the first stage amplifier circuit; the inter-stage matching circuit improves the overall gain flatness based on the idea of ​​gain compensation; the output matching circuit adopts a multi-stage LC matching network to match different frequency points, thereby reducing insertion loss and achieving good broadband output matching; compared with the existing broadband low noise amplifier with variable gain for narrowband applications, the design bandwidth of the variable gain multi-stage broadband low noise amplifier can reach more than 10 GHz.

[0024] (3) The variable gain multi-stage broadband low noise amplifier described in the present invention has a substantially consistent overall noise figure and linearity in different gain modes.

[0025] In summary, compared with the prior art, the present invention controls each switch through a logic level signal to achieve switching of multiple gain modes, the design bandwidth can reach more than 10 GHz, and the overall gain flatness and noise factor remain consistent in different gain modes. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 It is the overall structural block diagram of the present invention.

[0027] Figure 2 It is a topological structure principle diagram of the first stage amplifier circuit of the present invention.

[0028] Figure 3 It is a topological structure principle diagram of the nth (n≠1) stage amplifier circuit of the present invention.

[0029] Figure 4 It is a topological structure principle diagram of the inter-stage matching circuit of the present invention.

[0030] Figure 5 It is a topological structure principle diagram of the output matching circuit of the present invention.

[0031] Figure 6 It is a topological structure principle diagram of the bypass switch circuit of the present invention.

[0032] Figure 7 4 is a circuit diagram of a three-stage broadband low-noise amplifier according to an embodiment of the present invention.

[0033] Figure 8 It is a circuit diagram of the source degeneration inductor structure adopted for input matching of the present invention.

[0034] Fig. 9 It is the simulation result of the k factor changing with frequency in the stability simulation of the embodiment of the present invention.

[0035] Fig.10 It is the simulation result of the b factor changing with frequency in the stability simulation of the embodiment of the present invention. DETAILED DESCRIPTION

[0036] The technical solution of the present invention is further described in detail below in conjunction with the accompanying drawings. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without paying creative work.

[0037] The present invention provides a multi-stage broadband low noise amplifier with variable gain, and its structural block diagram is as follows: Figure 1 As shown. The variable gain multi-stage broadband low noise amplifier has a total of N (N≥2) stages of amplifier circuits, wherein the first and second stages of amplifier circuits are connected through the first inter-stage matching circuit, and the subsequent multi-stage amplifier circuits are connected in series with the main switch and the inter-stage matching circuit in sequence; the input end is connected to the first stage amplifier circuit through the series input matching circuit, and the Nth stage amplifier circuit is connected in series with the main switch and the output matching circuit to the signal output end in sequence; starting from the second stage, each stage amplifier circuit and the main switch are connected in parallel with a bypass switch as a whole; the first stage amplifier circuit is directly connected to the power supply Vdd, and starting from the second stage, a power switch is connected in series between the amplifier circuit and the power supply Vdd.

[0038] The power switch, the main switch and the bypass switch are controlled by logic level signals. If the gain of each stage of the amplifier circuit is different, at most 2^(N-1) gain modes can be switched through different combinations. The input matching network design adopts a source degeneration inductor solution to optimize the noise performance of the first stage amplifier circuit. The inter-stage matching circuit improves the overall gain flatness according to the idea of ​​gain compensation. The output matching circuit adopts a multi-stage LC matching network to match different frequency points, while reducing the insertion loss, achieving good broadband output matching. Therefore, the variable gain multi-stage broadband low-noise amplifier has a design bandwidth of more than 10 GHz.

[0039] Because the noise coefficient of the cascade system is mainly determined by the first stage, and the first stage amplification circuit of the variable gain multi-stage broadband low noise amplifier is fixed, the noise coefficient is theoretically not affected by the switching of the working mode; and the linearity of the cascade system is mainly determined by the final stage, by optimizing the linearity of each stage amplification circuit of the variable gain multi-stage broadband low noise amplifier, the low noise amplifier (LNA) can have good linearity no matter which stage of the amplifier is the final stage; therefore, the overall noise coefficient and linearity of the multi-stage broadband low noise amplifier remain basically consistent in different gain modes.

[0040] The variable gain multi-stage broadband low noise amplifier adopts 0.15um GaAs pHEMT technology.

[0041] In an embodiment of the present invention, a circuit schematic diagram of a variable gain three-stage broadband low noise amplifier is shown in FIG. Figure 7 As shown, the number of stages of the amplifier circuit is N=3.

[0042] The input matching circuit includes a capacitor C1 and an inductor L1. The signal input terminal RFin is connected in series with the capacitor C1 and the inductor L1 in sequence. The other port of the inductor L1 is connected to the gate of the transistor M3, i.e., the signal input terminal of the first-stage amplifier circuit. The noise of the first stage of the multi-stage low-noise amplifier determines the overall noise performance, and the insertion loss of the passive device used for input matching will be directly added to the overall noise coefficient of the LNA. Therefore, the input matching network should reduce the number of passive devices as much as possible. Ordinary passive matching networks such as T-type or L-type require two or three passive devices, while the source degeneration inductor structure only requires at least one inductor to complete the matching. Therefore, the present invention adopts a source degeneration inductor solution to complete the 50Ω impedance matching of the input terminal. The source degeneration inductor structure is as follows: Figure 8 shown.

[0043] The main feature of the source degeneration inductor structure is the degeneration inductance located at the source end of the common source tube. Considering the gate-source parasitic capacitance of the transistor, Figure 8 The input impedance can be written as:

[0044]

[0045] Where: L g is the inductance; g m is the transconductance of transistor M3.

[0046] If C gs and L g , L s Resonance is at the operating frequency ω0, that is:

[0047]

[0048] Then the input impedance is:

[0049]

[0050] At this time, as long as L is reasonably designed s The value of , so that:

[0051]

[0052] The impedance of the amplifier input can be matched. Therefore, the specific matching process is: after determining the target input impedance (50Ω) and the design center frequency, first calculate:

[0053]

[0054] After properly designing the transistor size to optimize the noise figure,

[0055]

[0056] To calculate the inductance L g The value of L g A coupling capacitor C1 with appropriate capacitance is connected in series before, which has little effect on impedance matching. Figure 7 As shown, the inductor L g That is, the inductance L1, the inductance L s Then use microstrip line T1 as equivalent.

[0057] There are a total of N-1 inter-stage matching circuits, which have the same topological structure and include 1 inductor and 1 capacitor; Figure 7 A variable gain three-stage broadband low noise amplifier is shown, with a total of two inter-stage matching circuits; Figure 4 The first inter-stage matching circuit shown is composed of an inductor L5 and a capacitor C4 connected in series in sequence, wherein the capacitor C4 also isolates the DC operating points of the front and rear stage amplifier circuits; the second inter-stage matching circuit is composed of an inductor L9 and a capacitor C8 connected in series in sequence, and similarly, the capacitor C8 also isolates the DC operating points of the front and rear stage amplifier circuits.

[0058] In the broadband range of 6 to 18 GHz, in order to improve the overall gain flatness, according to the idea of ​​gain compensation, the first and second inter-stage matching circuits perform broadband matching with 9 GHz and 15 GHz as the center frequencies respectively.

[0059] See also Figure 5The output matching circuit includes 4 sections of microstrip lines T2, T3, T4, and T5, and 3 capacitors C13, C14, and C15; after the 4 sections of microstrip lines T2, T3, T4, and T5 are connected in series in sequence, one end of the microstrip line T5 is connected to the signal output port RFout, the capacitor C13 with one end grounded is connected in parallel between the microstrip line T2 and the microstrip line T3, the capacitor C14 with one end grounded is connected in parallel between the microstrip line T3 and the microstrip line T4, and the capacitor C15 with one end grounded is connected in parallel between the microstrip line T4 and the microstrip line T5; the output matching circuit adopts a multi-stage LC matching structure. Considering that there are 4 different gain modes within the broadband range of 6 to 18 GHz, and the output matching results under different gain modes are different, it is first necessary to perform broadband matching of the 6 to 18 GHz design target in each gain mode to optimize the maximum gain and gain flatness, and then optimize the output matching circuit overall for the 4 different working modes.

[0060] Among them, Figure 5 As shown in the figure, the four microstrip lines T2, T3, T4, and T5 used in the output matching circuit are used to be equivalent to four inductors. First, considering that the output current will be very large, a wider microstrip line is used to replace the spiral inductor with a narrower line width. Second, in the layout design, too much use of inductors will lead to an excessively large chip area. Third, the high-frequency stability of the inductor is not as good as that of the microstrip line.

[0061] There are a total of N-1 main switches, which have the same topological structure and are controlled by logic level signals; Figure 7 A variable gain three-stage broadband low noise amplifier is shown, with two main switches in total. Considering that the isolation of depletion-type transistors is better than that of enhancement-type transistors, depletion-type transistors M12 and M22 are selected accordingly; one end of the main switch 1, i.e., transistor M12, is connected to the signal output end of the second-stage amplifier circuit, i.e., the drain of transistor M9, and the other end is connected to the input end of the second-stage inter-matching circuit, i.e., one end of inductor L9; the gate of transistor M12 is connected to the input end of the logic level signal Va1;

[0062] The main switch 2, i.e., transistor M22, has one end connected to the signal output end of the third-stage amplifier circuit, i.e., the drain of transistor M17, and the other end connected to the signal input end of the output matching circuit, i.e., one end of the microstrip line T2; the gate of transistor M22 is connected to the input end of the logic level signal Va2.

[0063] There are a total of N-1 bypass switches, with the same topological structure, and the bypass switches are controlled by logic level signals; Figure 6 and Figure 7A variable gain three-stage broadband low noise amplifier is shown, with two bypass switches in total. Considering that the isolation of depletion-type transistors is better than that of enhancement-type transistors, depletion-type transistors are selected accordingly; bypass switch 1 includes transistor M5, transistor M6 and a DC-blocking capacitor C6; the drain of transistor M5 is connected to the signal output end of the first inter-stage matching circuit, that is, one end of the DC-blocking capacitor C4, the source of transistor M5 is connected to the drain of transistor M6 after being connected in series with the DC-blocking capacitor C6, and the source of transistor M6 is connected to the signal input end of the second inter-stage matching circuit, that is, one end of the inductor L9; the gates of transistor M5 and transistor M6 are connected in parallel, and then lead out as the input end of the logic level signal Vb1;

[0064] The bypass switch 2 includes a transistor M20, a transistor M21 and a DC blocking capacitor C10; the drain of the transistor M20 is connected to the signal output end of the second inter-stage matching circuit, that is, one end of the DC blocking capacitor C8, the source of the transistor M20 is connected in series with the DC blocking capacitor C10 and then connected to the drain of the transistor M21, and the source of the transistor M21 is connected to the signal input end of the output matching circuit, that is, one end of the microstrip line T2; after the gates of the transistors M20 and M21 are connected in parallel, they are led out as the input end of the logic level signal Vb2.

[0065] There are a total of N-1 power switches, which have the same topological structure, and the power switches are controlled by logic level signals; Figure 7 A variable gain three-stage broadband low noise amplifier is shown, with a total of 2 power switches, corresponding to transistor M13 and transistor M16; power switch 1 is transistor M13, the drain of transistor M13 is connected to power supply Vdd and a filter capacitor C7 with one end grounded, the source is connected in series with a choke inductor L8, and the gate of transistor M13 is led out as the input end of logic level signal Va1;

[0066] The power switch 2 is a transistor M16, the drain of the transistor M16 is connected to the power supply Vdd and a filter capacitor C11 with one end grounded, the source is connected in series with a choke inductor L12, and the gate of the transistor M16 is connected to the input end of the logic level signal Va2.

[0067] like Figure 2 As shown, the first stage amplifier circuit includes a transistor M1, a transistor M2, a transistor M3, a transistor M4, a resistor R1, a resistor R2, a resistor R3, a resistor R4, an inductor L2, an inductor L3, an inductor L4, a capacitor C2, and a microstrip line T1;

[0068] like Figure 2As shown, the first-stage amplifier circuit is a common-source common-gate structure as a whole; the gate of the transistor M3 is connected to the input matching circuit, that is, one end of the inductor L1, the source of the transistor M3 is connected in series with a microstrip line T1 with one end grounded, the drain of the transistor M3 is connected in series with an inductor L3 and then connected to the source of the transistor M4; the gate of the transistor M4 is connected in series with a resistor R4 and then leads to the input end of the bias signal Vg1, and the drain of the transistor M4 is connected in parallel with the inductor L2, the inductor L4, and the first-stage matching circuit; in order to improve the circuit gain flatness and expand the bandwidth, an RL negative feedback circuit is introduced, and the circuit stability is adjusted by adjusting the resistance value of the negative feedback resistor R: the other end of the inductor L2 is connected to the resistor R2, and the other end of the resistor R2 is connected to the gate of the transistor M3; one end of the filter capacitor C3 is grounded, and the other end is connected to the power supply Vdd;

[0069] like Figure 2 As shown, a current mirror structure is used for biasing; the source of the transistor M1 is grounded, the gate and the drain are short-circuited, and the gate of the transistor M1 is connected in parallel with a capacitor C2 with one end grounded and a resistor R1 with one end connected to the gate of the transistor M3; wherein the capacitor C2 is an AC-to-ground capacitor, which is equivalent to a short circuit to the ground for the AC signal within the working frequency band, so as to prevent the AC signal from leaking to the bias circuit and affecting its normal operation; the transistor M2 is a switch tube for turning on or off the bias circuit, and is controlled by the gate voltage Vpd1; the drain of the transistor M2 is connected to the power supply Vdd, the source is connected in series with the resistor R3, and the other end of the resistor R3 is connected to the drain of the transistor M1.

[0070] The n-th stage amplifier circuits (n≠1) are N-1 in total, and their topological structures are the same. The number of stages can be determined according to the design objectives; Figure 7 A variable gain three-stage broadband low noise amplifier is shown, comprising a second stage amplification circuit and a third stage amplification circuit:

[0071] like Figure 3 As shown, the second stage amplifier circuit includes a transistor M7, a transistor M8, a transistor M9, a transistor M10, a transistor M11, a resistor R5, a resistor R6, a resistor R7, a resistor R8, an inductor L6, an inductor L7, an inductor L8, and a capacitor C5;

[0072] like Figure 3As shown, the second-stage amplifier circuit is a common-source common-gate structure as a whole; the gate of the transistor M8 is connected to the signal output end of the first-stage inter-matching circuit, that is, one end of the capacitor C4; the drain of the transistor M8 is connected in series with the inductor L7; in order to further reduce the leakage current when the second-stage amplifier circuit is turned off, the source of the transistor M8 is connected in series with a transistor M7 used as a switch; wherein the source of the transistor M7 is grounded, and the gate leads to the input end of the logic level signal Va1. When the state of the amplifier circuit of this stage is turned off, by setting Va1 to a low level "0", the leakage current of the amplifier circuit of this stage is smaller, the turn-off effect is better, and the isolation is also improved, avoiding the previous stage The signal is nonlinearly coupled to the subsequent stage through this point, thus affecting the overall linearity; the other end of the inductor L7 is connected to the source of the transistor M9, and the gate of the transistor M9 is connected in series with a resistor R8 and then leads to the input end of the bias signal Vg2, and the drain of the transistor M9 is connected in parallel with the inductor L6, the inductor L8 and the main switch 1; one end of the filter capacitor C7 is grounded, and the other end is connected to the power supply Vdd; in order to improve the circuit gain flatness and expand the bandwidth, the RL negative feedback circuit is introduced, and the circuit stability is adjusted by adjusting the resistance value of the negative feedback resistor R7: the other end of the inductor L6 is connected to the resistor R7, and the other end of the resistor R7 is connected to the gate of the transistor M8;

[0073] like Figure 3 As shown, a current mirror structure is used for biasing: the source of the transistor M10 is grounded, the gate and the drain are short-circuited, and the gate of the transistor M10 is connected in parallel with a capacitor C5 with one end grounded and a resistor R6 with one end connected to the gate of the transistor M8; wherein the capacitor C5 is an AC-to-ground capacitor, which is equivalent to a short circuit to the ground for the AC signal within the working frequency band, thereby preventing the AC signal from leaking to the bias circuit and affecting its normal operation; the transistor M11 is a switch tube for turning on or off the bias circuit, and is controlled by the gate voltage Vpd2; correspondingly, when the amplifier circuit of this stage is bypassed, the gate voltage Vpd2 is set to a low level "0", so that the shutdown effect of this stage is better, and the static power consumption is also reduced; the drain of the transistor M11 is connected to the power supply Vdd, the source is connected in series with the resistor R5, and the other end of the resistor R5 is connected to the drain of the transistor M10.

[0074] like Figure 7 As shown, the third stage amplifier circuit includes a transistor M14, a transistor M15, a transistor M16, a transistor M17, a transistor M18, a transistor M19, a resistor R10, a resistor R11, a resistor R12, a resistor R13, an inductor L10, an inductor L11, an inductor L12, a capacitor C9, and a capacitor C12;

[0075] Reference Figure 7, the third-stage amplifier circuit is a common-source and common-gate structure as a whole; the gate of the transistor M18 is connected to the signal output end of the second-stage inter-matching circuit, that is, one end of the capacitor C8; the drain of the transistor M18 is connected in series with an inductor L11; in order to further reduce the leakage current when the second-stage amplifier circuit is turned off, the source of the transistor M18 is connected in series with a transistor M19 used as a switch; wherein the source of the transistor M19 is grounded, and the gate is led to the input end of the logic level signal Va2; when the state of the amplifier circuit of this stage is turned off, by setting Va2 to a low level "0", the leakage current of the amplifier circuit of this stage is smaller, the shutdown effect is better, and the isolation is also improved, avoiding the nonlinear coupling of the previous stage signal to the next stage through this place, thereby affecting the overall linearity; the other end of the inductor L11 is connected to the source of the transistor M17, and the gate of the transistor M17 is connected in series with a resistor R12 and then led to the bias signal The input end of signal Vg3 and the drain of transistor M17 are connected in parallel with inductor L10, inductor L12 and main switch 2; one end of filter capacitor C12 is grounded, and the other end is connected to power supply Vdd; in order to improve the circuit gain flatness and expand the bandwidth, an RL negative feedback circuit is introduced, and the circuit stability is adjusted by adjusting the resistance value of negative feedback resistor R: the other end of inductor L10 is connected to resistor R11, and the other end of resistor R11 is connected to the gate of transistor M18; in particular, since the third-stage amplifier circuit is the last stage, considering further expanding the bandwidth during output matching, a capacitor C12 is connected in parallel to the signal output port of the third-stage amplifier circuit, so that capacitor C12, inductor L12 and gate-drain parasitic capacitance of M17 will form a π-type network to further improve the bandwidth of the circuit; at the same time, in order to improve the stability of the circuit, a low-value resistor R13 with one end grounded is connected in series after capacitor C12.

[0076] Reference Figure 7 , a current mirror structure is used for biasing: the source of the transistor M14 is grounded, the gate and the drain are short-circuited, and the gate of the transistor M14 is connected in parallel with a capacitor C9 with one end grounded and a resistor R10 with one end connected to the gate of the transistor M18; wherein the capacitor C9 is an AC-to-ground capacitor, which is equivalent to a short circuit to the ground for the AC signal within the working frequency band, thereby preventing the AC signal from leaking to the bias circuit and affecting its normal operation; the transistor M15 is a switch tube for turning on or off the bias circuit, and is controlled by the gate voltage Vpd3; correspondingly, when the amplifier circuit of this stage is bypassed, the gate voltage Vpd3 is set to a low level "0", so that the shutdown effect of this stage is better, and the static power consumption is also reduced; the drain of the transistor M15 is connected to the power supply Vdd, the source is connected in series with the resistor R9, and the other end of the resistor R9 is connected to the drain of the transistor M14.

[0077] like Figure 7In one embodiment of the present invention shown in FIG. 1 , the drain power supply voltage Vdd of the three-stage broadband low noise amplifier is set to 5V; the bias voltages Vg1, Vg2, and Vg3 are reasonably set so that the small signal gain of the three-stage amplifier circuit decreases step by step, and are set to G1, G2, and G3 respectively; then, within the target frequency band of 6 to 18 GHz, the power switch, the main switch, and the bypass switch are controlled by logic level signals, so that the variable gain three-stage broadband low noise amplifier can be switched between four different gain gears, as shown in Table 1, wherein (Va, Vb) represents the logic signals set corresponding to the Va and Vb ports: "0" represents a low level signal, and "1" represents a high level signal.

[0078] Gear (Va1,Vb1) (Va2, Vb2) Gain / dB 1 (0,1) (0,1) G1 2 (0,1) (1,0) G1+G3 3 (1,0) (0,1) G1+G2 4 (1,0) (1,0) G1+G2+G3

[0079] Table 1 Gain level table of the three-stage broadband low noise amplifier according to the embodiment of the present invention

[0080] In the target frequency band of 6 to 18 GHz, when the variable gain three-stage broadband low noise amplifier is switched from different gain gears 1 to 4 in sequence, the gain flatness is approximately 0.7 dB, 1.2 dB, 1.4 dB, and 1.7 dB, respectively, and the noise figure is less than 1.5 dB; and at a fixed frequency, when switching between the four gears, the overall noise figure floating range is within ±0.01 dB; compared with the prior art, within the broadband range of 12 GHz, switching between four different gain gears is achieved in a three-stage cascade manner, while maintaining relative consistency of gain flatness and noise figure; in addition, the stability simulation of the overall variable gain multi-stage broadband low noise amplifier is carried out. Fig. 9 and Fig.10 These are the simulation results of the k factor and b factor changing with frequency, and it can be seen that within the target frequency band, k>1 and b>0 are satisfied. According to the kb judgment method, the variable gain multi-stage broadband low noise amplifier is absolutely stable within the target frequency band of 6 to 18 GHz.

[0081] In summary, each stage of the amplifier circuit of the present invention can be biased differently according to the design goal so that the single-stage small signal gain of each stage is different; the power switch, the main switch and the bypass switch are controlled by logic level signals, and switching between 2^(N-1) gain modes at most can be achieved; the input matching network design adopts the source degeneration inductance scheme to optimize the noise performance of the first-stage amplifier circuit; the inter-stage matching circuit improves the overall gain flatness according to the idea of ​​gain compensation; the output matching circuit adopts a multi-stage LC matching network to match different frequency points, while reducing the insertion loss, achieving good broadband output matching; the variable gain multi-stage broadband low-noise amplifier has a design bandwidth of more than 10GHz, and in different gain modes, the overall noise coefficient and linearity remain basically consistent.

[0082] Finally, it should be noted that the above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Although the present invention has been described in detail with reference to the above embodiments, it is still possible for a person skilled in the art to modify the methods described in the above embodiments, such as changing the names of the methods, etc. Any modification, equivalent substitution, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A variable gain multi-stage broadband low noise amplifier, characterized in that The invention comprises N (N≥2) stages of amplification circuits, wherein the first and second stages of amplification circuits are connected through the first inter-stage matching circuit, and the subsequent stages of amplification circuits are connected in series with a main switch and an inter-stage matching circuit in sequence; the input end is connected to the first stage of amplification circuit through a series input matching circuit, and the N-stage amplification circuit is connected in series with the main switch and the output matching circuit to the signal output end in sequence; starting from the second stage, each stage of amplification circuit and the main switch are connected in parallel with a bypass switch as a whole; the first stage of amplification circuit is directly connected to a power supply Vdd, and starting from the second stage, a power switch is connected in series between the amplification circuit and the power supply Vdd.

2. A variable gain multi-stage broadband low noise amplifier according to claim 1, characterized in that: The variable-gain multi-stage broadband low-noise amplifier is manufactured using a 0.15um GaAs pHEMT process.

3. A variable gain multi-stage broadband low noise amplifier according to claim 1, characterized in that: The first-stage amplifier circuit topology structure includes a transistor M1, a transistor M2, a transistor M3, a transistor M4, a resistor R1, a resistor R2, a resistor R3, a resistor R4, an inductor L2, an inductor L3, an inductor L4, a capacitor C2, and a microstrip line T1; the gate of the transistor M3 is connected to the input matching circuit, the source of the transistor M3 is connected in series with a microstrip line T1 with one end grounded, the drain of the transistor M3 is connected in series with an inductor L3 and then connected to the source of the transistor M4; the gate of the transistor M4 is connected in series with a resistor R4 and then led out as the input end of the bias signal Vg1, the drain of the transistor M4 is connected in series with a resistor R4 and then led out as the input end of the bias signal Vg1, and the gate of the transistor M4 is connected in series with a microstrip line T1 with one end grounded. Inductor L2, inductor L4 and the first stage matching circuit are connected in parallel; the other end of inductor L2 is connected to resistor R2, and the other end of resistor R2 is connected to the gate of transistor M3; one end of filter capacitor C3 is grounded, and the other end is connected to power supply Vdd; the source of transistor M1 is grounded, and the gate and drain are short-circuited, and the gate of transistor M1 is connected in parallel with capacitor C2 with one end grounded and resistor R1 with one end connected to the gate of transistor M3; the gate of transistor M2 is controlled by voltage Vpd1, and its drain is connected to power supply Vdd, the source is connected in series with resistor R3, and the other end of resistor R3 is connected to the drain of transistor M1.

4. The variable gain multi-stage broadband low noise amplifier according to claim 1, characterized in that: The n-th stage amplifier circuit (n≠1) is N-1 in total, and its topological structure is the same, and the number of stages can be determined according to the design target; the n-th stage amplifier circuit (n≠1) includes a transistor M7, a transistor M8, a transistor M9, a transistor M10, a transistor M11, a resistor R5, a resistor R6, a resistor R7, a resistor R8, an inductor L6, an inductor L7, an inductor L8, and a capacitor C5; the gate of the transistor M8 is connected to the n-1-th stage matching circuit and the bypass switch n-1; the drain of the transistor M8 is connected in series with the inductor L7; the source of the transistor M8 is connected in series with a transistor M7 used as a switch; wherein the source of the transistor M7 is grounded, and the gate is led out as the input end of the logic level signal Va1; the other end of the inductor L7 is connected to the source of the transistor M9, and the gate of the transistor M9 is connected in series with a resistor R8 and then led out as a bias signal The input end of Vg2 and the drain of transistor M9 are simultaneously connected in parallel with inductor L6, inductor L8 and main switch n-1; one end of filter capacitor C7 is grounded, and the other end is connected to power supply Vdd; the other end of inductor L6 is connected to resistor R7, and the other end of resistor R7 is connected to the gate of transistor M8; in particular, when designing the last stage of amplifier circuit, a capacitor is connected in parallel to the signal output port, and the other end of the capacitor is connected in series with a low-value resistor with one end grounded; the source of transistor M10 is grounded, the gate and drain are short-circuited, and the gate of transistor M10 is simultaneously connected in parallel with capacitor C5 with one end grounded and resistor R6 with one end connected to the gate of transistor M8; the gate of transistor M11 is controlled by voltage Vpd2, its drain is connected to power supply Vdd, the source is connected in series with resistor R5, and the other end of resistor R5 is connected to the drain of transistor M10.

5. The variable gain multi-stage broadband low noise amplifier according to claim 1, characterized in that: The input matching circuit includes a capacitor C1 and an inductor L1; the signal input terminal RFin is connected in series with the capacitor C1 and the inductor L1 in sequence, and the other port of the inductor L1 is connected to the gate of the transistor M3, that is, the signal input terminal of the first-stage amplifier circuit; in order to improve the noise performance of the multi-stage low-noise amplifier, the input matching network design adopts a source degeneration inductor solution to complete the 50Ω impedance matching of the input terminal.

6. The variable gain multi-stage broadband low noise amplifier according to claim 1, characterized in that: There are a total of N-1 inter-stage matching circuits with the same topological structure, including an inductor and a capacitor connected in series, the other end of the inductor L5 is connected to the previous stage amplifier circuit, and the other end of the capacitor C4 is connected to the input end of the next stage amplifier circuit.

7. The variable gain multi-stage broadband low noise amplifier according to claim 1, characterized in that: The output matching circuit includes microstrip lines T2, T3, T4, and T5, and capacitors C13, C14, and C15. After the microstrip lines T2, T3, T4, and T5 are connected in series in sequence, one end of the microstrip line T5 is connected to the signal output port RFout, a capacitor C13 with one end grounded is connected in parallel between the microstrip line T2 and the microstrip line T3, a capacitor C14 with one end grounded is connected in parallel between the microstrip line T3 and the microstrip line T4, and a capacitor C15 with one end grounded is connected in parallel between the microstrip line T4 and the microstrip line T5. The output matching network adopts a multi-stage LC matching structure to optimize the maximum gain and gain flatness, and realize broadband output matching under different gain modes.

8. The variable gain multi-stage broadband low noise amplifier of claim 1, characterized in that: There are a total of N-1 main switches with the same topological structure, all of which are implemented using a transistor: one end of the main switch (i.e., the corresponding transistor) is connected to the signal output end of the previous stage amplifier circuit, and the other end is connected to the input end of the next stage matching circuit. The gate of the transistor is connected to the input end of the logic level signal, and the main switch is controlled by the logic level signal.

9. The variable gain multi-stage broadband low noise amplifier according to claim 1, characterized in that: There are a total of N-1 bypass switches with the same topological structure, including a transistor M5, a transistor M6 and a DC blocking capacitor C6: the drain of the transistor M5 is connected to the signal output end of the previous stage matching circuit, the source of the transistor M5 is connected in series with the DC blocking capacitor C6 and then connected to the drain of the transistor M6, and the source of the transistor M6 is connected to the signal input end of the next stage matching circuit; after the gates of the transistors M5 and M6 are connected in parallel, they are led out as the input end of the logic level signal Vb1, and the bypass switch is controlled by the logic level signal.

10. The variable gain multi-stage broadband low noise amplifier according to claim 1, characterized in that: There are a total of N-1 power switches with the same topological structure, all of which are implemented using a transistor: the drain of the power switch (i.e., the corresponding transistor) is connected to the power supply Vdd and a filter capacitor with one end grounded, the source is connected in series with a choke inductor, and the gate is led out as the input end of the logic level signal, and the power switch is controlled by the logic level signal.

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