Double-sided asymmetric mesa type piezoelectric quartz wafer

Abstract

The invention discloses a double-sided asymmetric table-board type piezoelectric quartz wafer. The quartz crystal wafer comprises a quartz crystal wafer body (1), two sides of the quartz crystal wafer body (1) are respectively provided with a boss, and the bosses on the two sides of the quartz crystal wafer are respectively a large-size boss (2) and a small-size boss (3). And the arrangement position of the small-size boss (3) is correspondingly positioned in the large-size boss (2). The invention provides a double-sided asymmetric mesa type piezoelectric quartz wafer. Bosses on the two sides of the quartz wafer are arranged to be a large-size boss (2) and a small-size boss (3) respectively. The arrangement position of the small-size boss (3) is correspondingly located on the inner side of the large-size boss (2), the actual vibration area of the quartz wafer is a small area, namely the vibration area of the quartz wafer is the area of the small-size boss (3), frequency change caused by dislocation of the upper boss and the lower boss is avoided, and the vibration area of the electrode can be utilized to the maximum extent.

Description

Technical Field

[0001] The invention relates to the field of piezoelectric quartz wafers, in particular to a double-sided asymmetric table-type piezoelectric quartz wafer. Background Art

[0002] As a device that generates stable oscillation signals, quartz resonators are widely used in communications, radar, precision computing, precision balances, mobile phones, aviation, electronic watches, automobiles and other fields. Traditional quartz resonator wafers are formed by mechanical processing methods such as wafer grinding, polishing, wafer size wire cutting, and drum grinding. With the miniaturization and high frequency development of quartz resonators, the processing technology has gradually been upgraded from mechanical processing to semiconductor micro-processing technology.

[0003] Theoretically, the displacement of thickness shear is a wave propagating in the thickness direction. When considering C0 and C1, the electrode is generally designed to be larger than the boss. If the boss of the piezoelectric quartz wafer with a double boss structure is misaligned, the thickness dimension of the vibration area is inconsistent in the non-overlapping area, resulting in different waves and a change in frequency. This will generate non-harmonic waves that are not the main vibrations, share the electric field energy, reduce the amplitude of the oscillation, and even jump the frequency to the non-harmonic wave, forming a frequency jump. The upper and lower bosses of a qualified quartz wafer cannot be misaligned. Therefore, the quartz wafer has the problem of greater processing difficulty and low qualified rate of finished products.

[0004] The applicant has found that the prior art has at least the following technical problems:

[0005] In the prior art, the piezoelectric quartz wafer with a double boss structure has the problems of being difficult to process and having a low qualified rate of finished products. Summary of the invention

[0006] The purpose of the present invention is to provide a double-sided asymmetric table-type piezoelectric quartz wafer to solve the technical problems of the piezoelectric quartz wafer with a double-convex table structure in the prior art, which is difficult to process and has a low qualified rate of finished products. The preferred technical solutions among the many technical solutions provided by the present invention can produce many technical effects as described below.

[0007] To achieve the above object, the present invention provides the following technical solutions:

[0008] The present invention provides a double-sided asymmetric table-type piezoelectric quartz wafer, comprising a quartz wafer body, wherein a boss is provided on both sides of the quartz crystal body, and the bosses on both sides of the quartz wafer body are respectively arranged as a large-size boss and a small-size boss; the arrangement position of the small-size boss corresponds to the inner side of the large-size boss.

[0009] Furthermore, any two opposite edges of the small-sized boss correspond to coincide with any two opposite edges of the large-sized boss; or, the edge of the small-sized boss is correspondingly located on the inner side of the edge of the large-sized boss.

[0010] Furthermore, the alignment error between the large-size boss and the small-size boss satisfies the following formula (1) and / or the following formula (2):

[0011] T1=L1*t*(0.8%-3.5%) (1);

[0012] T2=L2*t*(0.8%-3.5%) (2);

[0013] In formula (1), T1 is the distance between the edge of the small-size boss in the width direction and the edge of the large-size boss in the width direction, um; L1 is the length of the quartz wafer body, mm; t is the thickness of the quartz wafer body, um;

[0014] In formula (2), T2 is the distance between the edge of the small-size boss in the length direction and the edge of the large-size boss in the length direction, um; L2 is the width of the quartz wafer body, mm; t is the thickness of the quartz wafer body, um.

[0015] Furthermore, the alignment error between the large-size boss and the small-size boss satisfies the following formula (3) and / or the following formula (4):

[0016] T1 = L1*t*(1%-3%) (3);

[0017] T2 = L2*t*(1%-3%) (4);

[0018] In formula (3), T1 is the distance between the edge of the small-size boss in the width direction and the edge of the large-size boss in the width direction, um; L1 is the length of the quartz wafer body, mm; t is the thickness of the quartz wafer body, um;

[0019] In formula (4), T2 is the distance between the edge of the small-size boss in the length direction and the edge of the large-size boss in the length direction, um; L2 is the width of the quartz wafer body, mm; t is the thickness of the quartz wafer body, um.

[0020] Furthermore, the alignment error between the large-size boss and the small-size boss satisfies the following formula (5) and / or the following formula (6):

[0021] T1=L1*t*2% (5);

[0022] T2 = L2*t*2% (6);

[0023] In formula (5), T1 is the distance between the edge of the small-size boss in the width direction and the edge of the large-size boss in the width direction, um; L1 is the length of the quartz wafer body, mm; t is the thickness of the quartz wafer body, um;

[0024] In formula (6), T2 is the distance between the edge of the small-sized boss in the length direction and the edge of the large-sized boss in the length direction, um; L2 is the width of the quartz wafer body, mm; t is the thickness of the quartz wafer body, um.

[0025] Based on the above technical solution, the embodiments of the present invention can at least produce the following technical effects:

[0026] The double-sided asymmetric table-type piezoelectric quartz wafer provided by the present invention has bosses on both sides of the quartz wafer body respectively set as large-size bosses and small-size bosses; the setting position of the small-size bosses corresponds to the inner side of the large-size bosses, and the actual vibration area of ​​the quartz wafer is a relatively small area, that is, the vibration area of ​​the quartz wafer is the small-size boss area, which avoids the frequency change caused by the misalignment of the upper and lower bosses, and can maximize the use of the electrode vibration area. From the perspective of the processing technology of the quartz wafer, the processing difficulty is reduced and the qualified rate of finished products is improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0028] Figure 1 It is a schematic diagram of the structure of Embodiment 1 to Embodiment 15 of the present invention;

[0029] Figure 2 yes Figure 1 Schematic top views of Examples 1 to 5 of the present invention;

[0030] Figure 3 1 is a schematic top view of Embodiment 6 to Embodiment 10 of the present invention;

[0031] Figure 4 is a schematic top view of Embodiment 11 to Embodiment 15 of the present invention;

[0032] Figure 5 is a simulation schematic diagram of embodiment 1 of the present invention;

[0033] Figure 6 is a simulation schematic diagram of embodiment 2 of the present invention;

[0034] Figure 7is a simulation schematic diagram of Embodiment 7 of the present invention;

[0035] Figure 8 is a simulation schematic diagram of Embodiment 8 of the present invention;

[0036] Fig. 9 is a simulation schematic diagram of embodiment 3 of the present invention;

[0037] Fig.10 is a schematic top view of Comparative Example 1 of the present invention;

[0038] Fig.11 It is a schematic top view of comparative example 2 of the present invention.

[0039] In the figure: 1. quartz wafer body; 2. large-size boss; 3. small-size boss; 4. boss one; 5. boss two. DETAILED DESCRIPTION

[0040] To make the purpose, technical solution and advantages of the present invention clearer, the technical solution of the present invention will be described in detail below. Obviously, the described embodiments are only part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other implementation methods obtained by ordinary technicians in this field without creative work belong to the scope of protection of the present invention.

[0041] 1. Embodiment:

[0042] A double-sided asymmetric table-type piezoelectric quartz wafer comprises a quartz wafer body 1, with a boss provided on both sides of the quartz wafer body 1, the bosses on both sides of the quartz wafer body 1 are respectively arranged as a large-size boss 2 and a small-size boss 3; the arrangement position of the small-size boss 3 corresponds to the inner side of the large-size boss 2.

[0043] The double-sided asymmetric table-type piezoelectric quartz wafer provided by the present invention has bosses on both sides of the quartz wafer body 1 respectively set as large-size bosses 2 and small-size bosses 3; the setting position of the small-size boss 3 corresponds to the inner side of the large-size boss 2, and the actual vibration area of ​​the quartz wafer is a relatively small area, that is, the vibration area of ​​the quartz wafer is the area of ​​the small-size boss 3, which avoids the frequency change caused by the misalignment of the upper and lower bosses, and can maximize the use of the electrode vibration area. From the perspective of the processing technology of the quartz wafer, the processing difficulty is reduced and the qualified rate of finished products is improved.

[0044] As an optional embodiment, any two opposite edges of the small-sized boss 3 coincide with any two opposite edges of the large-sized boss 2 ; or, the edge of the small-sized boss 3 is located on the inner side of the edge of the large-sized boss 2 .

[0045] As an optional implementation, the alignment error between the large-size boss 2 and the small-size boss 3 satisfies the following formula (1) and / or the following formula (2):

[0046] T1=L1*t*(0.8%-3.5%) (1);

[0047] T2=L2*t*(0.8%-3.5%) (2);

[0048] In formula (1), T1 is the distance between the edge of the small-size boss 3 in the width direction and the edge of the large-size boss 2 in the width direction, um; L1 is the length of the quartz wafer body 1, mm; t is the thickness of the quartz wafer body 1, um;

[0049] In formula (2), T2 is the distance between the edge of the small-size boss 3 in the length direction and the edge of the large-size boss 2 in the length direction, um; L2 is the width of the quartz wafer body 1, mm; t is the thickness of the quartz wafer body 1, um. Alignment error between large-size boss 2 and small-size boss 3

[0050] As an optional implementation, the alignment error between the large-size boss 2 and the small-size boss 3 satisfies the following formula (3) and / or the following formula (4):

[0051] T1 = L1*t*(1%-3%) (3);

[0052] T2 = L2*t*(1%-3%) (4);

[0053] In formula (3), T1 is the distance between the edge of the small-size boss 3 in the width direction and the edge of the large-size boss 2 in the width direction, um; L1 is the length of the quartz wafer body 1, mm; t is the thickness of the quartz wafer body 1, um;

[0054] In formula (4), T2 is the distance between the edge of the small-size boss 3 in the length direction and the edge of the large-size boss 2 in the length direction, um; L2 is the width of the quartz wafer body 1, mm; t is the thickness of the quartz wafer body 1, um.

[0055] As an optional implementation, the alignment error between the large-size boss 2 and the small-size boss 3 satisfies the following formula (5) and / or the following formula (6):

[0056] T1=L1*t*2% (5);

[0057] T2 = L2*t*2% (6);

[0058] In formula (5), T1 is the distance between the edge of the small-size boss 3 in the width direction and the edge of the large-size boss 2 in the width direction, um; L1 is the length of the quartz wafer body 1, mm; t is the thickness of the quartz wafer body 1, um;

[0059] In formula (6), T2 is the distance between the edge of the small-sized boss 3 in the length direction and the edge of the large-sized boss 2 in the length direction, um; L2 is the width of the quartz wafer body 1, mm; t is the thickness of the quartz wafer body 1, um.

[0060] like Figure 1-Figure 4 The structure diagram of Example 1 to Example 15 is shown in the following Table 1:

[0061] Table 1 Example data and experimental results

[0062]

[0063] 2. Comparative ratio:

[0064] Comparative Example 1:

[0065] like Figure 5 As shown:

[0066] The boss 1 4 and boss 2 5 on both sides of the quartz wafer body 1 have the same size, are offset in the length direction, and the offset spacing T3 is 8um. The specific size data and the results of the temperature measurement simulation experiment are shown in Table 2 and Fig.10 shown.

[0067] Comparative Example 2:

[0068] like Figure 6 As shown:

[0069] The boss 1 4 and boss 2 5 on both sides of the quartz wafer body 1 have the same size, are offset in the width direction, and the offset spacing T4 is 4um. The specific size data and the results of the temperature measurement simulation experiment are shown in Table 2 and Fig.11 shown.

[0070] Table 2 Example data and experimental results

[0071] T3,um L1, mm T4,um L2, mm t,um Experimental Results Comparative Example 1 8 8 0 6 30 Unqualified, unacceptable Comparative Example 2 0 8 4 6 30 Unqualified, unacceptable

[0072] 2. Experimental example:

[0073] 1. Example 1, Example 2, Example 3, Example 7, Example 8 and Comparative Example 1 and Comparative Example 2 were subjected to temperature measurement simulation experiments. The results of the temperature measurement simulation experiments are shown in Table 1, Table 2 and Figure 5-Figure 11 As shown, in Figure 5-Figure 11 middle:

[0074] The horizontal axis represents temperature in °C;

[0075] The left ordinate represents the difference between the actual curve obtained by simulation and the ideal state curve, in ppm;

[0076] The right ordinate axis represents energy intensity;

[0077] The green curve represents the theoretical curve of AT cut in the temperature measurement simulation experiment;

[0078] The red curve represents the actual curve obtained by simulation when the piezoelectric quartz wafer in the embodiment is subjected to a temperature measurement simulation experiment, simulating the difference between the actual jump and the ideal state;

[0079] The blue curve represents the vibration intensity in the electrode area.

[0080] 2. Experimental result determination method:

[0081] The difference between the actual curve obtained by simulation and the ideal state curve at each temperature point is no more than 50ppm, which is qualified and acceptable.

[0082] 3. Experimental results:

[0083] like Figure 5-Figure 9 When the piezoelectric quartz chips obtained in Example 1, Example 2, Example 3, Example 7, and Example 8 are subjected to temperature measurement simulation experiments, the difference between the simulated actual curve and the ideal state curve at each temperature point is no more than 50ppm, which is qualified and acceptable.

[0084] like Figure 10-11 When the piezoelectric quartz wafers obtained in Example 1 and Example 2 were subjected to temperature measurement simulation experiments, the difference between the simulated actual curve and the ideal state curve at each temperature point was greater than 50ppm, which was unqualified and unacceptable.

[0085] The above description is only a specific implementation mode of the present invention, but the protection scope of the present invention is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed by the present invention, which should be covered by the protection scope of the present invention.

Claims

1. A double-sided asymmetric table-type piezoelectric quartz wafer, comprising a quartz wafer body (1), wherein a boss is provided on each side of the quartz wafer body (1), and wherein: The bosses on both sides of the quartz wafer body (1) are respectively arranged as a large-sized boss (2) and a small-sized boss (3); the arrangement position of the small-sized boss (3) is correspondingly located inside the large-sized boss (2).

2. The double-sided asymmetric mesa-type piezoelectric quartz wafer according to claim 1, characterized in that: Any two opposite edges of the small-sized boss (3) coincide with any two opposite edges of the large-sized boss (2); or, the edge of the small-sized boss (3) is located on the inner side of the edge of the large-sized boss (2).

3. The double-sided asymmetric mesa-type piezoelectric quartz wafer according to claim 2, characterized in that: The alignment error between the large-sized boss (2) and the small-sized boss (3) satisfies the following formula (1) and / or the following formula (2): T1=L1*t* (0.8%-3.5%) (1); T2=L2*t* (0.8%-3.5%) (2); In formula (1), T1 is the distance between the edge of the small-sized boss (3) in the width direction and the edge of the large-sized boss (2) in the width direction, um; L1 is the length of the quartz wafer body (1), mm; t is the thickness of the quartz wafer body (1), um; In formula (2), T2 is the distance between the edge of the small-sized boss (3) in the length direction and the edge of the large-sized boss (2) in the length direction, um; L2 is the width of the quartz wafer body (1), mm; and t is the thickness of the quartz wafer body (1), um.

4. The double-sided asymmetric mesa-type piezoelectric quartz wafer according to claim 2, characterized in that: The alignment error between the large-sized boss (2) and the small-sized boss (3) satisfies the following formula (3) and / or the following formula (4): T1=L1*t* (1%-3%) (3); T2=L2*t* (1%-3%) (4); In formula (3), T1 is the distance between the edge of the small-sized boss (3) in the width direction and the edge of the large-sized boss (2) in the width direction, um; L1 is the length of the quartz wafer body (1), mm; t is the thickness of the quartz wafer body (1), um; In formula (4), T2 is the distance between the edge of the small-sized boss (3) in the length direction and the edge of the large-sized boss (2) in the length direction, um; L2 is the width of the quartz wafer body (1), mm; and t is the thickness of the quartz wafer body (1), um.

5. The double-sided asymmetric mesa-type piezoelectric quartz wafer according to claim 2, characterized in that: The alignment error between the large-sized boss (2) and the small-sized boss (3) satisfies the following formula (5) and / or the following formula (6): T1=L1*t*2% (5); T2=L2*t*2% (6); In formula (5), T1 is the distance between the edge of the small-sized boss (3) in the width direction and the edge of the large-sized boss (2) in the width direction, um; L1 is the length of the quartz wafer body (1), mm; t is the thickness of the quartz wafer body (1), um; In formula (6), T2 is the distance between the edge of the small-sized boss (3) in the length direction and the edge of the large-sized boss (2) in the length direction, um; L2 is the width of the quartz wafer body (1), mm; and t is the thickness of the quartz wafer body (1), um.

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