Low surface concentration diffusion process for N-type battery

Abstract

The invention discloses a low surface concentration diffusion process for an N-type battery, which relates to the technical field of battery manufacturing and comprises the following steps of: (1) simultaneously corroding a light receiving surface and a backlight surface of a silicon wafer by using an etchant solution to remove damaged layers of the light receiving surface and the backlight surface of the silicon wafer; (2) independently corroding the light receiving surface of the silicon wafer with the damaged layer removed by using a corrosion solution so as to form a textured surface on the light receiving surface; (3) cleaning and drying the textured silicon wafer; (4) putting the textured silicon wafer into a quartz boat carrier, and then feeding the silicon wafer into a quartz furnace tube; (5) evacuating the furnace tube through a film pump, and keeping the furnace tube in a low-pressure state, and (6) heating the furnace tube to reach a corresponding temperature condition. According to the invention, the total gas flow of the special gas Bc13 introduced into the furnace tube is reduced, so that the amount of B atoms deposited on the surface of the silicon wafer is reduced, the carrier recombination is reduced, and the open-circuit voltage is increased, thereby achieving the purpose of improving the efficiency.

Description

Technical Field

[0001] The present invention relates to the technical field of battery manufacturing, and in particular to a low surface concentration diffusion process for an N-type battery. Background Art

[0002] It is particularly important to improve the photoelectric conversion efficiency of solar cells. At present, the junction depth of the diffused emitter of traditional high-efficiency cells is basically around 0.2um to 0.3um, and the absorption loss of short waves is more obvious. If you want to prepare a 0.1um to 0.2um diffused shallow junction through the traditional diffusion process, the diffusion square resistance will be very high and the surface concentration will be low, which will easily cause problems with the alloy ohmic contact in the screen process, resulting in the failure of the photoelectric conversion efficiency of the solar cell. Therefore, it is very difficult to obtain a diffused shallow junction through the current traditional solar manufacturing process.

[0003] At present, the photovoltaic market is still dominated by conventional crystalline silicon cells. The cost-effectiveness of high-efficiency structural cells still cannot compete with conventional cells. Improving the conversion efficiency of conventional batteries is the common pursuit of all photovoltaic companies.

[0004] The preparation of shallow junction high square resistance emitter is an important way to improve the conversion efficiency of crystalline silicon cells. This process can not only reduce the front surface recombination to increase the open circuit voltage, but also greatly improve the short-wave spectral response to increase the short-circuit current. The successful development of high square resistance silver paste has solved the problems of excessive series resistance and easy burn-through of the emitter. Increasing the square resistance of the emitter has become an important means to improve the efficiency of the cell. For polycrystalline silicon cells, the current square resistance can be generally increased to 85-90Ω / sq.

[0005] Currently, the square resistance of typical commercial solar cells is 55-65Ω / sq (ohms per square). Under the premise of good ohmic contact, higher square resistance means better blue-violet light response, lower surface recombination velocity (SRV), lower reverse saturation current (Jo) and higher short-circuit current (Isc).

[0006] Taking phosphorus source diffusion as an example, the existing conventional diffusion process is to place the silicon wafer into a diffusion furnace, and then introduce the phosphorus source into the diffusion furnace for deposition and diffusion on the surface of the silicon wafer. After the deposition is completed, the introduction of the phosphorus source is stopped, and oxygen is introduced into the diffusion furnace. The oxygen and the phosphorus source are oxidized into phosphorus pentoxide (P2O5) at high temperature. The phosphorus pentoxide deposited on the surface of the silicon wafer reacts with the silicon wafer to generate free phosphorus atoms and silicon dioxide, and then the phosphorus atoms diffuse into the interior of the silicon wafer.

[0007] With the development of high-efficiency crystalline silicon cell technology, the market's requirements for cell conversion efficiency continue to increase, and with the continuous innovation of process technology, N-type cell technology has emerged. N-type cells have the advantages of high conversion efficiency, anti-attenuation, low temperature coefficient, and high bifaciality, which are conducive to improving photovoltaic power generation gain and reducing power generation costs.

[0008] After nearly three years of development, the current mass production efficiency of N-type batteries has reached 26.4%, and the theoretical limit efficiency of TOPCon is 28.7%. Efficiency improvement is still a key difficulty. Before the arrival of a new generation of technology, the mass production efficiency will be gradually improved through continuous optimization of production line processes.

[0009] CN104269459B discloses a decompression diffusion process, which includes a constant temperature decompression process, a pre-oxidation process, a temperature increase process, a deep diffusion process, a phosphorus advancement process, a post-oxidation treatment, and a temperature reduction and pressure increase process. Compared with the normal pressure diffusion process, the decompression diffusion process of the present invention introduces the pressure variable in the diffusion process, reduces the pressure in the diffusion furnace tube, and adjusts the temperature, time, and gas flow rate to make the diffusion block resistance more uniform, and the prepared battery cell has a higher photoelectric conversion efficiency, while increasing the output per unit time of the equipment and saving the amount of diffusion phosphorus source.

[0010] CN112466985A discloses a low-pressure diffusion process for improving the uniformity of diffusion square resistance single wafer, which is prepared by a tubular low-pressure diffusion oxidation furnace, including the following steps: S1, low-temperature and normal pressure boat entry: S2, vacuuming: S3, two alternating low-temperature and low-pressure nitrogen filling oxidation: S4, three times of pushing the junction: S5, low-temperature and low-pressure oxidation: S6, nitrogen filling cooling and pressure raising: S7, boat exit. This process improves the uniformity of diffusion square resistance single wafer, makes the growth of pn junction in silicon wafer uniform, improves the effect of oxidation impurity absorption, reduces the number of recombination centers of minority carriers, improves the life of minority carriers, and achieves the effect of improving the efficiency of battery cells.

[0011] The current efficiency improvement has reached a technical bottleneck. The surface concentration of the current production line process is high, the surface recombination is serious, and the mass production efficiency is low. Therefore, a low surface concentration diffusion process for N-type batteries is now provided. Summary of the invention

[0012] In view of the deficiencies in the prior art, the present invention provides a low surface concentration diffusion process for N-type batteries. A quartz boat carrier is loaded with a texturized silicon wafer, which is then sent into a quartz furnace tube. The furnace tube is evacuated by a membrane pump to maintain a low pressure state of the furnace tube. The furnace tube is heated. After reaching the corresponding temperature conditions, a certain amount of N2, O2 and Bcl3 gas is introduced into the furnace tube. Under the conditions of high temperature and low pressure, the gas reacts with the silicon wafer to achieve the purpose of deposition and diffusion. The present invention mainly reduces the amount of B atoms deposited on the surface of the silicon wafer and reduces carrier recombination by reducing the total gas flow of the special gas Bcl3 introduced into the furnace tube, thereby achieving the purpose of improving efficiency. The deficiencies in the prior art are overcome, and the problems of high surface concentration, serious surface recombination and low mass production efficiency in the current production line process are solved.

[0013] In order to achieve the above object, the present invention adopts the following technical solutions:

[0014] A low surface concentration diffusion process for an N-type battery comprises the following steps:

[0015] (1): using a corrosive solution to simultaneously corrode the light-receiving surface and the backlight surface of the silicon wafer to remove the damaged layer on the light-receiving surface and the backlight surface of the silicon wafer;

[0016] (2): using a corrosive solution to corrode the light-receiving surface of the silicon wafer after the damaged layer is removed, so that the light-receiving surface forms a velvet surface;

[0017] (3): Clean and dry the silicon wafer after texturing;

[0018] (4): Load the textured silicon wafer into the quartz boat carrier and then send it into the quartz furnace tube;

[0019] (5): Use a diaphragm pump to evacuate the furnace tube to maintain a low pressure state;

[0020] (6): The furnace tube is heated, and after reaching the corresponding temperature conditions, a certain amount of N2, O2 and Bcl3 gas is introduced into the furnace tube;

[0021] (7): Under high temperature and low pressure conditions, the gas and silicon wafer react to achieve the purpose of deposition and diffusion.

[0022] Preferably, the heating temperature in step (6) is 650°C-750°C.

[0023] Preferably, the reaction time of step (7) is 5h-8h.

[0024] Preferably, the flow rate of N2 is 2000sccm-4000sccm.

[0025] Preferably, the flow rate of O2 is 300sccm-500sccm.

[0026] Preferably, the flow rate of Bcl3 is 100sccm-200sccm.

[0027] Preferably, the silicon wafer is a P-type boron-doped single crystal silicon wafer.

[0028] The beneficial effects of the present invention are:

[0029] The texturized silicon wafers are loaded into a quartz boat carrier and then sent into a quartz furnace tube. The furnace tube is evacuated by a membrane pump to maintain a low pressure state. The furnace tube is heated. After reaching the corresponding temperature conditions, a certain amount of N2, O2 and Bcl3 gases are introduced into the furnace tube. Under the conditions of high temperature and low pressure, the gas reacts with the silicon wafer to achieve the purpose of deposition and diffusion. The present invention mainly reduces the amount of B atoms deposited on the surface of the silicon wafer and reduces carrier recombination by reducing the total gas flow of the special gas Bcl3 introduced into the furnace tube, thereby achieving the purpose of improving efficiency. DETAILED DESCRIPTION

[0030] The technical solutions in the embodiments of the present invention are described clearly and completely below. Obviously, the described embodiments are only part of the embodiments of the present invention, rather than all the embodiments.

[0031] Embodiment, a low surface concentration diffusion process for an N-type battery, comprising the following steps:

[0032] (1): using a corrosive solution to simultaneously corrode the light-receiving surface and the backlight surface of the silicon wafer to remove the damaged layer on the light-receiving surface and the backlight surface of the silicon wafer;

[0033] (2): using a corrosive solution to corrode the light-receiving surface of the silicon wafer after the damaged layer is removed, so that the light-receiving surface forms a velvet surface;

[0034] (3): Clean and dry the silicon wafer after texturing;

[0035] (4): Load the textured silicon wafer into the quartz boat carrier and then send it into the quartz furnace tube;

[0036] (5): Use a diaphragm pump to evacuate the furnace tube to maintain a low pressure state;

[0037] (6): Heat the furnace tube to 650°C, introduce N2 into the furnace at a flow rate of 4000sccm, introduce O2 into the furnace at a flow rate of 450sccm, and introduce Bcl3 into the furnace at a flow rate of 165sccm.

[0038] (7): At 650°C and 220 mbar, the gas and silicon wafer react for 5 hours to achieve deposition and diffusion.

[0039] Comparative Example: A low surface concentration diffusion process for an N-type battery includes the following steps:

[0040] (1): using a corrosive solution to simultaneously corrode the light-receiving surface and the backlight surface of the silicon wafer to remove the damaged layer on the light-receiving surface and the backlight surface of the silicon wafer;

[0041] (2): using a corrosive solution to corrode the light-receiving surface of the silicon wafer after the damaged layer is removed, so that the light-receiving surface forms a velvet surface;

[0042] (3): Clean and dry the silicon wafer after texturing;

[0043] (4): Load the textured silicon wafer into the quartz boat carrier and then send it into the quartz furnace tube;

[0044] (5): Use a diaphragm pump to evacuate the furnace tube to maintain a low pressure state;

[0045] (6): The furnace tube was heated to 650°C, N2 was introduced into the furnace at a flow rate of 4000 sccm, O2 was introduced into the furnace at a flow rate of 450 sccm, and Bcl3 was introduced into the furnace at a flow rate of 145 sccm.

[0046] (7): Under the conditions of 650°C and 200 mbar, the gas and silicon wafer react for 5 hours to achieve the purpose of deposition and diffusion.

[0047] Currently, the verification efficiency has increased by more than 0.05%:

[0048] category Qty Eta Uoc Isc FF Rs R Irev2 Example 1108 26.449％ 0.7377 15.834 86.47 0.0006 2900 0.0413 Comparative Example 1502 26.379％ 0.7370 15.820 86.39 0.0006 2935 0.0420

[0049] step N2 Doorn2 O2 Bcl3 pressure Deposition 1 4000 1000 450 165→145 220→200 Deposition 2 4000 1000 450 165→145 220→200 Deposition 3 4000 1000 450 165→145 220→200

[0050] In the process formula, when passing the boron source step, the set amount of the boron source in each step is reduced respectively, and the pressure in the furnace tube is reduced at the same time, the excess source is pumped away, and the surface concentration is reduced.

[0051] This process is mainly to reduce the source flow rate in the deposition step, with a single-step flow rate reduction of 20, while reducing the furnace tube pressure to achieve the purpose of reducing the surface concentration.

[0052] The above description is only a preferred specific implementation manner of the present invention, but the protection scope of the present invention is not limited thereto. Any technician familiar with the technical field can make equivalent replacements or changes according to the technical scheme and inventive concept of the present invention within the technical scope disclosed by the present invention, which should be covered by the protection scope of the present invention.

Claims

1. A low surface concentration diffusion process for N-type batteries, characterized in that: The steps include: (1): using a corrosive solution to simultaneously corrode the light-receiving surface and the backlight surface of the silicon wafer to remove the damaged layer on the light-receiving surface and the backlight surface of the silicon wafer; (2): using a corrosive solution to corrode the light-receiving surface of the silicon wafer after the damaged layer is removed, so that the light-receiving surface forms a velvet surface; (3): Clean and dry the silicon wafer after texturing; (4): Load the textured silicon wafer into the quartz boat carrier and then send it into the quartz furnace tube; (5): Use a diaphragm pump to evacuate the furnace tube to maintain a low pressure state; (6): The furnace tube is heated, and after reaching the corresponding temperature conditions, a certain amount of N2, O2 and Bcl3 gas is introduced into the furnace tube; (7): Under high temperature and low pressure conditions, the gas and silicon wafer react to achieve the purpose of deposition and diffusion.

2. The low surface concentration diffusion process for N-type battery according to claim 1, characterized in that: The heating temperature of step (6) is 650°C-750°C.

3. The low surface concentration diffusion process for N-type battery according to claim 1, characterized in that: The reaction time of step (7) is 5h-8h.

4. The low surface concentration diffusion process for N-type battery according to claim 1, characterized in that: The flow rate of N2 is 2000sccm-4000sccm.

5. The low surface concentration diffusion process for N-type battery according to claim 1, characterized in that: The flow rate of O2 is 300sccm-500sccm.

6. The low surface concentration diffusion process for N-type battery according to claim 1, characterized in that: The flow rate of Bcl3 is 100sccm-200sccm.

7. The low surface concentration diffusion process for N-type battery according to claim 1, characterized in that: The silicon wafer is a P-type boron-doped single crystal silicon wafer.