Display device

Abstract

A display device is provided. The display device includes a light emitting element and a first transistor connected between a driving voltage line and the light emitting element, the first transistor including a first gate electrode and a second gate electrode facing each other and an active layer between the first gate electrode and the second gate electrode. The display device further includes a first data line connected to the first gate electrode of the first transistor, a second data line connected to the second gate electrode of the first transistor, and a data driver connected to the first data line and the second data line. The data driver applies a first data voltage to the first data line and applies a second data voltage having a different amplitude from the first data voltage to the second data line. A magnitude of the second data voltage varies according to a magnitude of the first data voltage.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2023-0123978 filed in the Korean Intellectual Property Office on September 18, 2023, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present disclosure relates to a display device having an extended operating range and a method for driving the display device. Background Art

[0004] Organic light emitting diode displays have self-luminous properties and, unlike liquid crystal displays, may not require a separate light source, thus enabling reductions in thickness and weight. In addition, since organic light emitting display devices exhibit high quality characteristics such as low power consumption, high brightness, and fast response speed, they have attracted attention as next-generation display devices for televisions, monitors, and portable electronic devices.

[0005] A head mounted display (HMD) is an image display device that is worn on a user's head in the form of glasses or a helmet to form a focus at a close distance in front of the user's eyes. The head mounted display can realize virtual reality (VR) or augmented reality (AR).

[0006] The head-mounted display can use a lens to magnify the image displayed on the small display device, and / or can display the magnified image. Therefore, the display device applied as a head-mounted display needs to provide a high-resolution image, for example, an image with a resolution of 3000PPI (pixels per inch) or higher. To this end, a silicon-based organic light-emitting diode (OLEDoS), which is a high-resolution small organic light-emitting display device, can be used as a display device applied as a head-mounted display. OLEDoS is an image display device in which an organic light-emitting diode (OLED) is arranged on a semiconductor wafer substrate on which a complementary metal oxide semiconductor (CMOS) is arranged.

[0007] It is to be understood that this background technology section is intended to provide, in part, a useful background for understanding the technology. However, this technical background section may also include ideas, concepts or understandings of parts that were not known or understood by a person skilled in the relevant art before the corresponding effective filing date of the subject matter disclosed herein. Summary of the invention

[0008] Aspects of the present disclosure relate to a display device having an extended operating range and a method for driving the display device.

[0009] According to an embodiment of the present disclosure, a display device may include: a light emitting element; a first transistor connected between a driving voltage line and the light emitting element, the first transistor including: a first gate electrode and a second gate electrode facing each other, and an active layer between the first gate electrode and the second gate electrode; the display device may also include: a first data line connected to the first gate electrode of the first transistor; a second data line connected to the second gate electrode of the first transistor; and a data driver connected to the first data line and the second data line. The data driver may apply a first data voltage to the first data line and apply a second data voltage having a different amplitude from the first data voltage to the second data line, and the amplitude of the second data voltage may be changed according to the amplitude of the first data voltage.

[0010] In an embodiment, the magnitude of the second data voltage may be changed according to the magnitude of the first data voltage such that a change amount of the magnitude of the first data voltage is inversely proportional to a change amount of the magnitude of the second data voltage.

[0011] In an embodiment, when the first data voltage has a value included in a range from a preset lower limit value to an upper limit value, the amplitude of the second data voltage can be changed according to the amplitude of the first data voltage, so that the change in the amplitude of the first data voltage is inversely proportional to the change in the amplitude of the second data voltage, and when the first data voltage is less than the lower limit value, the amplitude of the second data voltage can be maintained at a value corresponding to the first data voltage having the lower limit value, and when the first data voltage is greater than the upper limit value, the amplitude of the second data voltage can be maintained at a value corresponding to the first data voltage having the upper limit value.

[0012] In an embodiment, the magnitude of the second data voltage may be changed according to the magnitude of the first data voltage such that the first data voltage and the second data voltage have the same magnitude but opposite polarities.

[0013] In an implementation, the data driver may simultaneously apply the first data voltage and the second data voltage to the first data line and the second data line, respectively.

[0014] In an implementation, the display device may further include: a second transistor connected between the first data line and the first gate electrode of the first transistor.

[0015] In an implementation, the display device may further include: a third transistor connected between the second data line and the second gate electrode of the first transistor.

[0016] In an implementation, the on-time and the off-time of the second transistor may be the same as the on-time and the off-time of the third transistor.

[0017] In an embodiment, a first data voltage from the data driver may be applied to the first data line at a turn-on time of the second transistor, and a second data voltage from the data driver may be applied to the second data line at a turn-on time of the third transistor.

[0018] In an implementation, the display device may further include a first capacitor connected between the first gate electrode of the first transistor and the driving voltage line.

[0019] In an implementation, the display device may further include a second capacitor connected between the second gate electrode of the first transistor and the driving voltage line.

[0020] In an embodiment, the display device may further include a capacitor between the first gate electrode of the first transistor and the second gate electrode of the first transistor.

[0021] According to an embodiment of the present disclosure, a display device may include: a light emitting element; a transistor connected between a driving voltage line and the light emitting element, the transistor including: a first gate electrode and a second gate electrode facing each other, and an active layer between the first gate electrode and the second gate electrode. The display device may also include: a first data line connected to the first gate electrode of the transistor; a second data line connected to the second gate electrode of the transistor; a data driver connected to the first data line; and a conversion circuit connected between the first data line and the second data line. The data driver may apply a first data voltage to the first data line, the conversion circuit may generate a second data voltage according to the first data voltage, and the generated second data voltage may be applied to the second data line, the first data voltage and the second data voltage may have different amplitudes from each other, and the amplitude of the second data voltage may be changed according to the amplitude of the first data voltage.

[0022] In an embodiment, the magnitude of the second data voltage may be changed according to the magnitude of the first data voltage such that a change amount of the magnitude of the first data voltage is inversely proportional to a change amount of the magnitude of the second data voltage.

[0023] In an embodiment, when the first data voltage has a value included in a range from a preset lower limit value to an upper limit value, the amplitude of the second data voltage can be changed according to the amplitude of the first data voltage, so that the change in the amplitude of the first data voltage is inversely proportional to the change in the amplitude of the second data voltage, and when the first data voltage is less than the lower limit value, the amplitude of the second data voltage can be maintained at a value corresponding to the first data voltage having the lower limit value, and when the first data voltage is greater than the upper limit value, the amplitude of the second data voltage can be maintained at a value corresponding to the first data voltage having the upper limit value.

[0024] In an embodiment, the magnitude of the second data voltage may be changed according to the magnitude of the first data voltage such that the first data voltage and the second data voltage have the same magnitude but opposite polarities.

[0025] According to an embodiment of the present disclosure, a display device may include: a light emitting element; a transistor connected between a driving voltage line and the light emitting element, the transistor including: a first gate electrode and a second gate electrode facing each other, and an active layer between the first gate electrode and the second gate electrode. The display device may also include: a data line connected to the first gate electrode of the transistor; a data driver connected to the data line; and a voltage conversion circuit connected between the first gate electrode of the transistor and the second gate electrode of the transistor. The data driver may apply a first data voltage to the data line, the voltage conversion circuit may generate a second data voltage based on the first data voltage applied to the first gate electrode through the data line, and may apply the generated second data voltage to the second gate electrode, the first data voltage and the second data voltage may have different amplitudes, and the amplitude of the second data voltage may change according to the amplitude of the first data voltage.

[0026] In an embodiment, the magnitude of the second data voltage may be changed according to the magnitude of the first data voltage such that a change amount of the magnitude of the first data voltage is inversely proportional to a change amount of the magnitude of the second data voltage.

[0027] In an embodiment, when the first data voltage has a value included in a range from a preset lower limit value to an upper limit value, the amplitude of the second data voltage can be changed according to the amplitude of the first data voltage, so that the change in the amplitude of the first data voltage is inversely proportional to the change in the amplitude of the second data voltage, and when the first data voltage is less than the lower limit value, the amplitude of the second data voltage can be maintained at a value corresponding to the first data voltage having the lower limit value, and when the first data voltage is greater than the upper limit value, the amplitude of the second data voltage can be maintained at a value corresponding to the first data voltage having the upper limit value.

[0028] In an embodiment, the magnitude of the second data voltage may be changed according to the magnitude of the first data voltage such that the first data voltage and the second data voltage have the same magnitude but opposite polarities.

[0029] According to an embodiment of the present disclosure, a method for driving a display device may include preparing a transistor, the transistor including a first gate electrode and a second gate electrode connected between a driving voltage line and a light-emitting element and facing each other, and an active layer between the first gate electrode and the second gate electrode. The method may also include: applying a first data voltage to the first gate electrode; and applying a second data voltage having a different amplitude from the first data voltage to the second gate electrode. The amplitude of the second data voltage may be changed according to the amplitude of the first data voltage.

[0030] In an embodiment, the magnitude of the second data voltage may be changed according to the magnitude of the first data voltage such that a change amount of the magnitude of the first data voltage is inversely proportional to a change amount of the magnitude of the second data voltage.

[0031] In an embodiment, when the first data voltage has a value included in a range from a preset lower limit value to an upper limit value, the amplitude of the second data voltage can be changed according to the amplitude of the first data voltage, so that the change in the amplitude of the first data voltage is inversely proportional to the change in the amplitude of the second data voltage, and when the first data voltage is less than the lower limit value, the amplitude of the second data voltage can be maintained at a value corresponding to the first data voltage having the lower limit value, and when the first data voltage is greater than the upper limit value, the amplitude of the second data voltage can be maintained at a value corresponding to the first data voltage having the upper limit value.

[0032] In an embodiment, the magnitude of the second data voltage may be changed according to the magnitude of the first data voltage such that the first data voltage and the second data voltage have the same magnitude but opposite polarities.

[0033] According to the display device of the present disclosure, the operating range of the display device can be expanded, and more detailed grayscale expression can be performed, thereby improving the image quality of the display device.

[0034] The effects of the present disclosure are not limited to the above-described effects, and other effects not described herein will become apparent to those skilled in the art through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] The above and other aspects and features of the present disclosure will become more apparent by describing in detail embodiments thereof with reference to the accompanying drawings, in which:

[0036] Figure 1 is a schematic perspective view showing a display device according to an embodiment;

[0037] Figure 2 is a schematic cross-sectional view illustrating a display device according to an embodiment;

[0038] Figure 3 is a schematic plan view illustrating a display unit of a display device according to an embodiment;

[0039] Figure 4 is a schematic block diagram illustrating a display panel and a display driver according to an embodiment;

[0040] Figure 5 is a schematic circuit diagram of one pixel of a display device and a schematic diagram of a data driver according to an embodiment;

[0041] Figure 6 Yes Figure 5 A schematic cross-sectional view of a display device having a first transistor;

[0042] Figure 7 is a schematic circuit diagram of one pixel of a display device according to an embodiment and a schematic diagram illustrating a data driver and a voltage conversion circuit;

[0043] Figure 8 is a schematic circuit diagram of one pixel of a display device according to an embodiment and a schematic diagram illustrating a data driver and a voltage conversion circuit;

[0044] Fig. 9 is a schematic circuit diagram of one pixel of a display device according to an embodiment and a schematic diagram illustrating a data driver;

[0045] Fig.10 is a schematic circuit diagram of one pixel of a display device according to an embodiment and a schematic diagram illustrating a data driver; and

[0046] Fig.11 It is a schematic diagram for explaining the effect of the display device according to the embodiment. DETAILED DESCRIPTION

[0047] The present disclosure will now be described more fully below with reference to the accompanying drawings in which embodiments are shown. However, the present disclosure may be embodied in different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that the present disclosure will be exhaustive and comprehensive and will fully convey the scope of the present disclosure to those skilled in the art.

[0048] As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0049] The terms “comprises,” “comprising,” “includes,” “including,” “has,” “have,” “having,” and variations thereof, when used in the present specification, specify the presence of stated features, integers, steps, operations, elements, components, and / or groups thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0050] In the specification and claims, for the purpose of its meaning and interpretation, the term "and / or" is intended to include any combination of the terms "and" and "or". For example, "A and / or B" may be understood to mean "A, B, or A and B". The terms "and" and "or" may be used in the sense of a conjunction or an antonymous conjunction and may be understood to be equivalent to "and / or".

[0051] In the specification and claims, for the purpose of its meaning and interpretation, the phrase "at least one of" is intended to include the meaning of "at least one selected from the group of". For example, "at least one of A and B" can be understood to mean "A, B, or A and B".

[0052] It will also be understood that when a layer is referred to as being "on" another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may also be present. Throughout the specification, like reference numerals refer to like components. In the drawings, the thickness of layers and regions may be exaggerated for clarity.

[0053] Although the terms "first", "second", etc. can be used in this article to describe various elements, these elements should not be limited by these terms. These terms can be used to distinguish an element from another element. Therefore, the first element discussed below can be referred to as the second element, without departing from the teaching of one or more embodiments. The description of an element such as a "first" element may not require or imply the existence of a second element or other elements. The terms "first", "second", etc. can also be used herein to distinguish between elements of different categories or sets. For the sake of simplicity, the terms "first", "second", etc. can respectively represent "first category (or first set)", "second category (or second set)", etc.

[0054] The features of the various embodiments of the present disclosure may be combined in part or in whole. As will be clearly understood by those skilled in the art, it is technically possible to perform various interactions and operations. The various embodiments can be practiced individually or in combination.

[0055] The terms "facing" and "facing" mean that a first element may be directly or indirectly opposite to a second element. In the case where a third element is between the first and second elements, the first and second elements may be understood to be indirectly opposite to each other, although still facing each other.

[0056] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as those commonly understood by those skilled in the art to which the present disclosure belongs. It will also be understood that terms (such as those defined in commonly used dictionaries) should be interpreted as having a meaning consistent with their contextual meaning in the relevant art, and will not be interpreted in an idealized or overly formal sense unless explicitly so defined herein.

[0057] Figure 1 is a schematic perspective view showing a display device 10 according to an embodiment.

[0058] refer to Figure 1 The display device 10 can be applied to portable electronic devices such as mobile phones, smart phones, tablet personal computers, mobile communication terminals, electronic notepads, electronic books, portable multimedia players (PMPs), navigation systems, ultra mobile personal computers (UMPCs), etc. For example, the display device 10 can be used as a display unit of a television, a laptop computer, a monitor, a billboard, or an Internet of Things (IoT) device. As another example, the display device 10 can be applied to wearable devices such as smart watches, watch phones, glasses-type displays, or helmet-mounted displays (HMDs).

[0059] The display device 10 may have a planar shape similar to a quadrilateral shape. For example, the display device 10 may have a planar shape similar to a quadrilateral shape having short sides in the first direction DR1 and long sides in the second direction DR2. The corner at which the short sides in the first direction DR1 and the long sides in the second direction DR2 meet may be a right angle or a rounded corner having a predetermined or selected curvature. The planar shape of the display device 10 is not limited to a quadrilateral shape, and may be formed in a shape similar to another polygonal shape, a circular shape, or an elliptical shape.

[0060] The display device 10 may include a display panel 100 , a display driver 200 , a circuit board 300 , a touch driver 400 , and a power supply unit 500 .

[0061] The display panel 100 may include a main area MA and a sub area SBA.

[0062] The main area MA may include a display area DA including pixels displaying an image and a non-display area NDA surrounding the display area DA. The display area DA may emit light from an emission area or an opening area. For example, the display panel 100 may include a pixel circuit including a switching element, a pixel defining layer defining an emission area or an opening area, and a light emitting element ED (see Figure 5 ). The light emitting element ED may be a self-luminous element.

[0063] For example, the light emitting element ED may include at least one of an organic light emitting diode (LED) including an organic light emitting layer, a quantum dot LED including a quantum dot light emitting layer, an inorganic LED including an inorganic semiconductor, and a micro LED, but is not limited thereto.

[0064] The non-display area NDA may be an area outside the display area DA. The non-display area NDA may be defined as an edge area of ​​the main area MA of the display panel 100. The non-display area NDA may include a gate driver (not shown) supplying a gate signal to a gate line and a fan-out line (not shown) connecting the display driver 200 to the display area DA.

[0065] The sub-area SBA may extend from one side of the main area MA. The sub-area SBA may include a flexible material that can be bent, folded or curled. For example, when the sub-area SBA is bent, the sub-area SBA may overlap with the main area MA in the thickness direction (e.g., the third direction DR3). The sub-area SBA may include a display driver 200 and a pad portion connected to the circuit board 300. Alternatively, the sub-area SBA may be omitted, and the display driver 200 and the pad portion may be arranged in the non-display area NDA.

[0066] The display driver 200 may output a signal and a voltage for driving the display panel 100. The display driver 200 may supply a data voltage to a data line. The display driver 200 may supply a power voltage to a power line, and may supply a gate control signal to a gate driver. The display driver 200 may be formed as an integrated circuit (IC) and may be mounted on the display panel 100 by a chip on glass (COG) method, a chip on plastic (COP) method, or an ultrasonic welding method. For example, the display driver 200 may be arranged in a sub-area SBA, and may overlap with the main area MA in a thickness direction (third direction DR3) by bending of the sub-area SBA. As another example, the display driver 200 may be mounted on a circuit board 300.

[0067] The circuit board 300 may be attached to the pad portion of the display panel 100 by using an anisotropic conductive film (ACF). Leads of the circuit board 300 may be electrically connected to the pad portion of the display panel 100. The circuit board 300 may be a flexible printed circuit board, a printed circuit board, or a flexible film such as a chip on film.

[0068] The touch driver 400 may be mounted on the circuit board 300. The touch driver 400 may be electrically connected to the touch sensing unit of the display panel 100. The touch driver 400 may supply a touch drive signal to the touch electrode of the touch sensing unit, and may sense the amount of change in capacitance between the touch electrodes. For example, the touch drive signal may be a pulse signal having a predetermined or selected frequency. The touch driver 400 may calculate whether an input is made and the input coordinates based on the amount of change in capacitance between the touch electrodes. The touch driver 400 may be formed by an integrated circuit (IC).

[0069] The power supply unit 500 may be disposed on the circuit board 300 to apply a supply voltage to the display driver 200 and the display panel 100. The power supply unit 500 may generate a driving voltage to provide the driving voltage to the driving voltage line VDL, may generate an initialization voltage (e.g., a first initialization voltage and a second initialization voltage) to provide the initialization voltage to the initialization voltage line (e.g., a first initialization voltage line VIL1 and a second initialization voltage line VIL2), and may generate a common voltage to provide the common voltage to a common electrode common to a plurality of light emitting elements ED of a plurality of pixels. For example, the driving voltage may be a high level voltage for driving the light emitting element ED, and the common voltage may be a low level voltage for driving the light emitting element ED.

[0070] Figure 2 is a schematic cross-sectional view illustrating a display device 10 according to an embodiment.

[0071] refer to Figure 2 The display panel 100 may include a display unit DU, a touch sensing unit TSU, and a color filter layer CFL. The display unit DU may include a substrate SUB, a thin film transistor layer TFTL, a light emitting element layer EMTL, and an encapsulation layer ENC.

[0072] The substrate SUB may be a base substrate or a base member. The substrate SUB may be a flexible substrate that can be bent, folded, or curled. For example, the substrate SUB may include a polymer resin such as polyimide (PI), but is not limited thereto. As another example, the substrate SUB may include a glass material or a metal material.

[0073] The thin film transistor layer TFTL may be arranged on the substrate SUB. The thin film transistor layer TFTL may include a thin film transistor constituting a pixel circuit of a pixel. The thin film transistor layer TFTL may also include a gate line, a data line, a power line, a gate control line, a fan-out line connecting the display driver 200 to the data line, and a lead connecting the display driver 200 to the pad portion. Each of the plurality of thin film transistors may include a semiconductor region, a source electrode, a drain electrode, and a gate electrode. For example, in the case where a gate driver is formed on one side of the non-display area NDA of the display panel 100, the gate driver may include a thin film transistor.

[0074] The thin film transistor layer TFTL may be arranged in the display area DA, the non-display area NDA, and the sub-area SBA. The thin film transistor, gate line, data line, and power line of each of the plurality of pixels of the thin film transistor layer TFTL may be arranged in the display area DA. The gate control line and the fan-out line of the thin film transistor layer TFTL may be arranged in the non-display area NDA. The lead line of the thin film transistor layer TFTL may be arranged in the sub-area SBA.

[0075] The light emitting element layer EMTL may be disposed on the thin film transistor layer TFTL. The light emitting element layer EMTL may include a light emitting element ED in which a pixel electrode, a light emitting layer, and a common electrode are sequentially stacked to emit light, and a pixel defining layer defining a pixel. The light emitting element ED of the light emitting element layer EMTL may be disposed in the display area DA.

[0076] For example, the light-emitting layer may be an organic light-emitting layer including an organic material. The light-emitting layer may include a hole transport layer, an organic light-emitting layer, and an electron transport layer. In the case where the pixel electrode receives a predetermined or selected voltage through the thin film transistor of the thin film transistor layer TFTL and the common electrode receives a cathode voltage, holes and electrons may be transferred to the organic light-emitting layer through the hole transport layer and the electron transport layer, respectively, and may be combined with each other to emit light in the organic light-emitting layer. For example, the pixel electrode may be an anode electrode, and the common electrode may be a cathode electrode, but the present disclosure is not limited thereto.

[0077] As another example, the light emitting element ED may include a quantum dot light emitting diode including a quantum dot light emitting layer, an inorganic light emitting diode including an inorganic semiconductor, or a micro light emitting diode.

[0078] The encapsulation layer ENC may cover the top surface and the side surface of the light emitting element layer EMTL and may protect the light emitting element layer EMTL. The encapsulation layer ENC may include at least one inorganic layer and at least one organic layer for encapsulating the light emitting element layer EMTL.

[0079] The touch sensing unit TSU may be disposed on the encapsulation layer ENC. The touch sensing unit TSU may include a touch electrode for capacitively sensing a user's touch and a touch line connecting the touch electrode to the touch driver 400. For example, the touch sensing unit TSU may sense the user's touch by using a mutual capacitance method or a self capacitance method.

[0080] As another example, the touch sensing unit TSU may be disposed on a separate substrate SUB placed on the display unit DU. The substrate SUB supporting the touch sensing unit TSU may be a base member encapsulating the display unit DU.

[0081] The touch electrodes of the touch sensing unit TSU may be arranged in a touch sensor area overlapping the display area DA. The touch lines of the touch sensing unit TSU may be arranged in a touch peripheral area overlapping the non-display area NDA.

[0082] The color filter layer CFL may be arranged on the touch sensing unit TSU. The color filter layer CFL may include a plurality of color filters corresponding to the plurality of emission regions, respectively. Each of the plurality of color filters may selectively transmit light of a specific wavelength, and may block or absorb light of a different wavelength. The color filter layer CFL may absorb a portion of light from outside the display device 10 to reduce reflected light caused by external light. Therefore, the color filter layer CFL may prevent color distortion caused by reflection of external light.

[0083] Since the color filter layer CFL is directly disposed on the touch sensing unit TSU, the display device 10 may not require a separate substrate SUB for the color filter layer CFL. Therefore, the thickness of the display device 10 may be relatively reduced.

[0084] The sub-area SBA of the display panel 100 may extend from one side of the main area MA. The sub-area SBA may include a flexible material that can be bent, folded, or curled. For example, when the sub-area SBA is bent, the sub-area SBA may overlap the main area MA in the thickness direction (third direction DR3). The sub-area SBA may include a display driver 200 and a pad portion electrically connected to the circuit board 300.

[0085] Figure 3 is a schematic plan view illustrating a display unit DU of the display device 10 according to the embodiment. Figure 4 is a schematic block diagram illustrating a display panel 100 and a display driver 200 according to an embodiment.

[0086] refer to Figure 3 and Figure 4 , the display panel 100 may include a display area DA and a non-display area NDA.

[0087] The display area DA may include pixels PX and driving voltage lines VDL and common voltage lines VSL (see FIG. Figure 5 ), gate lines GL and data lines DL.

[0088] Each of the plurality of pixels PX may be connected to a gate line GL, a data line DL, a driving voltage line VDL, and a common voltage line VSL. Each of the plurality of pixels PX may include at least one transistor, a light emitting element ED, and a capacitor.

[0089] Each of the plurality of gate lines GL may extend in a first direction DR1 and may be spaced apart from each other in a second direction DR2 intersecting the first direction DR1. The gate lines GL may be arranged along the second direction DR2. The gate lines GL may sequentially supply gate signals to the pixels PX.

[0090] The data lines DL may extend in the second direction DR2 and may be spaced apart from each other in the first direction DR1. The data lines DL may be arranged along the first direction DR1. The data lines DL may supply a data voltage to the pixel PX. The data voltage may determine the brightness of each of the plurality of pixels PX. According to an embodiment, one pixel PX may be connected to two different data lines DL. For example, one pixel PX may be connected to the first data line DL1 (see Figure 5 ) and the second data line DL2 (see Figure 5 ).

[0091] The driving voltage lines VDL may extend in the second direction DR2 and may be spaced apart from each other in the first direction DR1. The driving voltage lines VDL may be arranged along the first direction DR1. The driving voltage lines VDL may supply a driving voltage to the pixel PX. The driving voltage may be a high potential voltage for driving the light emitting element ED of the pixel PX.

[0092] The non-display area NDA may surround the display area DA. The non-display area NDA may include a gate driver 610, a fan-out line FL, and a gate control line GSL.

[0093] The fan-out line FL may extend from the display driver 200 to the display area DA. The fan-out line FL may supply a data voltage received from the display driver 200 to the data line DL.

[0094] The gate control line GSL may extend from the display driver 200 to the gate driver 610. The gate control line GSL may supply the gate control signal GCS received from the display driver 200 (eg, the timing controller 210) to the gate driver 610.

[0095] The sub-area SBA may extend from one side of the non-display area NDA. The sub-area SBA may include a display driver 200 and a pad portion DP. The pad portion DP may be closer to one edge of the sub-area SBA than the display driver 200. The pad portion DP may be electrically connected to the circuit board 300 through an anisotropic conductive film ACF.

[0096] The display driver 200 may include a timing controller 210 and a data driver 220 .

[0097] The timing controller 210 may receive the digital video data DATA and the timing signal from the circuit board 300. The timing controller 210 may generate a data control signal DCS for controlling the operation timing of the data driver 220, a gate control signal GCS for controlling the operation timing of the gate driver 610, and an emission control signal for controlling the operation timing of the emission control driver based on the timing signal. The timing controller 210 may supply the gate control signal GCS to the gate driver 610 through the gate control line GSL. The timing controller 210 may supply the digital video data DATA and the data control signal DCS to the data driver 220.

[0098] The data driver 220 may convert the digital video data DATA into an analog data voltage and supply the analog data voltage to the data line DL through the fan-out line FL. The gate signal of the gate driver 610 may select the pixel PX to which the data voltage is supplied, and the selected pixel PX may receive the data voltage through the data line DL.

[0099] The power supply unit 500 may be arranged on the circuit board 300 to supply a power voltage to the display driver 200 and the display panel 100. The power supply unit 500 may generate a driving voltage to supply the driving voltage to the driving voltage line VDL, may generate an initialization voltage to supply the initialization voltage to the initialization voltage line, and may generate a common voltage to supply the common voltage to a common electrode common to a plurality of light emitting elements ED of a plurality of pixels PX. The common voltage may be applied to the common electrode through the common voltage line VSL.

[0100] The gate driver 610 may be arranged at the outer side of the display area DA or at one side of the non-display area NDA. The emission control driver may be arranged at the other outer side of the display area DA or at the other side of the non-display area NDA. However, the present disclosure is not limited thereto. As another example, the gate driver 610 and the emission control driver may be arranged at either one side or the other side of the non-display area NDA.

[0101] The gate driver 610 may include a transistor for generating a gate signal based on the gate control signal GCS. For example, the transistor of the gate driver 610 may be formed on the same layer as the transistor of each of the plurality of pixels PX. The gate driver 610 may supply the gate signal to the gate line GL.

[0102] Figure 5 2 is a schematic circuit diagram of one pixel PX of the display device 10 and a schematic diagram of the data driver 220 according to the embodiment.

[0103] refer to Figure 5 , the pixel PX may be connected to the first gate line GL1, the second gate line GL2, the first data line DL1, and the second data line DL2.

[0104] The pixel PX may include a pixel circuit PC and a light emitting element ED.

[0105] The pixel circuit PC may include a first transistor T1 , a second transistor T2 , a third transistor T3 , and a capacitor Cst.

[0106] The first transistor T1 may include a first gate electrode GE1, a second gate electrode GE2, a source electrode, and a drain electrode. The first transistor T1 may control a source-drain current (hereinafter referred to as a driving current) according to a first data voltage V1 applied to the first gate electrode GE1 and a second data voltage V2 applied to the second gate electrode GE2. The first gate electrode GE1 of the first transistor T1 may be electrically connected to a source electrode of the second transistor T2, the second gate electrode GE2 of the first transistor T1 may be electrically connected to a source electrode of the third transistor T3, the drain electrode of the first transistor T1 may be electrically connected to a driving voltage line VDL, and the source electrode of the first transistor T1 may be connected to a first electrode (or an anode electrode, or a pixel electrode) of the light emitting element ED. The driving voltage line VDL may transmit a driving voltage ELVDD.

[0107] The light emitting element ED may emit light by receiving a driving current. The emission amount or brightness of the light emitting element ED may be proportional to the amplitude of the driving current. The light emitting element ED may include a first electrode, a second electrode, and an organic light emitting layer, and the organic light emitting layer may be between the first electrode and the second electrode. As another example, the light emitting element ED may be an inorganic light emitting element including a first electrode, a second electrode, and an inorganic semiconductor, and the inorganic semiconductor may be between the first electrode and the second electrode. As yet another example, the light emitting element ED may be a quantum dot light emitting element including a first electrode, a second electrode, and a quantum dot light emitting layer, and the quantum dot light emitting layer may be between the first electrode and the second electrode. As yet another example, the light emitting element ED may be a micro light emitting diode. The first electrode of the light emitting element ED may be electrically connected to the source electrode of the first transistor T1. The second electrode of the light emitting element ED may be electrically connected to the common voltage line VSL. The second electrode of the light emitting element ED may receive a common voltage ELVSS (e.g., a low potential voltage) from the common voltage line VSL.

[0108] The second transistor T2 may be turned on by the first gate signal GS1 of the first gate line GL1 to electrically connect the first data line DL1 to the first gate electrode GE1 of the first transistor T1. When the second transistor T2 is turned on in response to the first gate signal GS1, the first data voltage V1 of the first data line DL1 may be supplied to the first gate electrode GE1 of the first transistor T1. The gate electrode of the second transistor T2 may be electrically connected to the first gate line GL1, the drain electrode of the second transistor T2 may be electrically connected to the first data line DL1, and the source electrode of the second transistor T2 may be electrically connected to the first gate electrode GE1 of the first transistor T1.

[0109] The third transistor T3 may be turned on by the second gate signal GS2 of the second gate line GL2 to electrically connect the second data line DL2 to the second gate electrode GE2 of the first transistor T1. When the third transistor T3 is turned on in response to the second gate signal GS2, the second data voltage V2 of the second data line DL2 may be supplied to the second gate electrode GE2 of the first transistor T1. The gate electrode of the third transistor T3 may be electrically connected to the second gate line GL2, the drain electrode of the third transistor T3 may be electrically connected to the second data line DL2, and the source electrode of the third transistor T3 may be electrically connected to the second gate electrode GE2 of the first transistor T1.

[0110] The capacitor Cst may be electrically connected between the first gate electrode GE1 of the first transistor T1 and the driving voltage line VDL. The first electrode of the capacitor Cst may be electrically connected to the first gate electrode GE1 of the first transistor T1, and the second electrode of the capacitor Cst may be electrically connected to the driving voltage line VDL. For example, the capacitor Cst may store the first data voltage V1 supplied from the first data line DL1 through the second transistor T2.

[0111] The first transistor T1, the second transistor T2, and the third transistor T3 may include an oxide-based active layer. The oxide-based active layer may include, for example, indium gallium zinc oxide (IGZO) or indium gallium zinc tin oxide (IGZTO). The transistor including the oxide-based active layer may have a coplanar structure in which the gate electrode is arranged at its upper portion. The transistor including the oxide-based active layer may correspond to an n-type transistor and output the current flowing into the drain electrode to the source electrode based on the gate high voltage applied to the gate electrode.

[0112] Figure 6 Yes Figure 5 Schematic cross-sectional view of a display device 10 showing a first transistor T1.

[0113] like Figure 6 , the display device 10 according to the embodiment may include a substrate SUB, a light blocking layer BML, a buffer layer BF, a thin film transistor layer TFTL, a light emitting element layer EMTL, and an encapsulation layer ENC. The light blocking layer BML, the buffer layer BF, the thin film transistor layer TFTL, the light emitting element layer EMTL, and the encapsulation layer ENC may be sequentially arranged on the substrate SUB along the third direction DR3. Here, the thin film transistor layer TFTL may include the above-described Figure 5 The first transistor T1, the second transistor T2 and the third transistor T3. Figure 6 , the first transistor T1 included in the thin film transistor layer TFTL is shown as an example.

[0114] The substrate SUB may be a rigid substrate or a flexible substrate that can be bent, folded or curled. The substrate SUB may be made of an insulating material such as glass, quartz or a polymer resin. Examples of polymer materials may include polyethersulfone (PES), polyacrylate (PA), polyarylate (PAR), polyetherimide (PEI), polyethylene naphthalate (PEN), polyethylene terephthalate (PET), polyphenylene sulfide (PPS), polyacrylate, polyimide (PI), polycarbonate (PC), cellulose triacetate (CAT), cellulose acetate propionate (CAP) or a combination thereof. The substrate SUB may include a metal material.

[0115] The light-blocking layer BML may be arranged on the substrate SUB. The light-blocking layer BML may be arranged on the substrate SUB to overlap with the active layer ACT to be described later. For example, the light-blocking layer BML may be formed of a metal material such as chromium (Cr) and molybdenum (Mo) or black ink or black dye. In the case where the light-blocking layer BML is made of a metal material, the light-blocking layer BML may receive a constant power supply. Therefore, the light-blocking layer BML may not be electrically floating, and the electrical characteristics of the transistor on the light-blocking layer BML can be stabilized. For example, it is possible to prevent degradation of oxide-type transistors. Incidentally, oxide semiconductors are sensitive to light, and therefore there may be changes in the amount of current, etc. caused by external light. The light-blocking layer BML may include a second gate electrode GE2 of the first transistor T1. In other words, a portion of the light-blocking layer BML may correspond to the second gate electrode GE2 of the first transistor T1.

[0116] The buffer layer BF may be disposed on the light blocking layer BML. The buffer layer BF may be disposed on the entire surface of the substrate SUB including the light blocking layer BML. The buffer layer BF may be a layer for protecting the thin film transistor of the thin film transistor layer TFTL and the light emitting layer EL of the light emitting element layer EMTL from moisture penetrating through the substrate SUB susceptible to moisture. The buffer layer BF may be composed of a plurality of inorganic layers alternately stacked with each other. For example, the buffer layer BF may be composed of a plurality of layers in which one or more inorganic layers of a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, and an aluminum oxide layer are alternately stacked with each other.

[0117] The active layer ACT may be disposed on the buffer layer BF. For example, the active layer ACT may be disposed on the buffer layer BF to overlap with the first gate electrode GE1 of the light blocking layer BML. The active layer ACT may be, for example, an oxide semiconductor. For example, the active layer ACT may be a semiconductor including indium gallium zinc oxide (IGZO) or indium gallium zinc tin oxide (IGZTO). In addition, the active layer ACT may be, for example, crystalline silicon, polycrystalline silicon, or amorphous silicon.

[0118] The gate insulating layer GTI may be arranged on the active layer ACT. For example, the gate insulating layer GTI may overlap with the channel region CH of the active layer ACT. The gate insulating layer GTI may include at least one of tetraethyl orthosilicate (TEOS), silicon nitride (SiNx), and silicon oxide (SiO2). For example, the gate insulating layer GTI may have a double-layer structure in which a silicon nitride layer having a thickness of 40nm and tetraethyl orthosilicate having a thickness of 80nm are sequentially stacked.

[0119] The first gate electrode GE1 may be disposed on the gate insulating layer GTI. The first gate electrode GE1 may be disposed on the gate insulating layer GTI to overlap with the channel region CH of the active layer ACT. The first gate electrode GE1 may be made of aluminum (Al) or titanium (Ti). In addition, the first gate electrode GE1 may have a double-layer or triple-layer structure in which aluminum (Al) and titanium (Ti) are stacked.

[0120] The interlayer insulating layer ITL may be disposed on the first gate electrode GE1. The interlayer insulating layer ITL may be disposed on the entire surface of the substrate SUB including the first gate electrode GE1. The interlayer insulating layer ITL may include an inorganic layer, for example, a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer. The interlayer insulating layer ITL may include an inorganic layer.

[0121] The source connection electrode SCE and the drain connection electrode DCE may be arranged on the interlayer insulating layer ITL. The source connection electrode SCE may be connected to the source electrode SE of the active layer ACT through a first contact hole CT1 penetrating the interlayer insulating layer ITL. The drain connection electrode DCE may be connected to the drain electrode DE of the active layer ACT through a second contact hole CT2 penetrating the interlayer insulating layer ITL. The source connection electrode SCE and the drain connection electrode DCE may be made of the same material as the first gate electrode GE1 described above.

[0122] The passivation layer PAS may be disposed on the source connection electrode SCE and the drain connection electrode DCE. The passivation layer PAS may be disposed on the entire surface of the substrate SUB including the interlayer insulating layer ITL. The passivation layer PAS may be made of the same material as the interlayer insulating layer ITL.

[0123] The planarization layer VA may be disposed on the passivation layer PAS. The planarization layer VA may be disposed on the entire surface of the substrate SUB including the passivation layer PAS. The planarization layer VA may include an organic layer made of acrylic resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin.

[0124] The light emitting element layer EMTL including the pixel electrode PE, the light emitting element ED and the pixel defining layer PDL may be disposed on the planarization layer VA. The pixel electrode PE may be connected to the source connection electrode SCE through the third contact hole CT3 penetrating the planarization layer VA. The pixel electrode PE may be connected to the source electrode SE of the active layer ACT through the source connection electrode SCE.

[0125] The light emitting element ED may include a pixel electrode PE, a light emitting layer EL, and a common electrode CM. The emission area EA refers to a region where the pixel electrode PE, the light emitting layer EL, and the common electrode CM are sequentially stacked and holes from the pixel electrode PE and electrons from the common electrode CM are combined with each other in the light emitting layer EL to emit light. The pixel electrode PE may be an anode electrode of the light emitting element ED, and the common electrode CM may be a cathode electrode of the light emitting element ED.

[0126] In a top emission structure based on the light emitting layer EL emitting light in the direction of the common electrode CM, the pixel electrode PE may be formed as a single layer made of molybdenum (Mo), titanium (Ti), copper (Cu), or aluminum (Al), or may be formed as a stacked structure of aluminum and titanium (Ti / Al / Ti), a stacked structure of aluminum and ITO (ITO / Al / ITO), an APC alloy, and a stacked structure of an APC alloy and ITO (ITO / APC / ITO). The APC alloy is an alloy of silver (Ag), palladium (Pd), and copper (Cu).

[0127] The pixel defining layer PDL is used to define the emission area EA of the pixel PX. To this end, the pixel defining layer PDL may expose a partial area of ​​the pixel electrode PE on the planarization layer VA. The pixel defining layer PDL may cover the edge of the pixel electrode PE. The pixel defining layer PDL may be formed as an organic layer made of acrylic resin, epoxy resin, phenolic resin, polyamide resin or polyimide resin.

[0128] The spacer SPC may be disposed on the pixel defining layer PDL. The spacer SPC may be used to support a mask during a process of manufacturing the light emitting layer EL. The spacer SPC may be formed as an organic layer made of acrylic resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin.

[0129] The light emitting layer EL may be formed on the pixel electrode PE. The light emitting layer EL may include an organic material to emit light of a predetermined or selected color. For example, the light emitting layer EL may include a hole transport layer, an organic material layer, and an electron transport layer. The organic material layer may include a host and a dopant. The organic material layer may include a material that emits a predetermined or selected light, and may be formed of a phosphorescent material or a fluorescent material.

[0130] The pixel PX may include a first pixel emitting light of a first color through a first emission region, a second pixel emitting light of a second color through a second emission region, and a third pixel emitting light of a third color through a third emission region.

[0131] The organic material layer of the first light-emitting layer of the first emission region emitting light of the first color may be a phosphorescent material including a host material including carbazole biphenyl (CBP) or mCP (1,3-bis(carbazole-9-yl) and including a dopant including at least one of PIQIr(acac) (bis(1-phenylisoquinoline) iridium acetylacetonate), PQIr(acac) (bis(1-phenylquinoline) iridium acetylacetonate), PQIr(tris(1-phenylquinoline)iridium) and PtOEP (octaethylporphyrin platinum). In other embodiments, the organic material layer of the first light-emitting layer of the first emission region may be a fluorescent material including PBD:Eu(DBM)3(Phen) or dinaphthylenediol, but is not limited thereto.

[0132] The organic material layer of the second light-emitting layer of the second emission region emitting light of the second color may be a phosphorescent material including a host material comprising CBP or mCP and a doping material comprising fac tris(2-phenylpyridine)iridium (Ir(ppy)3). In other embodiments, the organic material layer of the second light-emitting layer of the second emission region emitting light of the second color may be a fluorescent material including tris(8-hydroxyquinoline)aluminum (Alq3), but is not limited thereto.

[0133] The organic material layer of the light emitting layer of the third emission region emitting light of the third color may be a phosphorescent material including a host material including CBP or mCP and a dopant material including (4,6-F2ppy)2Irpic or L2BD111.

[0134] The common electrode CM may be arranged on the light-emitting layer EL. For example, the common electrode CM may be arranged on the first light-emitting layer, the second light-emitting layer, and the third light-emitting layer. The common electrode CM may cover the first light-emitting layer, the second light-emitting layer, and the third light-emitting layer. The common electrode CM may be a common layer arranged on the first light-emitting layer to the third light-emitting layer. A capping layer may be formed on the common electrode CM.

[0135] In the top emission structure, the common electrode CM may be formed of a transparent conductive material (TCO) such as ITO or IZO capable of transmitting light, or a semi-transmissive conductive material such as magnesium (Mg), silver (Ag), or an alloy of magnesium (Mg) and silver (Ag). In the case where the common electrode CM is formed of a semi-transmissive conductive material, the light emitting efficiency may be improved by a microcavity.

[0136] The encapsulation layer ENC may be arranged on the light emitting element layer EMTL. The encapsulation layer ENC may include at least one inorganic layer to prevent oxygen or moisture from penetrating into the light emitting element layer EMTL. In addition, the encapsulation layer ENC may include at least one organic layer to protect the light emitting element layer EMTL from foreign matter such as dust. For example, the encapsulation layer ENC may include a first encapsulation inorganic layer TFE1, an encapsulation organic layer TFE2, and a second encapsulation inorganic layer TFE3.

[0137] The first encapsulation inorganic layer TFE1 may be disposed on the common electrode CM, the encapsulation organic layer TFE2 may be disposed on the first encapsulation inorganic layer TFE1, and the second encapsulation inorganic layer TFE3 may be disposed on the encapsulation organic layer TFE2. The first encapsulation inorganic layer TFE1 and the second encapsulation inorganic layer TFE3 may be formed as a plurality of layers in which one or more inorganic layers of a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, and an aluminum oxide layer are alternately stacked. The encapsulation organic layer TFE2 may be an organic layer made of an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin.

[0138] The barrier layer may be between the substrate SUB described above and the light blocking layer BML. The barrier layer may be a layer for protecting the first transistor T1 to the third transistor T3 of the thin film transistor layer TFTL and the light emitting layer EL of the light emitting element layer EMTL from moisture penetrating through the substrate SUB susceptible to moisture penetration. The barrier layer may include a plurality of inorganic layers alternately stacked. For example, the barrier layer may be formed as a plurality of layers in which one or more inorganic layers of a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, and an aluminum oxide layer are alternately stacked.

[0139] refer to Figure 5 and Figure 6 The operation of the data driver 220 is described in detail as follows.

[0140] like Figure 5 As shown in FIG. 1 , the data driver 220 may be connected to the first data line DL1 and the second data line DL2 .

[0141] The data driver 220 may generate a first data voltage V1 and a second data voltage V2. The data driver 220 may apply the first data voltage V1 to the first data line DL1 and the second data voltage V2 to the second data line DL2.

[0142] The data driver 220 may simultaneously apply the first data voltage V1 and the second data voltage V2 to the first data line DL1 and the second data line DL2, respectively. To this end, according to an embodiment, the second transistor T2 and the third transistor T3 may be turned on at the same time. For example, the turn-on time of the second transistor T2 and the turn-on time of the third transistor T3 may be the same. The first data voltage V1 from the data driver 220 may be applied to the first data line DL1 at the turn-off time of the second transistor T2, and the second data voltage V2 from the data driver 220 may be applied to the second data line DL2 at the turn-off time of the third transistor T3. The turn-off time of the second transistor T2 and the turn-off time of the third transistor T3 may also be the same. To this end, in an embodiment, the first gate signal GS1 applied to the first gate line GL1 connected to the gate electrode of the second transistor T2 and the second gate signal GS2 applied to the second gate line GL2 connected to the gate electrode of the third transistor T3 may be the same. For example, during the light emission period of the pixel PX, the first gate signal GS1 applied to the first gate line GL1 and the second gate signal GS2 applied to the second gate line GL2 may be output simultaneously and maintained for some periods.

[0143] The conduction amplitude of the first transistor T1 can be controlled by the first data voltage V1 and the second data voltage V2. For example, in the case where the first transistor T1 is an n-type transistor, the first transistor T1 can be turned on so that as the first data voltage V1 becomes larger, more current flows through the first transistor T1, and the first transistor T1 can be turned on so that as the second data voltage V2 becomes smaller, less current flows through the first transistor T1. For example, in the case where the second data voltage V2 is a negative voltage, the larger the absolute value of the negative voltage, the smaller the current flowing through the first transistor T1 can be. The second data voltage V2 can have a different amplitude from the first data voltage V1. On the other hand, in the case where the first transistor T1 is a p-type transistor, the first transistor T1 can be turned on so that as the first data voltage V1 becomes smaller, a larger current flows, and the first transistor T1 can be turned on so that as the second data voltage V2 becomes larger, a smaller current flows. For example, in the case where the second data voltage V2 is a positive voltage, the larger the absolute value of the positive voltage, the smaller the current flowing through the first transistor T1 can be.

[0144] The amplitude of the first data voltage V1 and the amplitude of the second data voltage V2 may be different. For example, the amplitude of the second data voltage V2 may be smaller than the amplitude of the first data voltage V1. At this time, the amplitude of the second data voltage V2 may vary according to the amplitude of the first data voltage V1. In an embodiment, the amount of change in the amplitude of the first data voltage V1 and the amount of change in the amplitude of the second data voltage V2 may be inversely proportional. For example, when the first data voltage V1 has a larger value, the second data voltage V2 may have a smaller value, and when the first data voltage V1 has a smaller value, the second data voltage V2 may have a larger value.

[0145] In an embodiment, in the case where the first data voltage V1 has a value included in a preset range from a lower limit value to an upper limit value, the amplitude of the second data voltage V2 may vary according to the amplitude of the first data voltage V1 as described above. In an embodiment, in the case where the first data voltage V1 has a value included in a preset range from a lower limit value to an upper limit value, the amount of change in the amplitude of the first data voltage V1 and the amount of change in the amplitude of the second data voltage V2 may be inversely proportional to the above. In the case where the first data voltage V1 is less than the lower limit value, the amplitude of the second data voltage V2 may be maintained at a value corresponding to when the first data voltage V1 is the lower limit value. For example, in the case where the first data voltage V1 is the lower limit value and the amplitude of the corresponding second data voltage V2 is 3V, even in the case where the first data voltage V1 becomes less than the lower limit value, the amplitude of the second data voltage V2 can be maintained at 3V without changing. On the other hand, in the case where the first data voltage V1 is greater than the upper limit value, the amplitude of the second data voltage V2 may be maintained at a value corresponding to when the first data voltage V1 is the upper limit value. For example, when the first data voltage V1 is the upper limit value and the amplitude of the corresponding second data voltage V2 is 1V, even if the first data voltage V1 becomes greater than the upper limit value, the amplitude of the second data voltage V2 can be maintained at 1V without changing.

[0146] In an embodiment, the first data voltage V1 and the second data voltage V2 may have the same value but opposite polarities. For example, in a case where the first transistor T1 is an n-type transistor, when the first data voltage V1 is +3V, the second data voltage V2 may be -3V. On the other hand, in a case where the first transistor T1 is a p-type transistor, when the first data voltage V1 is -3V, the second data voltage V2 may be +3V.

[0147] As described above, in the case where the amplitude of the second data voltage V2 applied to the second gate electrode GE2 of the first transistor T1 changes according to the amplitude of the first data voltage V1 applied to the first gate electrode GE1 of the first transistor T1, the characteristic curve of the first transistor T1 (for example, a characteristic curve showing the amount of change of the drain current according to the gate-source voltage of the first transistor T1) can be changed. Therefore, by appropriately changing the amplitude of the second data voltage V2 according to the first data voltage V1, the characteristic curve of the first transistor T1 can be changed to have a gentle slope. The fact that the characteristic curve of the first transistor T1 has a gentle slope can mean that the display device 10 can ensure a wider driving range. Therefore, the display device 10 according to the embodiment can express the grayscale in more detail, thereby improving the image quality. For example, in the case where the first data voltage V1 and the second data voltage V2 have the same value but opposite polarities, the characteristic curve of the first transistor T1 can have a gentler slope.

[0148] Figure 7 is a schematic circuit diagram of one pixel PX of the display device 10 according to the embodiment and a schematic diagram illustrating a data driver 220 and a voltage conversion circuit VCC.

[0149] Figure 7 The display device 10 described above Figure 5 The display device 10 of FIG. 1 may be different from that of FIG. 1 at least in that a voltage conversion circuit VCC is further included, and the difference will be described.

[0150] first, Figure 7 The data driver 220 may generate a first data voltage V1. The first data voltage V1 from the data driver 220 may be applied to the first data line DL1 and the voltage conversion circuit VCC.

[0151] The voltage conversion circuit VCC may be connected between the first data line DL1 and the second data line DL2. The voltage conversion circuit VCC may receive the first data voltage V1 through the first data line DL1 and convert the first data voltage V1 into a second data voltage V2. The second data voltage V2 from the voltage conversion circuit VCC may be applied to the second data line DL2.

[0152] According to an embodiment, the voltage conversion circuit VCC may be disposed on the display panel 100. For example, the voltage conversion circuit VCC may be placed outside the pixel circuit PC.

[0153] because Figure 7 The first data voltage V1 may be the same as described above. Figure 5 The first data voltage V1 is the same as Figure 7 The second data voltage V2 may be the same as described above. Figure 5The second data voltage V2 is the same as that of Figure 5 The relevant description given above is Figure 7 Detailed description of the first data voltage V1 and the second data voltage V2.

[0154] Figure 8 is a schematic circuit diagram of one pixel PX of the display device 10 according to the embodiment and a schematic diagram illustrating a data driver 220 and a voltage conversion circuit VCC.

[0155] Figure 8 The display device 10 described above Figure 5 The display device 10 of FIG. 1 may be different from that of FIG. 1 at least in that a voltage conversion circuit VCC is further included, and the difference will be described.

[0156] first, Figure 8 The data driver 220 may generate a first data voltage V1. The first data voltage V1 from the data driver 220 may be applied to the first data line DL1.

[0157] The first data voltage V1 of the first data line DL1 may be applied to the first gate electrode GE1 of the first transistor T1 through the turned-on second transistor T2. Considering the resistance between the source electrode and the drain electrode of the second transistor T2, the first data voltage V1 of the first data line DL1 and the first data voltage V1' of the first gate electrode GE1 may not completely match. For example, the first data voltage V1' of the first gate electrode GE1 may be less than the first data voltage V1 of the first data line DL1.

[0158] The voltage conversion circuit VCC may be connected between the first gate electrode GE1 and the second gate electrode GE2 of the first transistor T1. The voltage conversion circuit VCC may receive the first data voltage V1 through the first data line DL1 and the second transistor T2, and convert the received first data voltage V1 (i.e., the first data voltage V1') into a second data voltage V2. The second data voltage V2 from the voltage conversion circuit VCC may be applied to the second gate electrode GE2 of the first transistor T1.

[0159] According to an embodiment, the voltage conversion circuit VCC may be disposed in the pixel circuit PC.

[0160] because Figure 8 The first data voltage V1 may be the same as described above. Figure 5 The first data voltage V1 is the same as Figure 8 The second data voltage V2 may be the same as described above. Figure 5 The second data voltage V2 is the same as that of Figure 5 The relevant description given above is Figure 8Detailed description of the first data voltage V1 and the second data voltage V2.

[0161] Fig. 9 is a schematic circuit diagram of one pixel PX of the display device 10 according to the embodiment and a schematic diagram illustrating the data driver 220 .

[0162] Fig. 9 The display device 10 described above Figure 5 The display device 10 of the embodiment of the present invention may be different at least in that a first capacitor Cst1 and a second capacitor Cst2 are included, and the difference will be described.

[0163] like Fig. 9 As shown in FIG. 1 , the pixel circuit PC may further include a second capacitor Cst2. The second capacitor Cst2 may be connected between the second gate electrode GE2 of the first transistor T1 and the driving voltage line VDL. The second capacitor Cst2 may store the second data voltage V2.

[0164] Fig. 9 The first capacitor Cst1 can be connected with the above described Figure 5 The capacitor Cst is the same.

[0165] Described above Figure 7 and Figure 8 Each pixel circuit PC may also include Fig. 9 The second capacitor Cst2 is shown in FIG.

[0166] Fig.10 is a schematic circuit diagram of one pixel PX of the display device 10 according to the embodiment and a schematic diagram illustrating the data driver 220 .

[0167] Fig.10 The display device 10 described above Figure 5 The display device 10 may be different from that of FIG. 1 at least in the connection relationship of the capacitor Cst, and the difference will be described.

[0168] like Fig.10 As shown in FIG. 1 , the capacitor Cst may be connected between the first gate electrode GE1 of the first transistor T1 and the second gate electrode GE2 of the first transistor T1. The capacitor Cst may store the first data voltage V1 and the second data voltage V2.

[0169] Described above Figure 7 and Figure 8 The capacitor Cst of each pixel circuit PC can be used Fig.10 The capacitor Cst shown in the figure is used instead.

[0170] A method of driving the display device 10 according to an embodiment will be described as follows.

[0171] First, a light emitting element ED and a first transistor T1 may be prepared. For example, a light emitting element ED and a first transistor T1 may be prepared. Figure 5 , Figure 7 , Figure 8 , Fig. 9 and Fig.10 Any one of the pixel circuits PC shown in the figure.

[0172] The first data voltage V1 may be applied to the first gate electrode GE1 of the first transistor T1, and the second data voltage V2 may be applied to the second gate electrode GE2 of the first transistor T1. The first data voltage V1 may be applied to the first gate electrode GE1 of the first transistor T1 through the first data line DL1 and the second transistor T2. In addition, the second data voltage V2 may be applied to the second gate electrode GE2 of the first transistor T1 through the second data line DL2, may be applied to the second gate electrode GE2 of the first transistor T1 through the voltage conversion circuit VCC described above, the second data line DL2, and the third transistor T3, and may be applied to the second gate electrode GE2 of the first transistor T1 through the voltage conversion circuit VCC described above.

[0173] Here, the first data voltage V1 may be Figure 5 , Figure 7 , Figure 8 , Fig. 9 and Fig.10 The first data voltage V1 of any one of the above data voltages may be the same, and the second data voltage V2 may be the same as that described above. Figure 5 , Figure 7 , Figure 8 , Fig. 9 and Fig.10 The second data voltage V2 of any one of them is the same.

[0174] Fig.11 It is a schematic diagram for explaining the effect of the display device 10 according to the embodiment.

[0175] exist Fig.11 , the first characteristic curve C1 is a characteristic curve of the drain current ID and the gate-source voltage VGS of the first transistor T1 provided in the display device 10 to be compared, and the second characteristic curve C2 is a characteristic curve of the drain current ID and the gate-source voltage VGS of the first transistor T1 provided in the display device 10 according to the embodiment.

[0176] like Fig.11As shown in FIG. 1 , the second characteristic curve C2 may have a gentler slope than the first characteristic curve C1. Therefore, the display device 10 according to the embodiment may ensure a wider operating range than the compared display device. Therefore, the display device 10 according to the embodiment may express grayscale levels in more detail, thereby improving image quality.

[0177] Embodiments have been disclosed herein, and although terms are employed, they are used and interpreted in a general and descriptive sense only and not for purposes of limitation. In some cases, as will be apparent to one of ordinary skill in the art, features, characteristics, and / or elements described in conjunction with embodiments may be used alone or in combination with features, characteristics, and / or elements described in conjunction with other embodiments, unless expressly stated otherwise. Therefore, one of ordinary skill in the art will appreciate that various changes in form and detail may be made without departing from the spirit and scope of the present disclosure.

Claims

1. A display device, comprising: Light emitting element; A first transistor connected between a driving voltage line and the light emitting element, the first transistor comprising: a first gate electrode and a second gate electrode facing each other, and an active layer between the first gate electrode and the second gate electrode; a first data line connected to the first gate electrode of the first transistor; a second data line connected to the second gate electrode of the first transistor; and a data driver connected to the first data line and the second data line, wherein the data driver applies a first data voltage to the first data line and applies a second data voltage having a different magnitude from the first data voltage to the second data line, and The magnitude of the second data voltage varies according to the magnitude of the first data voltage.

2. The display device according to claim 1, wherein: The amplitude of the second data voltage is changed according to the amplitude of the first data voltage, so that a change amount of the amplitude of the first data voltage is inversely proportional to a change amount of the amplitude of the second data voltage.

3. The display device according to claim 1, wherein: In a case where the first data voltage has a value included in a range from a preset lower limit value to an upper limit value, the amplitude of the second data voltage changes according to the amplitude of the first data voltage, so that a change amount of the amplitude of the first data voltage is inversely proportional to a change amount of the amplitude of the second data voltage, In the case where the first data voltage is less than the lower limit value, the amplitude of the second data voltage is maintained at a value corresponding to the first data voltage having the lower limit value, and In the case where the first data voltage is greater than the upper limit value, the magnitude of the second data voltage is maintained at a value corresponding to the first data voltage having the upper limit value.

4. The display device according to claim 1, wherein: The magnitude of the second data voltage is changed according to the magnitude of the first data voltage so that the first data voltage and the second data voltage have the same magnitude but opposite polarities.

5. The display device according to claim 1, wherein: The data driver simultaneously applies the first data voltage and the second data voltage to the first data line and the second data line, respectively.

6. The display device according to claim 1, further comprising: A second transistor is connected between the first data line and the first gate electrode of the first transistor.

7. The display device according to claim 6, further comprising: A third transistor is connected between the second data line and the second gate electrode of the first transistor.

8. The display device according to claim 7, wherein: The on-time and the off-time of the second transistor are the same as the on-time and the off-time of the third transistor.

9. A display device, comprising: Light emitting element; A transistor connected between a driving voltage line and the light emitting element, the transistor comprising: a first gate electrode and a second gate electrode facing each other, and an active layer between the first gate electrode and the second gate electrode; a first data line connected to the first gate electrode of the transistor; a second data line connected to the second gate electrode of the transistor; a data driver connected to the first data line; and a conversion circuit connected between the first data line and the second data line, wherein the data driver applies a first data voltage to the first data line, The conversion circuit generates a second data voltage according to the first data voltage, and the generated second data voltage is applied to the second data line, The first data voltage and the second data voltage have different magnitudes from each other, and The magnitude of the second data voltage varies according to the magnitude of the first data voltage.

10. A display device, comprising: Light emitting element; A transistor connected between a driving voltage line and the light emitting element, the transistor comprising: a first gate electrode and a second gate electrode facing each other, and an active layer between the first gate electrode and the second gate electrode; a data line connected to the first gate electrode of the transistor; a data driver connected to the data line; and a voltage conversion circuit connected between the first gate electrode of the transistor and the second gate electrode of the transistor, wherein the data driver applies a first data voltage to the data line, the voltage conversion circuit generates a second data voltage based on the first data voltage applied to the first gate electrode through the data line, and applies the generated second data voltage to the second gate electrode, The first data voltage and the second data voltage have different amplitudes, and The magnitude of the second data voltage varies according to the magnitude of the first data voltage.

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