Voltage generating circuit and long sequence pulse output unevenness adjusting method thereof

Abstract

The invention discloses a voltage generating circuit and a long sequence pulse output unevenness adjusting method thereof.The voltage generating circuit comprises an interface circuit, an FPGA, a memory, a D / A converter, an operational amplifier and a power conversion circuit, the interface circuit is used for converting various external control signal levels into signals which can be recognized by the FPGA and inputting the signals into the FPGA, and the interface circuit is used for converting various external control signal levels into signals which can be recognized by the FPGA; the FPGA collects radio frequency signal synchronization pulses from input signals and detects the radio frequency signal synchronization pulses, and is used for realizing segmented statistics of pulse sequences, controlling the D / A converter to dynamically output analog signals according to grid voltage calculation parameters preset in the memory, outputting grid voltage after the analog signals pass through the operational amplifier, and realizing dynamic adjustment of the grid voltage. Therefore, the purpose of long sequence pulse high-power output unevenness adjustment is achieved, an L wave band radio frequency pulse amplifier with the output power being about 700 W is achieved, sequence unevenness adjustment of continuous 770 pulses is achieved, and the sequence unevenness is controlled to be smaller than or equal to 1 dB.

Description

Technical Field

[0001] The invention relates to the technical field of power amplifiers, and in particular to a voltage generating circuit and a method for regulating the unevenness of a long sequence pulse output thereof. Background Art

[0002] At present, the transmitters in the field of airborne integrated avionics equipment technology belong to multi-mode transmitters, and their functions and signal formats generally include aviation control, ADS-B, DME, TACAN, data link, etc. The current multi-mode transmitters generally use GaN power amplifier tubes to achieve the amplification function of the port power of the order of 1000W to 2000W, and their modulation technology system generally uses drain high voltage modulation technology to achieve RF modulation of aviation control, ADS-B, DME, TACAN, data link and other mode signals. At the same time, gate voltage modulation is also used to adjust the power amplifier tube to a suitable working point.

[0003] The pulse power amplifier needs to amplify a series of modulated pulses. Depending on the working mode, working distance and other requirements, the number of pulses in a series varies, ranging from a few to hundreds. The amplitude of each pulse power should be consistent in theory. However, when the output power is as large as hundreds of watts, due to the influence of complex factors such as the instantaneous thermal effect of the GaN power amplifier tube and the power supply, the power of a single pulse in the transmitted pulse sequence will be differentiated. Generally, the later the pulse in the sequence, the smaller the output power. The difference between the power value of the maximum pulse and the power value of the minimum pulse in a single transmission cycle is the sequence unevenness. The ideal sequence unevenness should be 0dB, but in actual applications, when the transmission sequence is long, the sequence unevenness of the GaN power amplifier tube output signal is difficult to guarantee. To solve this problem, it is usually necessary to set the gate voltage value of different time periods by setting a lookup table through a digital processing circuit, so as to compensate for the amplifier gain of different time periods. Since the segmentation of the digital processing circuit is limited by the storage capacity of the digital circuit, there may be large differences in the sequence between the segments. Summary of the invention

[0004] The object of the present invention is to overcome the deficiencies of the prior art and to provide a voltage generating circuit and a method for adjusting the unevenness of a long sequence pulse output thereof.

[0005] The objective of the present invention is achieved through the following technical solutions: In a first aspect, the present invention discloses a voltage generating circuit, comprising an interface circuit, an FPGA, a memory, a D / A converter, an operational amplifier and a power conversion circuit, wherein the output end of the interface circuit and the memory is connected to the input end of the FPGA, the output end of the FPGA is connected to the input end of the D / A converter, the output end of the D / A converter is connected to the input end of the operational amplifier, and the power conversion circuit is connected to the FPGA, the D / A converter and the operational amplifier respectively; The interface circuit is used to convert multiple external control signal levels into signals recognizable by the FPGA and input them into the FPGA. The FPGA collects and detects the radio frequency signal synchronization pulses from the input signal to realize the segmented statistics of the pulse sequence, and controls the D / A converter to dynamically output the analog signal according to the gate voltage calculation parameters preset in the memory. The analog signal outputs the gate voltage after passing through the operational amplifier to realize the dynamic adjustment of the gate voltage, thereby achieving the purpose of adjusting the unevenness of long-sequence pulse high-power output.

[0006] Based on the first aspect, the voltage generating circuit generates a pulse voltage according to the input radio frequency signal synchronization pulse, which is used to control the gate voltage of the GaN power amplifier tube, thereby controlling the output power of the GaN power amplifier tube.

[0007] Based on the first aspect, the interface circuit converts the levels of various external control signals into signals recognizable by the FPGA through I / O driving.

[0008] Based on the first aspect, it also includes a crystal oscillator and a debugging interface module, the output end of the crystal oscillator is connected to the input end of the FPGA, the debugging interface module is provided with a serial port, and the output end of the debugging interface module is connected to the input end of the FPGA through the serial port.

[0009] In a second aspect, the present invention discloses a method for adjusting the unevenness of a long sequence pulse output, which is used in a voltage generating circuit as described in any one of the above items, and specifically comprises the following steps: S1, read the preset value in the memory and cache it into the FPGA to improve the response speed of gate voltage regulation; S2. When the RF signal synchronization pulse is at a high level and valid, detect in real time whether the RF signal synchronization pulse has a rising edge; when the RF signal synchronization pulse is at a low level and valid, detect in real time whether the RF signal synchronization pulse has a falling edge; S3, when the RF signal synchronization pulse appears at a valid level, the processing program counts the number of pulses, and calculates the digital value of the gate voltage corresponding to the current pulse according to the number of gate voltage segments, the number of pulses in each segment and the gate voltage value preset in the memory; S4, configuring the digital value of the gate voltage corresponding to the current pulse to the D / A converter, and making the D / A converter output the corresponding analog signal; S5. Complete the gate voltage adjustment of a pulse signal and return to step S1.

[0010] Based on the second aspect, the gate voltage adjustment of a pulse signal in step S5 specifically includes the following steps: S51, enter the module debugging interface; S52. The transmitter's operating modes include ADS-B, DME, TACAN and data link, of which only the data link is in long pulse mode, so that the transmitter enters the data link mode, i.e. the gate voltage long pulse debugging mode; S53, determining the number of gate voltage segments, the number of pulses in each segment, and the gate voltage value according to the factory test curve of the power amplifier tube; S54, writing the segment number, the number of pulses per segment and the gate voltage value into the data FLASH through the debugging interface; S55, call the FLASH data according to the working mode and temperature, and automatically calculate and generate each segment of gate voltage data according to the segmented data; call the FLASH data within the temperature value range transmitted back by the temperature sensor; suppose there are M pulses in N segments, and calculate the Xth gate voltage value V in N segments according to the Nth segment gate voltage value VA and the N+1th segment gate voltage value VB: V=VA+X(VB-VA) / M; S56, if the sequence is less than 1dB, the test is qualified; if the sequence is greater than or equal to 1dB, the test is unqualified, and the process returns to step S53; S57, confirm that the debugging is qualified, and the debugging is completed.

[0011] The beneficial effects of the present invention are: 1) The present invention realizes an L-band RF pulse amplifier with an output power of about 700W, and realizes sequence unevenness adjustment of 770 consecutive pulses, controlling the sequence unevenness to ≤1dB.

[0012] 2) The present invention uses digital gate voltage adjustment technology, and the gate voltage of each segment can be easily adjusted through the debugging interface. At the same time, the single pulse gate voltage in each segment can be adjusted in steps, which can be compensated with the power amplifier characteristics and can be flexibly adjusted according to different usage environments (mainly temperature environments). BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 A schematic diagram of hardware implementation of an embodiment of the present invention; Figure 2 is a schematic diagram of a gate voltage generating circuit according to an embodiment of the present invention; Figure 3 A timing diagram of pulse voltage generation according to an embodiment of the present invention; Figure 4 Schematic diagram of the gate voltage control process of an embodiment of the present invention; Figure 5 A schematic diagram of gate voltage adjustment according to an embodiment of the present invention; Figure 6 A schematic diagram of an input radio frequency modulated pulse train after detection according to an embodiment of the present invention; Figure 7It is a schematic diagram of an output RF modulated pulse train after detection and without gate segmentation control according to an embodiment of the present invention; Figure 8 A schematic diagram of gate voltage after segmented control of gate voltage according to an embodiment of the present invention; Fig. 9 Schematic diagram of an output RF modulated pulse train controlled by gate segmentation according to an embodiment of the present invention. DETAILED DESCRIPTION

[0014] The technical solution of the present invention will be clearly and completely described below in conjunction with the embodiments. Obviously, the described embodiments are only part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present invention.

[0015] The present invention discloses a voltage generating circuit and a method for adjusting the unevenness of a long sequence pulse output thereof. A GaN power amplifier tube is a voltage-controlled amplifier device, which can change the opening degree of an internal conductive channel by changing the control voltage of the amplifier, thereby changing the amplifier gain. The present invention sets the gate voltage value of different time periods by setting a lookup table through a digital processing circuit, thereby compensating the amplifier gain of different time periods. The present invention takes a GaN power amplifier tube circuit as an embodiment, and controls the pulse unevenness of the entire sequence to ≤1dB in one cycle (i.e., one sequence emits 770 pulses with a width of 7μs).

[0016] The GaN power amplifier tube has an output power of more than 800 watts within the working frequency band, 16dB amplification gain, a +40V DC drain voltage, and a gate control voltage of -5V to -2V. When the gate voltage is ≤-10V, the power amplifier tube has an isolation greater than 20dB, and between -5V and -2V, the output of the power amplifier tube has a good linear relationship with the gate voltage. Therefore, this linear relationship can be used to adjust the output power of the power amplifier tube by adjusting the gate voltage. The gate operating current is below the milliampere level and can be driven by an ordinary digital logic circuit. The hardware implementation schematic diagram of the present invention is shown in FIG. Figure 1 shown.

[0017] Exemplarily, the present invention discloses a voltage generating circuit, including an interface circuit, an FPGA, a memory, a D / A converter, an operational amplifier and a power conversion circuit, wherein the output end of the interface circuit and the memory is connected to the input end of the FPGA, the output end of the FPGA is connected to the input end of the D / A converter, the output end of the D / A converter is connected to the input end of the operational amplifier, and the power conversion circuit is connected to the FPGA, the D / A converter and the operational amplifier respectively; the schematic diagram of the gate voltage generating circuit is as shown in Figure 2 shown.

[0018] Specifically, the interface circuit is used to convert multiple external control signal levels into signals recognizable by the FPGA and input them into the FPGA. The FPGA collects and detects the radio frequency signal synchronization pulses from the input signal to realize the segmented statistics of the pulse sequence, and controls the D / A converter to dynamically output the analog signal according to the gate voltage calculation parameters preset in the memory. The analog signal outputs the gate voltage after passing through the operational amplifier to realize the dynamic adjustment of the gate voltage, thereby achieving the purpose of adjusting the unevenness of the long sequence pulse high-power output.

[0019] Specifically, the voltage generating circuit generates a pulse voltage according to the input RF signal synchronization pulse, which is used to control the gate voltage of the GaN power amplifier tube, thereby controlling the output power of the GaN power amplifier tube. The timing diagram of the pulse voltage generation is shown in FIG. Figure 3 As shown, there are about 770 pulses in the RF signal synchronization pulse and pulse voltage, each pulse is 8 .

[0020] Specifically, the interface circuit converts various external control signal levels into signals recognizable by the FPGA through I / O driving.

[0021] Specifically, it also includes a crystal oscillator and a debugging interface module, the output end of the crystal oscillator is connected to the input end of the FPGA, the debugging interface module is provided with a serial port, and the output end of the debugging interface module is connected to the input end of the FPGA through the serial port.

[0022] Exemplarily, the present invention also discloses a method for adjusting the unevenness of long sequence pulse output, which is used in the above-mentioned voltage generating circuit, and the flow chart of the gate voltage control is as follows: Figure 4 As shown, the method specifically comprises the following steps: S1, read the preset value in the memory and cache it into the FPGA to improve the response speed of gate voltage regulation; S2. When the RF signal synchronization pulse is at a high level and valid, detect in real time whether the RF signal synchronization pulse has a rising edge; when the RF signal synchronization pulse is at a low level and valid, detect in real time whether the RF signal synchronization pulse has a falling edge; S3, when the RF signal synchronization pulse appears at a valid level, the processing program counts the number of pulses, and calculates the digital value of the gate voltage corresponding to the current pulse according to the number of gate voltage segments, the number of pulses in each segment and the gate voltage value preset in the memory; S4, configuring the digital value of the gate voltage corresponding to the current pulse to the D / A converter, and making the D / A converter output the corresponding analog signal; S5. Complete the gate voltage adjustment of a pulse signal and return to step S1.

[0023] Specifically, the output amplitude of each pulse voltage can be adjusted according to the characteristics of the GaN power amplifier tube, so that the output power of the GaN power amplifier tube in the entire sequence meets the unevenness requirements. This usage requires the entire machine to provide a synchronous pulse of the RF signal to achieve the output of a pulsed gate voltage. The output gate pulse voltage can be adjusted by changing the preset value in the memory. The 770 pulses in a sequence are segmented, and the output gate voltage is set in segments. The output amplitude of each segment can be adjusted separately through the debugging interface. The gate voltage of the rear segment is increased, and the single pulse gate voltage between the front and rear segments can be linearly stepped. This can compensate for the gain loss caused by the instantaneous thermal effect of the power amplifier tube itself. In this way, the output amplitude of the signal after amplification by the power amplifier will be closer to the output signal in the ideal state. The schematic diagram of the gate voltage adjustment is shown as follows Figure 5 As shown, the gate voltage regulation of a pulse signal in step S5 specifically includes the following steps: S51, enter the module debugging interface; S52. The transmitter's operating modes include ADS-B, DME, TACAN and data link, of which only the data link is in long pulse mode, so that the transmitter enters the data link mode, i.e. the gate voltage long pulse debugging mode; S53, determining the number of gate voltage segments, the number of pulses in each segment, and the gate voltage value according to the factory test curve of the power amplifier tube; S54, writing the segment number, the pulse number of each segment and the gate voltage value into the data FLASH through the debugging interface; S55, call the FLASH data according to the working mode and temperature, and automatically calculate and generate each segment of gate voltage data according to the segmented data; call the FLASH data within the temperature value range transmitted back by the temperature sensor; suppose there are M pulses in N segments, and calculate the Xth gate voltage value V in N segments according to the Nth segment gate voltage value VA and the N+1th segment gate voltage value VB: V=VA+X(VB-VA) / M; S56, if the sequence is less than 1dB, the test is qualified; if the sequence is greater than or equal to 1dB, the test is unqualified, and the process returns to step S53; S57, confirm that the debugging is qualified, and the debugging is completed.

[0024] Specifically, the RF input signal (after detection) is Figure 6 As shown, Figure 6 There are about 770 pulses, each with 7 , the amplitude of each pulse is consistent, and the unevenness of the pulse sequence is good. The GaN power amplifier uses a constant gate voltage, that is, the signal diagram after power amplification without gate segmentation control is as follows Figure 7 As shown, Figure 7 There are about 770 pulses, each with 7 ; Pulse sequence unevenness> 1.8dB. The gate voltage of the GaN power amplifier tube is controlled in sections, as shown in the schematic diagram Figure 8 As shown, Figure 8 There are about 770 pulses in the circuit, each pulse is divided into 5 segments of 8μs, the output amplitude of each segment is inconsistent, the gate voltage of each segment can be arbitrarily segmented, the number of pulses in each segment can be set, and the gate voltage of each pulse can be increased and adjusted through the PC interface. The gate voltage frame should be slightly wider than the RF pulse. The schematic diagram of the signal waveform output after the gate voltage segment adjustment is shown in the figure below. Fig. 9 As shown, Fig. 9 There are about 770 pulses in the system, each pulse is 7μs, and the unevenness of the pulse sequence is significantly improved, which can meet the overall machine requirement of ≤1dB.

[0025] Specifically, a 20000μF capacitor can be used to eliminate the cause of insufficient power supply. However, the volume and weight of a 20000μF capacitor are unbearable for a miniaturized transmitter. The gate voltage value for different time periods can also be set by setting a lookup table through a digital processing circuit, but the index is poor. This application realizes an L-band RF pulse amplifier with an output power of about 700W, and realizes the sequence unevenness adjustment of 770 consecutive pulses, controlling the sequence unevenness to ≤1dB, such as Figure 7 This application uses digital gate voltage adjustment technology, and each segmented gate voltage can be easily adjusted through the debugging interface. At the same time, the single pulse gate voltage in each segment can be adjusted in steps, which can be compensated with the power amplifier characteristics and can be flexibly adjusted according to different usage environments (mainly temperature environments).

[0026] The above is only a preferred embodiment of the present invention. It should be understood that the present invention is not limited to the form disclosed herein, and should not be regarded as excluding other embodiments, but can be used in various other combinations, modifications and environments, and can be modified within the scope of the concept described herein through the above teachings or the technology or knowledge of the relevant field. The changes and modifications made by those skilled in the art shall not deviate from the spirit and scope of the present invention, and shall be within the scope of protection of the claims attached to the present invention.

Claims

1. A voltage generating circuit, characterized in that: It includes an interface circuit, an FPGA, a memory, a D / A converter, an operational amplifier and a power conversion circuit, wherein the output end of the interface circuit and the memory is connected to the input end of the FPGA, the output end of the FPGA is connected to the input end of the D / A converter, the output end of the D / A converter is connected to the input end of the operational amplifier, and the power conversion circuit is connected to the FPGA, the D / A converter and the operational amplifier respectively; The interface circuit is used to convert multiple external control signal levels into signals recognizable by the FPGA and input them into the FPGA. The FPGA collects and detects the radio frequency signal synchronization pulses from the input signal to realize the segmented statistics of the pulse sequence, and controls the D / A converter to dynamically output the analog signal according to the gate voltage calculation parameters preset in the memory. The analog signal outputs the gate voltage after passing through the operational amplifier to realize the dynamic adjustment of the gate voltage, thereby achieving the purpose of adjusting the unevenness of long-sequence pulse high-power output.

2. A voltage generating circuit according to claim 1, characterized in that: The voltage generating circuit generates a pulse voltage according to the input radio frequency signal synchronization pulse, which is used to control the gate voltage of the GaN power amplifier tube, thereby controlling the output power of the GaN power amplifier tube.

3. A voltage generating circuit according to claim 1, characterized in that: The interface circuit converts various external control signal levels into signals recognizable by the FPGA through I / O driving.

4. A voltage generating circuit according to claim 1, characterized in that: It also includes a crystal oscillator and a debugging interface module. The output end of the crystal oscillator is connected to the input end of the FPGA. The debugging interface module is provided with a serial port. The output end of the debugging interface module is connected to the input end of the FPGA through the serial port.

5. A method for adjusting the unevenness of long sequence pulse output, used in a voltage generating circuit according to any one of claims 1 to 4, characterized in that: The specific steps include: S1, read the preset value in the memory and cache it into the FPGA to improve the response speed of gate voltage regulation; S2. When the RF signal synchronization pulse is at a high level and valid, detect in real time whether the RF signal synchronization pulse has a rising edge; when the RF signal synchronization pulse is at a low level and valid, detect in real time whether the RF signal synchronization pulse has a falling edge; S3, when the RF signal synchronization pulse appears at a valid level, the processing program counts the number of pulses, and calculates the digital value of the gate voltage corresponding to the current pulse according to the number of gate voltage segments, the number of pulses in each segment and the gate voltage value preset in the memory; S4, configuring the digital value of the gate voltage corresponding to the current pulse to the D / A converter, and making the D / A converter output the corresponding analog signal; S5. Complete the gate voltage adjustment of a pulse signal and return to step S1.

6. A method for adjusting unevenness of long sequence pulse output according to claim 5, characterized in that: The gate voltage regulation of a pulse signal in step S5 specifically includes the following steps: S51, enter the module debugging interface; S52. The transmitter's operating modes include ADS-B, DME, TACAN and data link, of which only the data link is in long pulse mode, so that the transmitter enters the data link mode, i.e. the gate voltage long pulse debugging mode; S53, determining the number of gate voltage segments, the number of pulses in each segment, and the gate voltage value according to the factory test curve of the power amplifier tube; S54, writing the segment number, the pulse number of each segment and the gate voltage value into the data FLASH through the debugging interface; S55, call the FLASH data according to the working mode and temperature, and automatically calculate and generate each segment of gate voltage data according to the segmented data; call the FLASH data within the temperature value range transmitted back by the temperature sensor; suppose there are M pulses in N segments, and calculate the Xth gate voltage value V in N segments according to the Nth segment gate voltage value VA and the N+1th segment gate voltage value VB: V=VA+X(VB-VA) / M; S56, if the sequence is less than 1dB, the test is qualified; if the sequence is greater than or equal to 1dB, the test is unqualified, and the process returns to step S53; S57, confirm that the debugging is qualified, and the debugging is completed.

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