Overcurrent protection circuit, driving chip and intelligent power module

Abstract

The invention discloses an overcurrent protection circuit, a driving chip and an intelligent power module wherein the overcurrent protection circuit comprises a first triode, a second triode, a sampling resistor, a first feedback resistor, a second feedback resistor, a first comparator, a second comparator, a first NOT gate, a first NAND gate and a blanking circuit. And the blanking circuit is used for eliminating noise interference of the driving chip. According to the overcurrent protection circuit, signal amplification is carried out through the first triode and the second triode at the preceding stage, then comparison is carried out through the first comparator and the second comparator, so that the comparison result is more accurate, and finally noise interference is eliminated through the blanking circuit; therefore, the condition of false triggering protection of the overcurrent protection circuit due to noise interference can be avoided.

Description

Technical Field

[0001] The present invention relates to the technical field of power modules, and in particular to an overcurrent protection circuit, a drive chip and an intelligent power module. Background Art

[0002] It is well known that the current flowing through the power tube is relatively large. If it exceeds the normal working voltage range of the driver chip, it may affect the working state of the circuit or even damage the chip. The overcurrent protection circuit can play a key protective role in this case. Its working principle is that when the current in the power tube exceeds the preset value, the circuit will immediately change the working state, thereby reducing the working current.

[0003] Most of the overcurrent protection circuits in the prior art are implemented using sampling resistors, which consume power, so the sampling resistors are relatively small. This may cause some false triggering of protection due to noise interference, often causing the driver chip to fail to work properly. Summary of the invention

[0004] The purpose of the present invention is to provide a new overcurrent protection circuit, a driving chip and an intelligent power module to solve the problem that the overcurrent protection circuit in the technology may cause false triggering of protection due to noise interference.

[0005] In order to solve the above problems, the present invention provides an overcurrent protection circuit, which is applied to a driver chip, and includes a first triode, a second triode, a sampling resistor, a first feedback resistor, a second feedback resistor, a first comparator, a second comparator, a first NOT gate, a first NAND gate, and a blanking circuit, wherein the blanking circuit is used to eliminate noise interference of the driver chip;

[0006] The base of the first transistor is connected to the first signal input terminal of the driving chip, and the collector of the first transistor is respectively connected to the working voltage and the emitter of the first transistor;

[0007] The base of the second transistor is connected to the second signal input terminal of the driving chip, and the collector of the second transistor is connected to the emitter of the first transistor and the emitter of the second transistor respectively;

[0008] The first end of the sampling resistor is connected to the emitter of the second transistor, and the second end of the sampling resistor is grounded;

[0009] The first end of the first feedback resistor is connected to the second end of the sampling resistor;

[0010] The first end of the second feedback resistor is connected to the second end of the first feedback resistor;

[0011] The positive input terminal of the first comparator is connected to the emitter of the second transistor, and the negative input terminal of the first comparator is connected to the second end of the first feedback resistor;

[0012] The positive input terminal of the second comparator is connected to the reference voltage of the driving chip, and the negative input terminal of the second comparator is connected to the output terminal of the first comparator and the second terminal of the second feedback resistor;

[0013] An input terminal of the first NOT gate is connected to an output terminal of the second comparator;

[0014] The first input end of the first NAND gate is connected to the output end of the first NAND gate, and the output end of the first NAND gate serves as the output end of the overcurrent protection circuit;

[0015] The input end of the blanking circuit is connected to the voltage input end of the driving chip, and the output end of the blanking circuit is connected to the second signal input end of the first NAND gate.

[0016] Preferably, the overcurrent protection circuit further includes a first resistor, a first end of the first resistor is connected to a first signal input end of the driving circuit, and a second end of the first resistor is connected to a base of the first transistor.

[0017] Preferably, the overcurrent protection circuit further includes a second resistor, a first end of the second resistor is connected to the second signal input end of the driving circuit, and a second end of the second resistor is connected to the base of the second transistor.

[0018] Preferably, the blanking circuit includes a second NOT gate, an inverter, a Schmitt circuit, a third NOT gate, a NOR gate, a second NAND gate and a fourth NOT gate;

[0019] The input end of the second NOT gate serves as the input end of the blanking circuit;

[0020] The input end of the inverter is connected to the output end of the second NOT gate;

[0021] The input end of the Schmitt circuit is connected to the first output end of the inverter;

[0022] The input end of the third NOT gate is connected to the output end of the Schmitt circuit;

[0023] The first input terminal of the NOR gate is connected to the output terminal of the third NOT gate, and the second input terminal of the NOR gate is connected to the output terminal of the second NOT gate;

[0024] The first input terminal of the second NAND gate is connected to the voltage input terminal of the driving chip, and the second input terminal of the second NAND gate is connected to the output terminal of the NOR gate;

[0025] The input end of the fourth NOT gate is connected to the output end of the second NAND gate, and the output end of the fourth NOT gate serves as the output end of the blanking circuit.

[0026] Preferably, the inverter includes a first field effect transistor, a second field effect transistor and a third field effect transistor;

[0027] The gate of the first field effect tube and the gate of the second field effect tube are used together as the input end of the inverter, the source of the first field effect tube is connected to the total voltage of the driving chip, the drain of the second field effect tube is connected to the drain of the first field effect tube and is used together as the output end of the blanking circuit, and the source of the second field effect tube is grounded;

[0028] The gate of the third field effect transistor is connected to the drain of the first field effect transistor, and the source of the third field effect transistor and the drain of the third field effect transistor are grounded respectively.

[0029] Preferably, the inverter also includes a third resistor, a first end of the third resistor is connected to the drain of the first field effect transistor, a second end of the third resistor is connected to the drain of the second field effect transistor; and a gate of the third field effect transistor is connected to the second end of the third resistor.

[0030] In a second aspect, the present invention provides a driver chip, which includes the overcurrent protection circuit as described above.

[0031] In a third aspect, the present invention provides an intelligent power module, which includes the driving chip as described above.

[0032] Compared with the prior art, the overcurrent protection circuit of the present invention first amplifies the signal through the first transistor and the second transistor of the previous stage, and then compares the signal through the first comparator and the second comparator, so that the comparison result can be more accurate, and finally the noise interference is eliminated through the blanking circuit, thereby avoiding the situation where the overcurrent protection circuit is falsely triggered due to noise interference. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0034] Figure 1 A circuit structure diagram of an overcurrent protection circuit provided by an embodiment of the present invention;

[0035] Figure 2A circuit structure diagram of a blanking circuit in an overcurrent protection circuit provided by an embodiment of the present invention;

[0036] Figure 3 A blanking time sequence diagram of an overcurrent protection circuit provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0037] The technical solutions in the embodiments of the present invention are described clearly and completely below. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0038] The embodiment of the present invention provides an overcurrent protection circuit, which is applied to a driver chip and is combined with Figure 1 As shown, it includes a first transistor 1, a second transistor 2, a sampling resistor 6, a first feedback resistor 7, a second feedback resistor 8, a first comparator 3, a second comparator 4, a first NOT gate 9, a first NAND gate 10 and a blanking circuit 5 (LEB), and the blanking circuit 5 is used to eliminate noise interference of the driving chip.

[0039] The base of the first transistor 1 is connected to the first signal input terminal (V H123 ), the collector of the first transistor 1 is connected to the operating voltage and the emitter of the first transistor 1 respectively.

[0040] The base of the second transistor 2 is connected to the second signal input terminal (V L123 ), the collector of the second transistor 2 is connected to the emitter of the first transistor 1 and the emitter of the second transistor 2 respectively.

[0041] A first end of the sampling resistor 6 is connected to the emitter of the second transistor 2 , and a second end of the sampling resistor 6 is grounded.

[0042] A first end of the first feedback resistor 7 is connected to a second end of the sampling resistor 6 .

[0043] A first end of the second feedback resistor 8 is connected to a second end of the first feedback resistor 7 .

[0044] The positive input terminal of the first comparator 3 is connected to the emitter of the second transistor 2 , and the negative input terminal of the first comparator 3 is connected to the second end of the first feedback resistor 7 .

[0045] The positive input terminal of the second comparator 4 is connected to the reference voltage (Vref) of the driving chip, and the negative input terminal of the second comparator 4 is connected to the output terminal of the first comparator 3 and the second end of the second feedback resistor 8 .

[0046] An input terminal of the first NOT gate 9 is connected to an output terminal of the second comparator 4 .

[0047] The first input end of the first NAND gate 10 is connected to the output end of the first NOT gate 9 , and the output end of the first NAND gate 10 serves as the output end of the overcurrent protection circuit.

[0048] The input terminal of the blanking circuit 5 is connected to the voltage input terminal (V L ), the output end of the blanking circuit 5 is connected to the second signal input end of the first NAND gate 10.

[0049] In this embodiment, the overcurrent protection circuit further includes a first resistor R1 and a second resistor R2.

[0050] The first end of the first resistor R1 is connected to the first signal input end of the driving circuit, and the second end of the first resistor R1 is connected to the base of the first transistor 1; the first end of the second resistor R2 is connected to the second signal input end of the driving circuit, and the second end of the second resistor R2 is connected to the base of the second transistor 2.

[0051] In this embodiment, the overcurrent protection circuit further includes a first diode D1 and a second diode D2.

[0052] The first diode D1 is connected in series between the collector and the emitter of the first transistor 1 , and the second diode D2 is connected in series between the collector and the emitter of the second transistor 2 .

[0053] In this embodiment, combined with Figure 2 As shown, the blanking circuit 5 includes a second NOT gate 16 , an inverter 17 , a Schmitt circuit 11 , a third NOT gate 12 , a NOR gate 13 , a second NAND gate 14 and a fourth NOT gate 15 .

[0054] An input terminal of the second NOT gate 16 serves as an input terminal of the blanking circuit 5 .

[0055] An input terminal of the inverter 17 is connected to an output terminal of the second NOT gate 16 .

[0056] An input terminal of the Schmitt circuit 11 is connected to a first output terminal of the inverter 17 .

[0057] An input terminal of the third NOT gate 12 is connected to an output terminal of the Schmitt circuit 11 .

[0058] A first input terminal of the NOR gate 13 is connected to an output terminal of the third NOT gate 12 , and a second input terminal of the NOR gate 13 is connected to an output terminal of the second NOT gate 16 .

[0059] A first input terminal of the second NAND gate 14 is connected to a voltage input terminal of the driving chip, and a second input terminal of the second NAND gate 14 is connected to an output terminal of the NOR gate 13 .

[0060] An input end of the fourth NOT gate 15 is connected to an output end of the second NAND gate 14 , and an output end of the fourth NOT gate 15 serves as an output end of the blanking circuit 5 .

[0061] In this embodiment, the inverter 17 includes a first field effect transistor P1 , a second field effect transistor P2 , and a third field effect transistor P3 .

[0062] The gate of the first field effect transistor P1 and the gate of the second field effect transistor P2 serve as the input end of the inverter 17. The source of the first field effect transistor P1 is connected to the total voltage (V REG ), the drain of the second field effect transistor P2 is connected to the drain of the first field effect transistor P1 and serves as the output end of the blanking circuit 5, and the source of the second field effect transistor P2 is grounded (GND).

[0063] The gate of the third field effect transistor P3 is connected to the drain of the first field effect transistor P1 , and the source of the third field effect transistor P3 and the drain of the third field effect transistor P3 are grounded respectively.

[0064] The inverter 17 further includes a third resistor R3, a first end of the third resistor R3 is connected to the drain of the first field effect transistor P1, a second end of the third resistor R3 is connected to the drain of the second field effect transistor P2; and a gate of the third field effect transistor P3 is connected to the second end of the third resistor R3.

[0065] Figure 2 The internal structure of the operational amplifier circuit 110 and the operational amplifier comparison internal structure circuit 120 are also included.

[0066] In this embodiment, the overcurrent protection circuit mainly includes a first comparator 3, a second comparator 4 and a blanking circuit 5. The first comparator 3 and the second comparator 4 use a differential structure, and then the function of the blanking circuit 5 is realized through a digital logic circuit; when the current of the driving chip exceeds, the output signal of the overcurrent protection circuit is a low level. When the blanking circuit 5 is a high level, the final output of the overcurrent protection circuit is a low level, and the circuit is overcurrent. At this time, the fault logic control circuit will be set to a low level, the logic signal output is a low level, the circuit is shut down, and the power tube is protected in time.

[0067] Since the sampling resistor in the prior art is relatively small, the present embodiment first uses an amplifier to amplify the sampling voltage signal (Vcs) by R3 / R2 times and then compares it with the reference voltage through the first comparator 3 to obtain an output signal (OCP1). When the circuit is normal, the sampling voltage signal is relatively small. At this time, the output signal of the first comparator 3 is at a high level, and the circuit works normally. When the current is too large, the output signal of the first comparator 3 will change from high to low, and the circuit stops working; the output of the second comparator 4 is the final signal (OCP).

[0068] The blanking circuit 5 in this embodiment is mainly to avoid the occurrence of excessive current spikes at the moment when the power tube is just turned on, thereby causing the overcurrent protection circuit to be falsely triggered. Therefore, in the period of time when the power tube is just turned on, a blanking time is set to prevent the overcurrent protection circuit from working at this time. Specifically, Figure 3 As shown, when the low-side power tube is turned on, a blanking time of Δt1 is set at the beginning of the conduction time Δt. At this time, the output LEB of the blanking circuit 5 is low level. At Δt2, the overcurrent protection circuit is falsely triggered, and the OCP1 output is low level. However, due to the blanking time, the overcurrent does not work and the output is still high. After Δt1, when the overcurrent occurs at Δt3, OCP is low level. Only when OCP1 and LED are high level at the same time, OCP output is low level, and the circuit is protected from overcurrent. The blanking time of this embodiment is designed to be 200ns, which can improve the reliability of the circuit.

[0069] Compared with the prior art, the overcurrent protection circuit of this embodiment first amplifies the signal through the first transistor 1 and the second transistor 2 of the previous stage, and then compares the signal through the first comparator 3 and the second comparator 4, so that the comparison result can be more accurate, and finally the blanking circuit 5 eliminates noise interference, thereby avoiding the overcurrent protection circuit from falsely triggering protection due to noise interference.

[0070] In addition, the present invention also provides an embodiment of a driver chip, which includes the overcurrent protection circuit in the above embodiment. Since the driver chip in this embodiment includes the overcurrent protection circuit in the above embodiment, it can also achieve the technical effect achieved by the overcurrent protection circuit in the above embodiment, which will not be described in detail here.

[0071] The present invention also provides an embodiment of an intelligent power module, which includes the driver chip in the above embodiment. Since the intelligent power module in this embodiment includes the driver chip in the above embodiment, it can also achieve the technical effect achieved by the driver chip in the above embodiment, which will not be described in detail here.

[0072] The above descriptions are merely embodiments of the present invention and are not intended to limit the patent scope of the present invention. Any equivalent structure or equivalent process transformation made using the contents of the present invention specification and drawings, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present invention.

Claims

1. An overcurrent protection circuit, applied to a driver chip, characterized in that: The overcurrent protection circuit includes a first transistor, a second transistor, a sampling resistor, a first feedback resistor, a second feedback resistor, a first comparator, a second comparator, a first NOT gate, a first NAND gate and a blanking circuit, and the blanking circuit is used to eliminate noise interference of the driving chip; The base of the first transistor is connected to the first signal input terminal of the driving chip, and the collector of the first transistor is respectively connected to the working voltage and the emitter of the first transistor; The base of the second transistor is connected to the second signal input terminal of the driving chip, and the collector of the second transistor is connected to the emitter of the first transistor and the emitter of the second transistor respectively; The first end of the sampling resistor is connected to the emitter of the second transistor, and the second end of the sampling resistor is grounded; The first end of the first feedback resistor is connected to the second end of the sampling resistor; The first end of the second feedback resistor is connected to the second end of the first feedback resistor; The positive input terminal of the first comparator is connected to the emitter of the second transistor, and the negative input terminal of the first comparator is connected to the second end of the first feedback resistor; The positive input terminal of the second comparator is connected to the reference voltage of the driving chip, and the negative input terminal of the second comparator is connected to the output terminal of the first comparator and the second terminal of the second feedback resistor; An input terminal of the first NOT gate is connected to an output terminal of the second comparator; The first input end of the first NAND gate is connected to the output end of the first NAND gate, and the output end of the first NAND gate serves as the output end of the overcurrent protection circuit; The input end of the blanking circuit is connected to the voltage input end of the driving chip, and the output end of the blanking circuit is connected to the second signal input end of the first NAND gate.

2. The overcurrent protection circuit according to claim 1, characterized in that: The overcurrent protection circuit further includes a first resistor, a first end of the first resistor is connected to a first signal input end of the driving circuit, and a second end of the first resistor is connected to a base of the first transistor.

3. The overcurrent protection circuit according to claim 2, characterized in that: The overcurrent protection circuit further includes a second resistor, a first end of the second resistor is connected to the second signal input end of the driving circuit, and a second end of the second resistor is connected to the base of the second transistor.

4. The overcurrent protection circuit according to claim 1, characterized in that: The blanking circuit includes a second NOT gate, an inverter, a Schmitt circuit, a third NOT gate, a NOR gate, a second NAND gate and a fourth NOT gate; The input end of the second NOT gate serves as the input end of the blanking circuit; The input end of the inverter is connected to the output end of the second NOT gate; The input end of the Schmitt circuit is connected to the first output end of the inverter; The input end of the third NOT gate is connected to the output end of the Schmitt circuit; The first input terminal of the NOR gate is connected to the output terminal of the third NOT gate, and the second input terminal of the NOR gate is connected to the output terminal of the second NOT gate; The first input terminal of the second NAND gate is connected to the voltage input terminal of the driving chip, and the second input terminal of the second NAND gate is connected to the output terminal of the NOR gate; The input end of the fourth NOT gate is connected to the output end of the second NAND gate, and the output end of the fourth NOT gate serves as the output end of the blanking circuit.

5. The overcurrent protection circuit according to claim 4, characterized in that: The inverter includes a first field effect transistor, a second field effect transistor and a third field effect transistor; The gate of the first field effect tube and the gate of the second field effect tube are used together as the input end of the inverter, the source of the first field effect tube is connected to the total voltage of the driving chip, the drain of the second field effect tube is connected to the drain of the first field effect tube and is used together as the output end of the blanking circuit, and the source of the second field effect tube is grounded; The gate of the third field effect transistor is connected to the drain of the first field effect transistor, and the source of the third field effect transistor and the drain of the third field effect transistor are grounded respectively.

6. The overcurrent protection circuit according to claim 5, characterized in that: The inverter also includes a third resistor, a first end of the third resistor is connected to the drain of the first field effect transistor, a second end of the third resistor is connected to the drain of the second field effect transistor; and a gate of the third field effect transistor is connected to the second end of the third resistor.

7. A driver chip, characterized in that: The driving chip includes the overcurrent protection circuit as described in any one of claims 1 to 6.

8. An intelligent power module, characterized in that: The intelligent power module comprises the driving chip as claimed in claim 7.

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