Low-power-consumption capacitance-to-digital converter based on SAR logic and coarse-fine binary counter

Abstract

The invention discloses a low-power-consumption capacitance digital converter based on SAR (Synthetic Aperture Radar) logic and a coarse-fine binary counter, and relates to a low-power-consumption capacitance digital converter. The invention aims to solve the problem that a micro capacitance measuring circuit cannot meet the requirements of large dynamic range, low noise and good spurious resistance. The system comprises an ultra-low power consumption relaxation oscillator, an asynchronous tracking algorithm circuit, a coarse-fine binary counter, a bootstrap switch circuit and a fully differential SAR logic capacitance digital-to-analog converter. The ultra-low power consumption relaxation oscillator is used for generating a clock signal Scan, and the clock signal Scan is an input signal of the asynchronous tracking algorithm circuit, the coarse and fine binary counter and the bootstrap switch circuit; the asynchronous tracking algorithm circuit is used for generating a clock signal Valid, and the clock signal Valid is a clock signal of the coarse and fine binary counter; and the coarse and fine binary counter is used for generating a control signal of the fully differential SAR logic capacitance digital-to-analog converter and controlling a switch time sequence. The invention belongs to the technical field of analog-to-digital conversion and capacitive sensor interface circuits.

Description

Technical Field

[0001] The invention relates to a low-power consumption capacitance-to-digital converter, belonging to the technical field of analog-to-digital conversion and capacitance sensor interface circuits. Background Art

[0002] Using capacitance characteristics to detect physical quantities is widely used in industrial process control, measurement and instrumentation systems. Although different application types have different performance requirements for sensor interface circuits, people have been committed to improving the energy efficiency of interface circuits. The CDC proposed in this paper is applied to unattended ZC sensing systems. The sound sensor frequency of 200-2kHz and the vibration sensor frequency of 50Hz can be equivalent to variable capacitors. Their capacitance values ​​change with the detected signal frequency. CDC can measure the capacitance values ​​of these sensors, and their frequency values ​​can be further obtained through output. Finally, the digital code stream is output and wirelessly transmitted to the host computer.

[0003] Since capacitive sensors do not consume static power, the power consumption of the capacitive sensing system will be limited by the readout circuit, which is usually a capacitance-to-digital converter (CDC). For use in watchdog circuits, ultra-low power readout circuits are required. In nW-class wireless sensor nodes used in bio-implanted telemetry, smart healthcare, panel control, and environmental monitoring, ultra-low power consumption is required to achieve high functionality for the system, especially for wearable devices and handheld applications. Currently, this design application still faces challenges.

[0004] Because digital systems have better user interfaces and superior signal processing capabilities compared to analog systems, the latest trend in capacitive sensing interface circuits is to directly digitize the sensor capacitance rather than converting the capacitance to a voltage and then digitizing the output voltage. Direct digitization has lower complexity, smaller area, and lower power consumption; in the "semi-digital" approach, the capacitance can be used to modulate the period or pulse width of the digital signal; however, this approach requires a time-to-digital converter to provide a digital output code, such as a fast digital counter and a stable high-frequency oscillator, which prevents its use in low-power applications.

[0005] A more attractive approach to capacitance-to-digital conversion (CDC) is to use a ΔΣ modulator; however, the oversampling and digital decimation filtering required by the ΔΣ architecture results in significant power consumption; in addition, the ΔΣ interface has a limited capacitance range and cannot avoid modulator overload; to increase the capacitance range of the ΔΣ interface circuit, a successive approximation register (SAR) algorithm has been proposed to adjust the modulator reference capacitance; however, the SAR step is only used for initial coarse calibration, while sensor digitization is still performed using a ΔΣ modulator.

[0006] The capacitance-to-digital converter (CDC) architecture that relies entirely on the SAR algorithm does not require oversampling, which effectively reduces power consumption and relaxes the requirements for analog blocks; in addition, the digital output code can be provided directly without digital filtering, further reducing power consumption. The successive approximation register (SAR) analog-to-digital converter (ADC) is considered to be an ideal architecture for biomedical signal processing systems due to its small area and low power consumption; however, with the advancement of technology and the reduction of power supply voltage, it is challenging to extend these advantages to high-resolution designs due to the limitation of excessive power dissipation of the capacitance-to-digital converter (CDAC), which has attracted great attention from industry and academia.

[0007] In addition, the capacitance-to-digital converter must also be stable against external interference to limit the occurrence of power consumption detection errors. The capacitance change of micro-capacitance sensors is often very small, making the influence of cable stray capacitance very obvious; and stray capacitance will change with many factors such as temperature, structure, position, internal and external electric field distribution and device selection, and the measured capacitance has a large range of variation; therefore, the micro-capacitance measurement circuit must meet the requirements of large dynamic range, low noise, and good anti-stray performance. Summary of the invention

[0008] The present invention solves the problem that a tiny capacitance measurement circuit cannot meet the requirements of large dynamic range, low noise and good anti-spurious performance, and further proposes a low-power capacitance-to-digital converter based on SAR logic and a coarse-fine binary counter.

[0009] The technical solution adopted by the present invention to solve the above problems is: the present invention includes an ultra-low power consumption relaxation oscillator, an asynchronous tracking algorithm circuit, a coarse-fine binary counter, a bootstrap switch circuit and a fully differential SAR logic capacitor digital-to-analog converter;

[0010] The ultra-low power relaxation oscillator is used to generate a clock signal Scan, which is an input signal of an asynchronous tracking algorithm circuit, a coarse-fine binary counter and a bootstrap switch circuit;

[0011] The asynchronous tracking algorithm circuit is used to generate a clock signal Valid, and the clock signal Valid is a clock signal of a coarse and fine binary counter;

[0012] The coarse and fine binary counter is used to generate the control signal of the fully differential SAR logic capacitor digital-to-analog converter and control the switching timing.

[0013] Furthermore, the ultra-low power relaxation oscillator includes a nanoampere-level reference generation circuit, a low power comparator, a T trigger, and a trimming circuit;

[0014] One end of the low power comparator is connected to the charging capacitor C INT Connect the other end of the low power comparator to V REF connect;

[0015] The current I of the nanoampere bandgap reference generation circuit REF The charging capacitor C INT Charging, the charging capacitor C INT The rising slope is The voltage V INT , when V INT >V REF The comparator periodically resets V INT ;

[0016] The Scan clock signal period is

[0017] The low power comparator uses a low power comparator structure with a high threshold device, a secondary open-loop operational amplifier, a cascade inverter and a latch. REF Represents the reference voltage output by the nanoampere-level reference generation circuit.

[0018] Furthermore, the nanoampere-level reference generation circuit uses self-cascaded NMOS transistors instead of resistors.

[0019] Furthermore, the asynchronous tracking algorithm circuit includes a low noise dynamic comparator, a self-oscillating loop and a reset logic.

[0020] Furthermore, the coarse-fine binary counter uses a combination of a 4-bit coarse CDAC and an 8-bit fine CDAC to optimize the switching timing.

[0021] Furthermore, the bootstrap switch circuit is a 10-tube structure.

[0022] Furthermore, the fully differential SAR logic capacitor digital-to-analog converter includes a 12-bit fully differential capacitor array, a charge injection cancellation switch, a reset switch, and a pull-up switch.

[0023] The beneficial effects of the present invention are:

[0024] Compared with other capacitance-to-digital converters, the 12-bit SAR algorithm proposed in the present invention uses a coarse-fine capacitor array to be executed in the capacitance domain, so that a wide range of capacitance can be digitized in a compact area, effectively reducing circuit power consumption while achieving high-precision measurement, and the lowest power consumption can reach nW level;

[0025] The present invention adopts an asynchronous tracking algorithm to periodically trigger the CDC through an ultra-low power relaxation oscillator to achieve power consumption that is consistent with the conversion frequency;

[0026] The present invention adopts a differential architecture and intrinsic CDS sampling, is insensitive to charge injection and offset voltage, and is resistant to noise coupling;

[0027] Compared with the traditional capacitance detection circuit, the coarse-fine binary counter of the present invention effectively reduces the system power consumption, so that the power consumption can reach the nW level. The power consumption depends on the frequency of capacitance digitization in the application scenario. In the absence of capacitance conversion events, the power consumption can be ignored. Secondly, the circuit has strong anti-interference ability to common-mode noise and external interference caused by capacitance detection. Finally, it has high measurement accuracy and the resolution can reach 12 bits. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 It is the overall logic block diagram of the capacitance digital converter;

[0029] Figure 2 It is a schematic diagram of an ultra-low power relaxation oscillator;

[0030] Figure 3 It is a schematic diagram of a low power comparator in an ultra-low power relaxation oscillator;

[0031] Figure 4 It is the circuit diagram of asynchronous tracking algorithm;

[0032] Figure 5 It is a schematic diagram of a low noise dynamic comparator in an asynchronous tracking algorithm circuit;

[0033] Figure 6 is a schematic diagram of a coarse enable signal generating circuit of a coarse-fine binary counter;

[0034] Figure 7 This is a schematic diagram of the bootstrap switch circuit. DETAILED DESCRIPTION

[0035] Specific implementation method 1: Figures 1 to 7 As shown, a low-power capacitance-to-digital converter based on SAR logic and coarse-fine binary counter includes an ultra-low power relaxation oscillator 101, an asynchronous tracking algorithm circuit 102, a coarse-fine binary counter 103, a bootstrap switch circuit 104 and a fully differential SAR logic capacitance digital-to-analog converter 105;

[0036] The ultra-low power relaxation oscillator 101 is used to generate a clock signal Scan, which is an input signal of the asynchronous tracking algorithm circuit 102, the coarse and fine binary counter 103 and the bootstrap switch circuit 104;

[0037] The asynchronous tracking algorithm circuit 102 is used to generate a clock signal Valid, which is a clock signal of a coarse and fine binary counter 103;

[0038] The coarse and fine binary counter 102 is used to generate a control signal of the fully differential SAR logic capacitance digital-to-analog converter 105 and control the switching timing.

[0039] The input capacitor to be measured is connected to one end of the fully differential CDAC, and after the capacitance changes, it is converted into a digital signal by the CDAC.

[0040] Specific implementation method 2: Figures 1 to 7 As shown, the ultra-low power relaxation oscillator 101 includes a nanoampere-level reference generation circuit, a low-power comparator, a T trigger, and a trimming circuit;

[0041] One end of the low power comparator is connected to the charging capacitor C INT Connect the other end of the low power comparator to V REF connect;

[0042] Current I of the nanoampere bandgap reference generation circuit REF The charging capacitor C INT Charging, the charging capacitor C INT The rising slope is The voltage V INT , when V INT >V REF The comparator periodically resets V INT ;

[0043] The Scan clock signal period is

[0044] The low power comparator uses a low power comparator structure with a high threshold device, a secondary open-loop operational amplifier, a cascade inverter and a latch. REF Represents the reference voltage output by the nanoampere-level reference generation circuit.

[0045] Specific implementation method three: Figures 1 to 7 As shown, the nano-ampere level reference generation circuit uses self-cascaded NMOS transistors instead of resistors.

[0046] According to the relationship between the output reference voltage and the current, the influence of temperature on the bandgap reference is further reduced.

[0047] Specific implementation method four: Figures 1 to 7 As shown, the asynchronous tracking algorithm circuit 102 includes a low noise dynamic comparator, a self-oscillating loop and a reset logic.

[0048] Among them, dynamic logic enables the CDC to use the digital output stored in the previous conversion cycle as the starting point and update its digital output only when the capacitance changes;

[0049] The self-oscillating loop formed by the delay between the comparator clock signal and the comparator enable signal (approximately 30ns) provides the clock signal for the comparator and the counter;

[0050] The output of the comparator is connected to a D flip-flop to generate a Finish signal. The Finish signal controls the CDC to stop converting only after the output of the comparator changes its sign three times.

[0051] When the self-oscillation loop outputs 12 clock cycles and completes the comparison, the reset logic immediately turns off the self-oscillation loop to ensure that the power consumption of the CDC is negligible when there is no touch event. By comparison, it can be seen that the conventional SAR CDC has power consumption limitations: even if the input capacitance of the capacitive sensor has not changed, the complete SAR algorithm needs to be executed in each conversion cycle. If the capacitance to be measured has not changed, the corresponding SAR cycle is unnecessary, consuming unnecessary power.

[0052] Specific implementation method five: Figures 1 to 7 As shown, the coarse-fine binary counter 102 uses a combination of a 4-bit coarse CDAC and an 8-bit fine CDAC to optimize the switching timing.

[0053] Each time the capacitance is converted, the voltage is first compared through the 8-bit fine CDAC. When the capacitance change ΔC exceeds the comparison range of the 8-bit fine CDAC, the 4-bit coarse CDAC starts to work, thereby reducing the mid-code conversion caused by small changes in the sensor capacitance, greatly reducing circuit power consumption, and achieving high-precision detection.

[0054] Specific implementation method six: Figures 1 to 7 As shown, the bootstrap switch circuit 104 is a 10-transistor structure.

[0055] Among them, the 10-tube structure adopts deep N-well technology, the size of all MOS tubes is kept small, and the size of the switch tube is kept large. The enable signal is connected to the gate terminal of Ms after passing through the AND gate operation circuit, and the bootstrap switch circuit is turned off during the non-capacitive conversion period, thereby effectively reducing the system power consumption.

[0056] Specific implementation method seven: Figures 1 to 7 As shown, the fully differential SAR logic capacitor digital-to-analog converter 105 includes a 12-bit fully differential capacitor array, a charge injection cancellation switch, a reset switch, and a pull-up switch.

[0057] Among them, a capacitor array with optimized switching timing is used, that is, a combination of 8-bit fine CDAC and 4-bit coarse CDAC. The fully differential structure has a strong anti-interference ability against common-mode interference and external input noise (i.e., external interference coupled into the sensor through touch events);

[0058] CDAC digital output corresponds to the analog value V OUT By formula The calculation results are: C0 is the capacitance at the last moment, ΔC is the capacitance change to be measured, and C SARis the total capacitance of the 12-bit capacitor array.

[0059] Example

[0060] like Figure 2 As shown in , the ultra-low power relaxation oscillator 101 is composed of a nanoampere-level reference generation circuit, a low-power comparator, a T trigger, a delay circuit, and a charging capacitor;

[0061] C1 and C2 are trimming capacitors. By controlling M1 and M2, the value of the charging capacitor can be changed, thereby changing the frequency of the clock signal Scan. The output V OUT It is a short pulse with a very low duty cycle. It may not trigger the CDC accurately due to the low duty cycle. In order to increase the duty cycle of the short pulse, the low-power comparator is followed by a T flip-flop (TFF), which will generate a stable clock with a 50% duty cycle. At the same time, an inverter chain is connected after the T flip-flop to obtain a clock with a steep edge.

[0062] When working, the current I generated by the nano-ampere reference generation circuit REF C INT Charging at C INT The rising slope is The voltage V INT , when V INT >V REF The comparator periodically resets V INT The generated Scan clock signal period is The I output of the nano-ampere reference generation circuit REF and V REF They have similar temperature characteristics, so the oscillation frequency is less affected by temperature, which improves the stability of the oscillator circuit;

[0063] like Figure 3 As shown in , this part of the low-power comparator consists of a two-stage preamplifier, an inverter chain and a latch module. All devices of the low-power comparator use high-threshold devices to achieve low operating current and low leakage. At the same time, a PMOS input pair is used, and the comparator works under a low input common-mode voltage.

[0064] The specific connection method is as follows, where M1, M2, M3, M6, M8, M10, and M12 are PMOS tubes, and M4, M5, M7, M9, M11, and M13 are NMOS tubes:

[0065] The gates of M2 and M3 are used as positive and negative inputs Vref and Vint, the source of M2 and M3 are connected to the drain of M1, the drain of M2 is connected to the drain of M4, the drain of M3 is connected to the drain of M5, except for M2 and M3, the source of all PMOS tubes is connected to the highest potential Vdd, the source of all NMOS tubes is grounded, the gate of M1 is used as bias input Vbias, the drain of M4 is connected to the gate, and the gate of M5 is connected, the gate of M6 is connected to V Bias, the drain of M6 is connected to the drain of M7, the gate of M7 is connected to the drain of M5, the gate of M8 is connected to the drain of M7, the drain of M8 is connected to the drain of M9, the gate of M9 is connected to the drain of M7, the gate of M10 is connected to the drain of M9, the drain of M10 is connected to the drain of M11, the gate of M11 is connected to the drain of M9, the gate of M12 is connected to the drain of M11, the drain of M12 is connected to the drain of M13, and the gate of M13 is connected to the drain of M11. The substrates of all PMOS tubes are connected to the highest potential Vdd, and the substrates of NMOS tubes are grounded.

[0066] like Figure 4 As shown in , the asynchronous tracking algorithm circuit 102 is composed of a low-noise dynamic comparator, a self-oscillating loop, and a reset logic;

[0067] The asynchronous tracking algorithm is mainly used to greatly reduce static power consumption and use fewer MOS tubes. Conventional SAR CDC has power consumption limitations: even if the input capacitance of the capacitive sensor has not changed, the complete SAR algorithm needs to be executed in each conversion cycle. If the capacitance to be measured has not changed, the corresponding SAR cycle is unnecessary, consuming unnecessary power. This patent proposes a more efficient algorithm. The dynamic logic enables the CDC to use the digital output stored in the previous conversion cycle as the starting point and update its digital output only when the capacitance changes. Under the condition of the same power consumption, higher capacitance-to-digital conversion accuracy can be achieved;

[0068] First, the two output voltages Vs1 and Vs2 of the fully differential CDAC are used as the positive and negative input terminals of the dynamic comparator respectively. The comparison result output by the comparator is connected to the inverter chain and input into the coarse-fine binary counter. After that, the self-oscillation loop formed based on the delay (about 30ns) between the comparator clock signal and the delay signal generates the clock signal Valid, which is then used as the clock signal of the coarse-fine binary counter. The self-oscillation loop includes two delay modules (Delay1 and Delay2), which are inserted into the self-oscillation loop as an inverter chain to increase the steepness of the generated clock edge and improve the conversion rate.

[0069] Delay1 is designed to provide a delay of about 3ns to meet the requirements of the logic that generates the Finish signal. Delay2 can provide a delay of about 12ns required to ensure that the CDAC is stable. When the Finish signal is low, the self-oscillation loop works to provide a clock signal for the comparator and counter. In order to minimize wrong decisions to save power and improve conversion accuracy, the Finish signal stops the entire system from converting only after the comparator output changes sign three times;

[0070] like Figure 5 As shown in , the low noise dynamic comparator differential input will be amplified by two gain stages before driving the latch, thereby reducing the total input reference noise and offset of the latch and improving the capacitance conversion accuracy; its working principle is as follows:

[0071] After the rising edge of the clock, the voltage at the Di node decreases at a rate that depends on the input voltage. At t=t0, Gm1 amplifies the differential input, and the outputs of Gm1 (Di+ and Di-) ​​are connected to the Gm2 pair and further amplify the differential input. The output is then latched by the latch. The noise of the first-stage amplifier circuit can be expressed as: Since flicker noise is much smaller than thermal noise, the main source of noise comes from the first item. In order to reduce the equivalent input noise of the first-stage amplification, the transconductance of the comparator input to the tube must be large enough;

[0072] The specific structure of the low-noise dynamic comparator used in this part of the circuit is as follows: the comparator consists of a two-stage pre-amplifier Gm1, Gm2 and a regenerative latch, and the specific connection method is as follows: (where M4, M5, M6, M7, M10, M12 are PMOS tubes, and M1, M2, M3, M8, M9, M11, M13, M14, M15 are NMOS tubes): the gate terminals of M3, M4 and M5 serve as the clock CLK input terminals, the source terminal of M3 is grounded, the drain terminal of M3 is connected to the source terminals of M1 and M2, the drain terminal of M4 is connected to the drain terminal of M1, the source terminal of M4 is connected to the highest potential Vdd, the drain terminal of M5 is connected to the drain terminal of M2, the source terminal of M5 is connected to the highest potential Vdd, the gate terminals of M1 and M2 are used as Gm1 input Vp and Vn respectively, the gate terminal of M6 is connected to the drain terminal of M1, and the drain terminal of M6 is connected to M The drain terminal of M8 is connected to the highest potential Vdd, the source terminal of M6 is connected to the highest potential Vdd, the gate terminal of M7 is connected to the gate terminal of M14, the drain terminal of M7 is connected to the drain terminal of M14, the source terminal of M7 is connected to the highest potential Vdd, the gate terminal of M8 is connected to the gate terminal of M6, the source terminal of M8 is grounded, the gate terminal of M9 is connected to the gate terminal of M8, the drain terminal of M9 is connected to the drain terminal of M10, the source terminal of M9 is grounded, the source terminal of M10 is connected to the drain terminal of M6, and the gate terminal of M10 is connected to the drain terminal of M6. The gate terminal is connected to the gate terminal of M11, the drain terminal of M11 is connected to the drain terminal of M10, the source terminal of M11 is grounded, the gate terminal of M12 is connected to the gate terminal of M13, the source terminal of M12 is connected to the drain terminal of M14, the drain terminal of M12 is connected to the drain terminal of M13, the source terminal of M13 is grounded, the source terminal of M14 is grounded, the gate terminal of M15 is connected to the gate terminal of M14, the drain terminal of M15 is connected to the drain terminal of M13, and the source terminal of M15 is grounded. The substrates of all PMOS tubes are connected to the highest potential Vdd, and the substrates of NMOS tubes are all grounded.

[0073] like Figure 1 As shown in , the coarse and fine binary counter 103 is implemented by a logic control circuit, which is mainly used to generate a control signal of a charge injection cancellation switch in a fully differential SAR CDAC circuit;

[0074] In a conventional SAR CDAC, if the complete SAR algorithm is always executed, that is, each capacitor in the capacitor array has switching activities that consume power, especially during the mid-code conversion of the CDAC, a large amount of energy will be consumed. In order to avoid this situation, the CDAC proposed in the present invention is implemented as a combination of an 8-bit coarse CDAC and a 4-bit fine CDAC; a coarse and fine binary counter is used to generate a corresponding switch control signal to achieve V S1 and V S2 First, the 8-bit fine CDAC rises. If V S1 and V S2 The difference exceeds the range of the 8-bit fine CDAC, and then rises through the 4-bit coarse CDAC, eventually making V S1 =V S2 ; Therefore, when the capacitance change is small In one SAR cycle, only 8 small capacitors in the capacitor array consume current. For such fine conversion, this technology reduces the maximum CDAC capacitance conversion power consumption by about 16 times.

[0075] The coarse-fine binary counter is composed of n D flip-flops and a coarse enable signal generating circuit. First, the clock signal Valid generated by the asynchronous tracking algorithm circuit is used as the clock input of the D flip-flop, and the clock signal Scan generated by the relaxation oscillator is used as the reset signal of the D flip-flop to generate 13 clock signals CLK1-CLK13, wherein CLK13 is used to reset the asynchronous tracking algorithm circuit. After CDAC completes the comparison of 12 clock cycles, the self-oscillation loop in the asynchronous tracking algorithm is closed in time to achieve the purpose of reducing power consumption. When the next comparison starts, the self-oscillation loop is re-triggered; then the clock signals CLK1-CLK12 are used as the clock of the D flip-flop, and the comparator output result in the asynchronous tracking algorithm circuit is used as the input of the D flip-flop to generate the switch control signal in CDAC; at the same time, the Scan signal is used as the clock and set signal of the D flip-flop, and the generated CDAC switch control signal is used as the input of the D flip-flop, and finally a 12-bit digital output signal is generated, i.e., the final digital output of the circuit;

[0076] In order to realize the coarse and fine binary counter, a coarse enable signal generating circuit is designed, such as Figure 6 As shown in , it is composed of NOR gate logic, AND gate logic, OR gate logic, delay module and D flip-flop;

[0077] The switch control signal of the 8-bit fine CDAC is used as the input of the coarse enable signal generating circuit. After passing through the NOR operation circuit and the AND gate operation circuit, the output signal is further operated by the OR gate. The output signal of the OR gate is used as the input of the D flip-flop. The clock signal CLK8 is used as the clock signal of the D flip-flop after passing through the delay module Delay, thereby generating a coarse enable signal, which makes the capacitance change amount , the 4-bit coarse CDAC starts working.

[0078] like Figure 1 As shown, the bootstrap switch circuit (104) is mainly used to increase the gate voltage of the switch tube and improve the sampling linearity. After Vs1 and Vs2 are reset and pulled up, the switch tube in the bootstrap switch circuit transmits the change of Vs1 caused by the change of the capacitance to be measured to the capacitor array for comparison;

[0079] When the clock signal CLK is at a low level, the capacitor C1 is charged to the highest potential Vdd, at which time M4 and M9 are turned off; when CLK jumps to a high level, M4 and M9 are turned on. Since the voltage across the capacitor cannot suddenly change, the V GS is clamped to Vdd, i.e. V G=V IN +Vdd ensures that Vs1 can be fully transmitted to the capacitor array. The bootstrap switch circuit uses a deep N-well process, the size of all MOS tubes is kept small, the size of the transmission tube is kept large, and C1 should be much larger than the parasitic capacitance;

[0080] At the same time, the output of M4 and the enable signal are connected to the gate of Ms through the AND gate operation circuit; the specific connection method of this part of the circuit is as follows (where M1, M3, and M4 are PMOS tubes, and M2, M5, M6, M7, M8, M9, and M10 are NMOS tubes): the source end of the sampling switch tube Ms is used as the input Vin, the drain end of Ms is used as the output Vout, the gate end of Ms is connected to the output of the AND gate operation circuit, the gate end of M1 is connected to the clock signal CLK, the source end of M1 is connected to the highest potential Vdd, the drain end of M1 is connected to the drain end of M2, the gate end of M2 is connected to the clock signal CLK, the source end of M2 is connected to the drain end of M7, and the gate end of M3 is connected to the gate end of M4. The drain of M4 is connected to the drain of M3, the source of M3 is connected to the highest potential Vdd, the drain of M3 is connected to one end of capacitor C1, the gate of M4 is connected to the drain of M8, the source of M4 is connected to the drain of M3, the drain of M4 is connected to the source of M5, the gate of M5 is connected to the highest potential Vdd, the drain of M5 is connected to the source of M6, the gate of M6 is connected to the clock signal CLKb, the drain of M6 is grounded, the gate of M7 is connected to CLKb, the source of M7 is grounded, the gate of M8 is connected to the drain of M4, the source of M8 is connected to the drain of M7, the gate of M9 is connected to the gate of Ms, the source of M9 is connected to the source of M8, and the drain of M9 is connected to the source of Ms. The substrates of all NMOS except Ms are grounded, the substrates of all PMOS are connected to the highest potential Vdd, and the substrate of Ms is connected to the input Vin.

[0081] like Figure 1 As shown, the fully differential SAR logic capacitor digital-to-analog converter 105 is composed of a reset and pull-up switch, a charge injection cancellation switch, and a 12-bit fully differential capacitor array;

[0082] A capacitor array with optimized switching timing is used, i.e., a combination of an 8-bit fine CDAC and a 4-bit coarse CDAC. First, at the beginning of each conversion, Vs1 and Vs2 are reset to zero potential through the reset switch, and then the voltage on the capacitor to be measured, Vs1 and Vs2, is pulled up to Vdd through the bootstrap switch. Since the lower limit of the common-mode input range of the comparator in the asynchronous tracking algorithm circuit is determined by the threshold voltage of the NMOS, the pull-up function ensures that Vs1 and Vs2 are within the common-mode range even under large changes in sensor capacitance. Assume that C0 is the capacitance at the previous moment, ΔC is the capacitance change to be measured, and C SAR is the total capacitance of the 12-bit capacitor array. After reset and pull-up, the total charge on the upper half of CDAC is (C0+C SAR)Vdd, then the capacitor to be tested changes, the gate voltage bootstrap switch circuit is turned on, so that the voltage change caused by the capacitor to be tested is transmitted to the 12-bit capacitor array in CDAC, which causes the change of Vs1. Finally, Vs1 and the voltage Vc on the capacitor to be tested change to the same value Vout. Vout and Vs2 are first compared through the 8-bit fine CDAC. When the total charge is kept constant, the total charge of the upper part of CDAC is (C0+C SAR +ΔC)Vout=(C0+C SAR )Vdd;

[0083] In summary, the analog value V corresponding to the CDAC digital output OUT By formula The calculation can be obtained; in addition, the fully differential structure has a strong anti-interference ability to common-mode interference and external input noise (i.e., external interference coupled to the sensor through touch events). Due to the mismatch between capacitors, a small part of the external environment interference will still appear as a differential voltage, but in practical applications, this mismatch interference can be ignored; and since the asynchronous tracking algorithm is only sensitive to the change of the capacitance to be measured in a short period of time and can suppress low-frequency interference, it can greatly reduce the impact of external interference; the capacitor switch in the CDAC uses a charge injection offset switch. At the moment the switch is disconnected, the MOS device will generate a channel charge injection error when working, introducing noise. In order to reduce noise and improve the accuracy of capacitor detection, a charge injection offset switch is used;

[0084] like Figure 7 As shown in , the structure of the charge injection cancellation switch in this part of the circuit is as follows: The charge injection cancellation switch is composed of CMOS transmission gates, and the specific connection method is as follows (wherein M1, M2, and M3 are PMOS transistors, and M4, M5, and M6 are NMOS transistors): the source end of M1 is used as the input end Vin, the gate end of M1 is connected to the switch control signal S, the drain end of M1 is connected to the source end of M1, the gate end of M2 is connected to the switch control signal S~, the source end of M2 is connected to the drain end of M1, and the drain end of M2 is connected The source of M3 and the gate of M3 are connected to the control signal S, the drain of M3 is connected to the source of M3, the gate of M4 is connected to the control signal S~, the drain of M4 is used as the input Vin, the source of M4 is connected to the drain of M4 and the drain of M1, the gate of M5 is connected to the control signal S, the drain of M5 is connected to the source of M4, the source of M5 is connected to the drain of M6, the gate of M6 is connected to the control signal S~, the drain of M6 is connected to the source of M6 and the source of M3 as the output Vout. The substrates of all PMOS tubes are connected to the highest potential Vdd, and the substrates of all NMOS tubes are grounded.

[0085] How it works

[0086] The present invention converts the changing capacitance to be measured into a 12-bit digital output, and its corresponding analog quantity is V OUT , capacitance change and V OUT The relationship is: Where C0 is the capacitance at the last moment, ΔC is the capacitance change to be measured, and CSAR is the total capacitance of the 12-bit capacitor array. When the circuit starts working, each capacitor may have a weak residual charge, which will cause a large error in the experimental results. Therefore, at the beginning of each conversion, V S1 and V S2 First reset to zero level, then pulled up to V by the bootstrap switch DD After completing the reset and pull-up, the bootstrap switch transmits the input voltage change caused by the capacitance change to the capacitor array. Since the lower limit of the common-mode input range of the comparator is defined by the threshold voltage of the NMOS device, the pull-up function implemented by the bootstrap switch ensures that V S1 and V S2 Always within the common mode range of the comparator, thereby expanding the capacitance detection range. In the SAR CDAC with conventional switching timing, the complete SAR algorithm is executed in each conversion cycle, that is, each capacitor in the capacitor array consumes current, even if the capacitance of the sensor has not changed. Therefore, the corresponding SAR cycle is unnecessary and the power consumption of the circuit is increased. The asynchronous tracking algorithm module and the coarse and fine binary counter proposed in this circuit respectively make V S1 and V S2 First, the 8-bit fine CDAC rises. If V S1 and V S2 The difference exceeds the range of the 8-bit fine CDAC, and then rises through the 4-bit coarse CDAC, eventually making V S1 =V S2 Therefore, when the capacitance change is small In one SAR cycle, only 8 small capacitors in the capacitor array consume current, which effectively reduces power consumption. The asynchronous tracking algorithm circuit also generates an output signal (Finish) to output the digital code latched by the CDAC control logic. In the next conversion device, the counter will load the previous code and perform an increment calculation to make V S1 =V S2 Therefore, CDC works only when ΔC changes. This fine conversion greatly reduces the power consumption of the circuit and improves the accuracy of CDC. After completing a capacitance conversion, the coarse and fine binary counter immediately outputs a reset signal Valid_RST, resets the clock signal Valid, closes the self-oscillation loop, and further reduces the power consumption of the asynchronous tracking algorithm circuit.

[0087] The proposed SAR logic CDAC is a fully differential structure, so that the environmental interference coupled to the two inputs of the CDC will appear a common-mode voltage and be eliminated, and it has a strong anti-interference ability to common-mode interference and frequency noise (i.e., external interference coupled into the sensor through detection events). In addition, the low-noise dynamic comparator in the asynchronous tracking algorithm circuit adopts a two-stage amplification structure, Gm1 amplifies the differential output, and the Gm1 output is connected to Gm2 for further amplification. Compared with the traditional comparator, the differential input will be amplified by two gain stages before driving the latch, thereby reducing the total input reference noise and offset of the latch.

[0088] The capacitance conversion is triggered periodically by an ultra-low power relaxation oscillator. Since CDC is widely used in different scenarios, it is necessary to add a trimming circuit to the ultra-low power relaxation oscillator to output a clock signal Scan of different frequencies. The current I generated by the nanoampere bandgap reference contained in the oscillator REF C INT Charging at C INT The rising slope is The voltage V INT , when V INT >V REF The comparator periodically resets V INT The generated Scan clock signal period is Because I REF 、V REF They have similar temperature characteristics and the oscillation frequency has nothing to do with temperature.

[0089] The above is only a preferred embodiment of the present invention and does not limit the present invention in any form. Although the present invention has been disclosed as a preferred embodiment as above, it is not used to limit the present invention. Any technician familiar with this profession can make some changes or modify the technical contents disclosed above into equivalent embodiments without departing from the scope of the technical solution of the present invention. However, any simple modification, equivalent replacement and improvement made to the above embodiments without departing from the content of the technical solution of the present invention, based on the technical essence of the present invention, within the spirit and principles of the present invention, still fall within the protection scope of the technical solution of the present invention.

Claims

1. A low power capacitance-to-digital converter based on SAR logic and coarse-fine binary counter, characterized in that: It includes an ultra-low power relaxation oscillator (101), an asynchronous tracking algorithm circuit (102), a coarse-fine binary counter (103), a bootstrap switch circuit (104) and a fully differential SAR logic capacitor digital-to-analog converter (105); The ultra-low power consumption relaxation oscillator (101) is used to generate a clock signal Scan, which is an input signal of an asynchronous tracking algorithm circuit (102), a coarse-fine binary counter (103) and a bootstrap switch circuit (104); The asynchronous tracking algorithm circuit (102) is used to generate a clock signal Valid, which is a clock signal of a coarse and fine binary counter (103); The coarse and fine binary counter (102) is used to generate a control signal of a fully differential SAR logic capacitance digital-to-analog converter (105) and control a switch timing.

2. The low power consumption capacitance-to-digital converter based on SAR logic and coarse-fine binary counter according to claim 1, characterized in that: The ultra-low power consumption relaxation oscillator (101) comprises a nano-ampere level reference generation circuit, a low power consumption comparator, a T trigger and a trimming circuit; One end of the low power comparator is connected to the charging capacitor C INT Connect the other end of the low power comparator to V REF connect; The current I of the nanoampere bandgap reference generation circuit REF The charging capacitor C INT Charging, the charging capacitor C INT The rising slope is The voltage V INT , when V INT >V REF The comparator periodically resets V INT ; The Scan clock signal period is The low power comparator uses a low power comparator structure with a high threshold device, a secondary open-loop operational amplifier, a cascade inverter and a latch. REF Represents the reference voltage output by the nanoampere-level reference generation circuit.

3. The low power consumption capacitance-to-digital converter based on SAR logic and coarse-fine binary counter according to claim 2, characterized in that: The nano-ampere level reference generation circuit uses self-cascaded NMOS transistors instead of resistors.

4. The low power consumption capacitance-to-digital converter based on SAR logic and coarse-fine binary counter according to claim 1, characterized in that: The asynchronous tracking algorithm circuit (102) includes a low noise dynamic comparator, a self-oscillating loop and a reset logic.

5. The low power consumption capacitance-to-digital converter based on SAR logic and coarse-fine binary counter according to claim 1, characterized in that: The coarse-fine binary counter (102) uses a combination of a 4-bit coarse CDAC and an 8-bit fine CDAC to optimize switching timing.

6. The low power consumption capacitance-to-digital converter based on SAR logic and coarse-fine binary counter according to claim 1, characterized in that: The bootstrap switch circuit (104) is a 10-tube structure.

7. The low power consumption capacitance-to-digital converter based on SAR logic and coarse-fine binary counter according to claim 1, characterized in that: The fully differential SAR logic capacitor digital-to-analog converter (105) comprises a 12-bit fully differential capacitor array, a charge injection cancellation switch, a reset switch and a pull-up switch.

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