Multifunctional analog instrument test acquisition card based on ZYNQ and data processing method

Abstract

The application discloses a multifunctional analog instrument acquisition card based on a ZYNQ-7000 chip and a data processing method. The acquisition card takes a ZYNQ-7000 series main control chip as a core, a PS end is responsible for data storage and network transmission, and a PL end covers data acquisition, output and cache modules. Four-way single-channel ADC circuits are adopted for data acquisition, and the data is transmitted to the PS end by DMA after FIFO cache and conversion; a signal output module generates analog signals according to instructions of an upper computer; data transmission is realized by multi-channel DMA to be high-speed and stable; and an Ethernet module guarantees communication with the upper computer. The application utilizes the unique structure of the ZYNQ chip, and combines with the collaborative operation of various functional modules, has the advantages of modularization, high precision, high-speed processing and scalability, effectively solves many defects of existing data acquisition systems, can be widely applied to analog signal acquisition and processing in many fields, improves the efficiency and precision of data acquisition and processing, and has a great market application prospect.

Description

Technical Field

[0001] This invention relates to the field of data output and acquisition technology, and in particular to a multi-functional analog instrument test acquisition card and data processing method based on ZYNQ. Background Technology

[0002] Zynq is an innovative chip, unlike traditional FPGAs, it belongs to the category of chip-on-a-programmable systems. Its full name is Zynq-7000 All Programmable SoC, which tightly integrates a dual-core ARM Cortex-A9 processor and a traditional field-programmable gate array (FPGA) logic unit. This unique architecture enables Zynq to excel in meeting the stringent requirements of complex embedded systems for high performance, low power consumption, and multi-core processing capabilities. Based on the SoC characteristics of the ARM processor, Zynq possesses powerful capabilities in handling complex algorithms, control logic, and communication with external devices. Simultaneously, leveraging the programmability of the FPGA, it can flexibly implement various hardware acceleration functions, such as high-speed data processing and interface customization.

[0003] In recent years, my country's integrated circuit industry has developed rapidly, encompassing multiple stages including design, manufacturing, packaging, and testing. Among these, testing is crucial and runs throughout the entire industry chain. During the integrated circuit manufacturing stage, precise testing of each component is required to ensure its performance meets requirements. After packaging, comprehensive functional and parameter testing of the circuit board is necessary to guarantee product quality. Automated testing technology plays an increasingly prominent role in the integrated circuit industry, significantly improving testing efficiency and greatly enhancing accuracy. Data acquisition, as the primary step in information processing, is becoming increasingly important with technological advancements and is widely used in various fields. Furthermore, as applications demand higher data quality, the required precision of data acquisition systems is becoming increasingly stringent, presenting both challenges and opportunities for the development of data acquisition technology.

[0004] However, existing data acquisition systems suffer from limitations of microcontroller-based solutions and issues with the collaborative operation of FPGAs, ARMs, and DSPs. In the current technological field, many companies' automated production lines often employ hardware solutions using microcontrollers as the main control chip to implement data acquisition functions. While this solution is inexpensive, it has significant drawbacks. Due to the relatively weak processing power of microcontrollers, their acquisition speed is severely limited by the processor's operating speed and processing cycle, making it difficult to meet the demands of high-speed signal acquisition. Furthermore, traditional parallel transmission bus interfaces are widely used in this solution; however, such interfaces suffer from weak signal interference resistance and slow data transmission speeds, making them unsuitable for acquiring large volumes of signals.

[0005] Due to their unique circuit design, FPGAs possess extremely strong parallel processing capabilities. However, in data processing, their performance is slightly inferior to ARM and DSP, and their logic design is complex, resulting in high development costs. To compensate for these shortcomings, processors are often used in tandem. However, most current data acquisition systems employ a separate processing architecture using FPGAs and ARM or DSPs, which not only significantly increases costs but also makes circuit design extremely complex. Furthermore, different processors require different development platforms, which significantly extends the development cycle and hinders rapid product iteration and application.

[0006] Furthermore, using a single multi-channel ADC has many system drawbacks. While some designs abandon traditional acquisition systems and use the Xilinx Zynq-7000 series SoC, which integrates FPGA and ARM, as the main control chip, thus improving efficiency to some extent, most of these systems still rely on a single multi-channel ADC for data acquisition. In practice, acquiring multiple analog signals requires circuit switching, and after each switch, the sampling circuit must stabilize before a stable signal voltage can be obtained. As the system sampling time increases, the errors at the acquisition time of each analog signal gradually accumulate and become larger, which is extremely detrimental to subsequent data acquisition analysis and processing, potentially leading to inaccurate analysis results and poor processing performance.

[0007] The ZYNQ heterogeneous chip data transmission method also has drawbacks. Xilinx's ZYNQ heterogeneous chip consists of an FPGA core and an ARM core. When the FPGA and ARM interact, if traditional interrupt or polling data transmission methods are used, the ARM core will frequently participate in the control of every instruction in the system, which will greatly reduce the system transmission efficiency. Moreover, under this data transmission method, the data transmission speed between the ARM and FPGA is slow and unstable, which cannot meet the application scenarios with high real-time requirements, and seriously restricts the overall system performance and application scope. Summary of the Invention

[0008] In view of the numerous problems existing in the prior art, the present invention aims to provide a multi-functional analog instrument test acquisition card and data processing method based on ZYNQ. It is committed to designing a strictly synchronous data generation and acquisition device with modularity, high-speed processing, large-capacity storage, low power consumption, and flexible scalability, and to matching it with a corresponding data processing method, so as to effectively overcome the defects of the prior art and meet the urgent needs of various fields for high-precision and high-efficiency data acquisition and processing.

[0009] To address the aforementioned technical problems, this application provides the following technical solution:

[0010] A ZYNQ-based analog instrument circuit test acquisition card uses the ZYNQ-7000 series main control chip. The PS (Power Supply) side of the main control chip is responsible for raw data storage and network data transmission, including an ARM hard core, large-capacity DDR3 storage, and TCP Ethernet. The PL (Power Buffer) side is responsible for data acquisition, output, and buffering, including:

[0011] The data acquisition module adopts a four-channel single-channel ADC acquisition circuit. The ADC chip is AD9280, which has a maximum conversion rate of 32MSPS and a data bit width of 8bit. It integrates a sample-and-hold amplifier and a power reference source. Single-ended input or differential input can be selected according to actual needs. The data acquisition module is used to serialize the acquired parallel data. The data is buffered and aligned with the help of the FIFO module. After being converted into AXI-Stream data, it is transmitted to the PS end through DMA.

[0012] The signal output module mainly consists of a DDS, including a phase accumulator, a phase modulator, a waveform data table ROM, and an AD9708 converter. It is used to receive waveform data generated by the host computer, convert it into an analog signal, and then output the signal.

[0013] The FIFO cache module, built on RAM, features a first-in-first-out characteristic, requires no address lines, and can efficiently cache data. Its writing and reading are performed under clock control.

[0014] The data transmission module includes a DMA control unit. The DMA control unit is designed with four channels, each of which independently receives different AXI-Stream data streams and uses a FIFO to buffer the data streams. The ARM core can initialize the DMA control unit and assign different interrupt numbers to each channel. Data directly accesses the specified address unit of DDR memory through the S2MM interface. The DMA adopts the Direct transfer mode. The length register of the buffer is 23 bits wide and the address is 32 bits wide. The s_axi_lite_aclk of the DMA uses a 50MHz clock frequency of the ZYNQ GP interface, and the m_axi__s2mm interface uses a 100MHz clock frequency of the ZYNQ HP interface. The reset is a Global low-level reset.

[0015] The Ethernet module uses ZYNQ as the Client and the PC as the Server. It adopts Xilinx's embedded development environment SDK and selects the lwip protocol as the Ethernet protocol stack. First, the Ethernet lwip protocol stack is initialized, and then the TCP configuration parameters, network address, port number, and storage space are initialized. Data from the four channels is transmitted to the host computer through channel traversal. After the data transmission of each channel is completed, the Tcp_Flag signal is pulled high. Before transmission, the network port connection function enables the ZYNQ to actively initiate a TCP connection request to the PC and complete a three-way handshake to establish a TCP network connection.

[0016] This invention relates to a multi-functional analog instrument test acquisition card based on ZYNQ, with the ZYNQ-7000 series main control chip as its core. The PS (Power Supply) side of this main control chip is responsible for storing raw data and transmitting it over the network, and its components include an ARM hard core, large-capacity DDR3 storage, and TCP Ethernet. The PL (Power Buffer) side focuses on data acquisition, output, and buffering, encompassing key components such as ADC, DAC, signal output module, data acquisition module, and FIFO buffer module.

[0017] The present invention also provides a method for acquiring test data of analog instrument circuits based on ZYNQ, a method for outputting test signals of analog instrument circuits based on ZYNQ, and a method for transmitting test data of analog instrument circuits based on ZYNQ.

[0018] in:

[0019] Data acquisition module

[0020] A four-channel single-channel ADC acquisition circuit is employed, using the AD9280 ADC chip. This chip boasts a maximum conversion rate of up to 32 MSPS and an 8-bit data width, integrating a sample-and-hold amplifier and a power reference. It allows for flexible selection of single-ended or differential input modes depending on the application scenario. During operation, the data acquisition module first acquires the input data from the analog instrument circuit, obtaining parallel data. Then, using a FIFO module, this parallel data is buffered and aligned to ensure data width matching before being converted into AXI-Stream data. Finally, the converted data is accurately transmitted to the PS terminal via DMA transfer.

[0021] Signal output module

[0022] It mainly consists of a DDS (Digital Synthesizer), whose internal structure includes important components such as a phase accumulator, a phase modulator, a waveform data table ROM, and an AD9708 converter. This module can receive various waveform data generated by a host computer, such as sine waves, square waves, and sawtooth waves. The host computer first converts the generated waveform data into a COE file in memory format, then sets the signal parameters and sends the data via Ethernet. After receiving the data, the signal output module of the acquisition card writes it into the waveform data table ROM. Subsequently, the data is read from the ROM, and the AD9708 digital-to-analog converter accurately converts the digital signal into an analog signal, which is then finally output as a signal.

[0023] FIFO caching module

[0024] Built on RAM, it features a first-in, first-out (FIFO) architecture and operates efficiently without address lines. Both write and read operations are precisely controlled by the clock. When the write enable (wr_en) signal goes high, data (din) begins to be written to the FIFO; when the read enable (rd_en) signal goes high, the FIFO begins to read data and outputs the read data in the next clock cycle. The FIFO also has several status signals, such as full (full), almost_full (almost full), wr_ack (write operation response), over_flow (overflow), valid (valid read data), almost_empty (almost empty), empty (empty), and underflow (empty). These status signals provide real-time indication of the FIFO's buffer status, offering crucial information for stable system operation.

[0025] Data transmission module

[0026] The core component is the DMA control unit, which is meticulously designed with four channels. Each channel independently receives a different AXI-Stream data stream and is equipped with a FIFO to buffer the data stream. The ARM core can fully initialize the DMA control unit, including assigning a unique interrupt number to each channel and setting various parameters of the DMA engine, such as the channel DMA engine address, the memory address for sending data, the length of the data to be sent, and the DMA transfer direction. The DMA uses a Direct transfer mode, with its buffer length register width set to 23 bits and the address width to 32 bits to match the AXI bus (ZYNQ uses a 32-bit bus width). The DMA's s_axi_lite_aclk uses a 50MHz clock frequency from the ZYNQ GP interface, and the m_axi__s2mm interface uses a 100MHz clock frequency from the ZYNQ HP interface. Reset is performed using a Global low-level reset. Eight-way DMA requires eight DMA interrupts. By using a Connect IP core, four DMA interrupts are cleverly integrated into one data stream, which is then connected to the IRQ_F2P interrupt interface of the ZYNQ core to ensure the efficiency and stability of data transmission.

[0027] Ethernet module

[0028] In this invention, the ZYNQ acts as the Client, and the PC host computer acts as the Server. Xilinx's embedded development environment SDK is used, and the lwip protocol is selected as the Ethernet protocol stack. First, the Ethernet lwip protocol stack is initialized, followed by careful initialization of TCP configuration parameters, network address, port number, and storage space. During data transmission, a channel traversal method is used to sequentially transmit data from the four channels of the acquisition card to the host computer. Before data transmission for each channel, the ZYNQ terminal initiates a TCP connection request to the PC host computer via the network port connection function tcp_client_connect, completing the three-way handshake process for the TCP connection. After successfully establishing the TCP network connection, data transmission begins. After each channel's data transmission is completed, the Tcp_Flag signal is raised to indicate successful Ethernet transmission.

[0029] Compared with existing technologies, the multifunctional analog instrument test acquisition card and data processing method based on ZYNQ of this invention have at least the following beneficial effects:

[0030] 1. This invention adopts a modular design concept, where each functional module works independently yet collaboratively. This design approach gives the system strong scalability, allowing for easy addition or modification of functional modules according to actual needs without requiring large-scale changes to the entire system. This effectively reduces the cost of system upgrades and maintenance, and extends the product's lifecycle.

[0031] 2. Advantages of a four-channel single-channel ADC acquisition circuit

[0032] The design employs a four-channel single-channel ADC acquisition circuit, which effectively avoids signal delay issues during circuit switching compared to traditional multi-channel ADCs. This design ensures the accuracy and real-time performance of data acquisition, providing a reliable data foundation for subsequent data processing and analysis. Furthermore, the ADC requires no additional complex software design; it can operate automatically simply by connecting a corresponding clock, greatly simplifying the development process, improving development efficiency, and reducing development costs.

[0033] 3. Multi-channel DMA technology improves system performance

[0034] The system innovatively employs multi-channel DMA technology, establishing direct data transfer channels between memory and between memory and peripherals. During data transfer, data transfer across the memory-mapped space can be completed without frequent intervention from the ARM core. Multi-channel DMA enables simultaneous, real-time, high-speed transfer of multiple data streams, allowing the ARM-based central processing unit to focus on signal processing and system function control, significantly improving overall system performance and enhancing real-time responsiveness.

[0035] 4. Advantages of customization based on AXI4 bus

[0036] This system is custom-designed based on the AXI4 bus, allowing for flexible customization of the number of transmission channels according to actual needs. It supports fixed-point high-speed data transmission with a maximum bit width of 32 bits, while also possessing strong compatibility, enabling variable-length, variable-address DMA packet transmission for data from different channels. This flexible transmission method effectively adapts to diverse data transmission requirements, improving the system's data processing capabilities and transmission efficiency.

[0037] 5. Utilize ZYNQ's existing DDR memory resources

[0038] By fully utilizing ZYNQ's existing DDR storage resources without using external devices, the system significantly improves its ability to transmit and store various types of data. This not only reduces reliance on external storage devices, lowering system costs and complexity, but also increases data storage and access speed, further enhancing overall system performance.

[0039] The following description, in conjunction with the accompanying drawings, further illustrates the multifunctional analog instrument test acquisition card and data processing method based on ZYNQ of this invention. Attached Figure Description

[0040] Figure 1 This is a system overall design block diagram of the multi-functional analog instrument test acquisition card based on ZYNQ according to the present invention;

[0041] Figure 2 This is a flowchart of the data acquisition module of the ZYNQ-based multi-functional analog instrument test acquisition card of the present invention;

[0042] Figure 3 This is a flowchart of the data output module of the multi-functional analog instrument test acquisition card based on ZYNQ of the present invention;

[0043] Figure 4 This is a timing diagram for writing the FIFO standard of the multi-functional analog instrument test acquisition card based on ZYNQ in this invention;

[0044] Figure 5 This is a timing diagram of the FIFO standard reading operation of the ZYNQ-based multi-functional analog instrument test acquisition card of the present invention;

[0045] Figure 6 This is a schematic diagram of the four-channel DMA design of the ZYNQ-based multi-functional analog instrument test acquisition card of the present invention;

[0046] Figure 7 This is a flowchart of the data transmission module of the ZYNQ-based multi-functional analog instrument test acquisition card of the present invention;

[0047] Figure 8 This is a flowchart of the Ethernet module of the ZYNQ-based multi-functional analog instrument test acquisition card of the present invention. Detailed Implementation

[0048] In the ZYNQ-based analog instrument circuit test acquisition card of this invention, data processing mainly covers core links such as data acquisition, transmission and storage. Each link works closely together and is deeply integrated with the overall system architecture.

[0049] like Figure 1The diagram shown is a system overall design block diagram of the multi-functional analog instrument test acquisition card based on ZYNQ according to the present invention. It mainly includes the connection relationships between various components on the PS and PL ends of the ZYNQ main control chip, including the connection methods between components such as the ARM hard core, DDR3 memory, TCP Ethernet, ADC, DAC, signal output module, data acquisition module, FIFO buffer module, and DMA control unit. The PS end of the ZYNQ-7000 series main control chip is responsible for raw data storage and network data transmission, including the ARM hard core, large-capacity DDR3 memory, and TCP Ethernet; the PL end is responsible for data acquisition, output, and buffering.

[0050] The main components of the ZYNQ-based multi-functional analog instrument test acquisition card of this invention are described below with reference to the accompanying drawings:

[0051] 1. Clock Management

[0052] In the overall program design of ZYNQ, based on Figure 1 In the system architecture shown, the clock management program on the PL side is crucial. This system is based on the XC7Z020 core board, which provides multiple clock sources, such as a 50MHz crystal oscillator. During FPGA operation, the clock is precisely managed by calling the corresponding IP core. Figure 1 As can be seen, there is a close connection between each module and the clock source. For example, the data acquisition module and the signal output module all rely on a precise clock signal to coordinate their operation. By properly allocating and controlling the clock, it is ensured that each module can obtain the required clock frequency, enabling each module to operate stably at an appropriate speed, thereby strictly guaranteeing the clock synchronization of the entire test board system. For example, the AD9280 ADC chip in the data acquisition module requires a specific frequency clock signal to drive it to operate at its maximum conversion rate of 32MSPS. The clock management program can accurately provide this signal, avoiding data acquisition errors or performance degradation caused by inaccurate clock frequencies.

[0053] 2. Data acquisition module,

[0054] A four-channel single-channel ADC acquisition circuit is adopted. The ADC chip is AD9280, with a maximum conversion rate of 32MSPS and a data bit width of 8bit. It integrates a sample-and-hold amplifier and a power reference source. Single-ended input or differential input can be selected according to actual needs. The operating voltage range is 2.7V-5.5V. The data acquisition module is used to serialize the acquired parallel data. The data is buffered and aligned with the help of the FIFO module. After being converted into AXI-Stream data, it is transmitted to the PS end through DMA.

[0055] Specifically, please see Figure 1 , Figure 2,Include:

[0056] 1) ADC configuration and data acquisition (see...) Figure 1 )

[0057] The data acquisition module uses the AD9280 chip for data acquisition. (Refer to...) Figure 1 First, the registers of the AD9280 are configured appropriately using the ARM architecture to determine its operating mode (single-ended or differential input) and other parameters. Then, the AD9280 acquires the input data from the analog instrument circuit according to the set maximum conversion rate of 32 MSPS and a data width of 8 bits, obtaining parallel data. During this process, based on... Figure 1 The connection between the data acquisition module and the ADC is described, with data flowing from the analog instrument circuit into the ADC and then into the subsequent processing flow of the data acquisition module.

[0058] 2) Data caching and transformation (see Figure 1 , Figure 2 )

[0059] The acquired parallel data is fed into the FIFO module for buffering and alignment. Figure 2 The data acquisition module flowchart clearly shows the data operation process within the FIFO module. Under the control of the clock signal, the FIFO module manages data in an orderly manner according to the first-in, first-out (FIFO) principle. When data is written to the FIFO, the write enable signal (wr_en) is pulled high on the corresponding clock edge, and the data is sequentially stored in the FIFO. Simultaneously, the FIFO module monitors its buffer status to prevent data overflow (determined by the overflow signal). When data needs to be read, the read enable signal (rd_en) is pulled high, and the FIFO outputs the buffered data sequentially, converting it into an AXI-Stream. Figure 1 As can be seen, the FIFO module acts as a bridge between the data acquisition module and the DMA control unit, caching and converting data formats, ensuring that data can smoothly enter the DMA transfer stage.

[0060] 3) DMA transfer (see...) Figure 1 , Figure 2 , Figure 6 , Figure 7 )

[0061] The converted AXI-Stream data is transferred to the PS via DMA. Combined with... Figure 6 and Figure 7 The DMA control unit, under the initialization of the ARM core, assigns an interrupt number to each channel and sets relevant parameters. Figure 1As can be seen, data is read from the FIFO by the DMA and then accurately transferred to the DDR3 memory on the PS side via the S2MM interface according to the preset address units. During the transfer process, the DMA strictly follows the Direct transfer mode to ensure efficient and stable data transmission. For example, in Figure 7 The document details the entire process of DMA engine initialization, interrupt initialization, parameter configuration, and initiating DMA transfer. This process is consistent with... Figure 1 The data acquisition modules in the middle correspond to each other in the path for transmitting data to the PS end via DMA, ensuring the accuracy of data from acquisition to storage.

[0062] 3. Signal output module (see Figure 1 , Figure 3 )

[0063] The signal output module mainly consists of a DDS, including a phase accumulator, a phase modulator, a waveform data table ROM, and an AD9708 converter. It is used to receive waveform data with arbitrary 8-bit width and 256-bit depth generated by the host computer, such as sine waves, square waves, sawtooth waves, etc., and convert them into COE files in memory format. The host computer sets the signal parameters and sends the data via Ethernet. After the data is written to the ROM, the digital signal is converted into an analog signal by the AD9708 digital-to-analog converter before being output.

[0064] 1) Data preparation for the host computer

[0065] like Figure 1 As shown, the host computer generates specific waveform data as needed, such as sine waves, square waves, or sawtooth waves. The generated waveform data is converted into a COE file in memory format. Then, the host computer sets signal parameters, such as waveform frequency and amplitude, via Ethernet and sends the COE file data to the acquisition card. Figure 1 As can be seen, the host computer and the signal output module of the acquisition card establish a connection through the Ethernet module to realize data transmission and interaction.

[0066] 2) Data writing and conversion output

[0067] Please see Figure 1 , Figure 3 After receiving the data, the signal output module of the acquisition card writes it into the waveform data table ROM. Combined with... Figure 3 The data output module flowchart shows that the writing process is managed by the internal control logic of the DDS, ensuring that the data is accurately stored in the ROM. When an output signal is needed, the data is read from the ROM, processed sequentially by components such as a phase accumulator and a phase modulator, and finally converted from a digital signal to an analog signal by the AD9708 digital-to-analog converter before being output to external devices or circuits. Figure 1In the diagram, the connection relationships between the components within the signal output module demonstrate the complete path of data from reception to the host computer to the final output of the analog signal. The components work together to complete the signal output function.

[0068] 4. Implementation of the FIFO caching module

[0069] See Figure 4 , Figure 5 The FIFO cache module is built on RAM and features a first-in-first-out characteristic. It does not require address lines and can efficiently cache data. Its writing and reading are performed under clock control. Data is written when the write enable is pulled high and data is read when the read enable is pulled high. It also has corresponding status signals to indicate the cache status.

[0070] The FIFO cache module is built on RAM in its hardware design. Figure 4 As can be seen from the write timing diagram of the standard FIFO, the write enable (wr_en) and read enable (rd_en) signals are pulled high or low by the system control logic according to data transmission needs. When data needs to be buffered, the write enable signal is pulled high on the rising edge (or falling edge, depending on the specific design) of the clock, and the data is written to the FIFO bit by bit under the control of the clock. Simultaneously, the internal logic circuitry of the FIFO monitors the buffer status in real time, such as using the full and almost_full signals to determine if it is about to be full, so that the system can take appropriate measures, such as pausing data writing or performing data transfer operations. During data reading, refer to... Figure 5 The timing diagram for the standard FIFO read operation is as follows: when the read enable signal is pulled high, the FIFO outputs data sequentially under clock control. At the same time, the valid signal indicates the validity of the output data. The almost_empty and empty signals help the system determine whether the FIFO is about to be empty or is already empty, avoiding data errors caused by empty read operations. Figure 4 and Figure 5 The timing diagrams in the document provide a detailed illustration of the precise timing of the FIFO cache module's operations during data writing and reading, offering a reliable basis for the system's data cache management.

[0071] 5. Implementation of the data transmission module

[0072] Please combine Figure 1 , Figure 6 , Figure 7The data transmission module includes a DMA control unit. The DMA control unit is designed with four channels, each of which independently receives different AXI-Stream data streams and uses a FIFO to buffer the data streams. The ARM core can initialize the DMA control unit and assign different interrupt numbers to each channel. Data directly accesses the specified address unit of DDR memory through the S2MM interface. The DMA adopts the Direct transfer mode. The length register of the buffer is 23 bits wide and the address is 32 bits wide. The s_axi_lite_aclk of the DMA uses a 50MHz clock frequency of the ZYNQ GP interface, and the m_axi__s2mm interface uses a 100MHz clock frequency of the ZYNQ HP interface. The reset is a Global low-level reset.

[0073] 1) DMA control unit initialization

[0074] See Figure 6 , Figure 7 During system startup, the ARM core performs a full initialization of the DMA control unit. Based on... Figure 6 The four-channel DMA design assigns different interrupt numbers to each of the four channels; for example, interrupt number 5 is assigned to channel 1, interrupt number 6 to channel 2, etc., ensuring that an interrupt notification can be accurately sent to the ARM core after data transfer is completed on each channel. Then, refer to... Figure 7 Configure various parameters of the DMA engine, including the address of the DMA engine for each channel (e.g., setting the DMA engine address for channel 1 to 0x20000000), the memory address for sending data to the corresponding channel data storage address of the data acquisition module, the length of the data to be sent based on the actual amount of data acquired, and the DMA transfer direction, etc. Figure 6 The connection between the DMA control unit, the FIFO cache of each channel, and the DDR memory can be clearly seen, which provides an intuitive reference for parameter setting and ensures the accuracy of the initialization process.

[0075] 2) Data transmission process

[0076] Combination Figure 1 , Figure 6 , Figure 7 It can be seen that when the AXI-Stream data stream from the data acquisition module is input to the AD9208_Stream IP core at the front end of each channel of the DMA control unit, combined with Figure 6 These IP cores convert the data format to the AXI-Stream data format supported by the AXI4 bus and then store it in the corresponding FIFO buffer. Subsequently, according to... Figure 7The process involves the ARM core initiating DMA and sending commands. The DMA control unit, according to preset parameters, drives data from the FIFO cache to the specified address in the DDR memory via the S2MM interface. During this process, from... Figure 6 It is known that the DMA uses a Direct transfer mode, with a buffer length register width of 23 bits and an address width of 32 bits to match the AXI bus (ZYNQ uses a 32-bit bus width). The DMA's s_axi_lite_aclk uses the 50MHz clock frequency of the ZYNQ GP interface, and the m_axi__s2mm interface uses the 100MHz clock frequency of the ZYNQ HP interface. Reset is performed using a Global low-level reset. The eight-channel DMA requires eight DMA interrupts. A Connect IP core integrates four DMA interrupts into a single data interrupt, which is then connected to the ZYNQ core's IRQ_F2P interrupt interface. This integration process occurs within... Figure 6 The system provides a clear overview, ensuring efficient and accurate handling of interruptions during data transmission and guaranteeing stable data transmission within the system.

[0077] 6. Implementation of Ethernet module

[0078] Combination Figure 1 , Figure 8 As can be seen, the Ethernet module uses ZYNQ as the Client and the PC as the Server. It adopts Xilinx's embedded development environment SDK and selects the lwip protocol as the Ethernet protocol stack. First, the Ethernet lwip protocol stack is initialized, and then the TCP configuration parameters, network address, port number, and storage space are initialized. The data of the four channels is transmitted to the host computer through channel traversal. After the data transmission of each channel is completed, the Tcp_Flag signal is pulled high. Before transmission, the network port connection function enables the ZYNQ to actively initiate a TCP connection request to the PC and complete the three-way handshake to establish a TCP network connection.

[0079] 1) Ethernet communication link setup

[0080] Combination Figure 8 After running Xilinx's embedded development environment SDK on the ZYNQ platform, according to Figure 8The Ethernet module flowchart first initializes the Ethernet LWIP protocol stack. During initialization, network layer parameters are set, such as the IP address being set to 192.168.0.100, the subnet mask to 255.255.255.0, and the gateway to 192.168.0.1. Simultaneously, TCP configuration parameters are initialized, including setting the port number to 8888, the timeout retransmission count to 3, and storage space is initialized, allocating a certain amount of memory for data caching based on the estimated data transmission volume. From... Figure 1 The image shows the position of the Ethernet module in the overall system architecture. It serves as a communication bridge between the acquisition card and the host computer, and these initialization parameters lay the foundation for establishing a stable Ethernet connection.

[0081] 2) Data transmission proceeds in an orderly manner

[0082] Combination Figure 1 , Figure 8 During data transmission, according to Figure 8 The channel traversal method starts with channel 1 of the acquisition card. Before data transmission on each channel, the ZYNQ client initiates a TCP connection request to the PC host computer (acting as the server) via the network interface connection function `tcp_client_connect`, completing a three-way handshake to establish a TCP network connection. For example, during the first handshake, the ZYNQ client sends a SYN packet to the host computer, which returns a SYN+ACK packet. The ZYNQ client then sends an ACK packet to complete the connection establishment. After the connection is established, data transmission begins on channel 1. Once transmission is complete, the `Tcp_Flag` signal is raised. Upon detecting this signal, the host computer prepares to receive data from the next channel, and this cycle continues until all four channels have completed data transmission. Figure 1 The diagram illustrates the data interaction path between the Ethernet module, other modules of the acquisition card, and the host computer, ensuring accurate and efficient data transmission between the acquisition card and the host computer via Ethernet, thus realizing the system's Ethernet communication function.

[0083] The following is combined with Figure 1 , Figure 2 , Figure 6 , Figure 7 The implementation process of the data processing module is described in detail:

[0084] In the ZYNQ-based analog instrument circuit test acquisition card of this invention, data processing mainly covers core links such as data acquisition, transmission and storage. Each link works closely together and is deeply integrated with the overall system architecture. The implementation process is described in detail below with reference to the accompanying drawings.

[0085] I. Data Acquisition and Preliminary Processing

[0086] like Figure 1 , Figure 2 As shown, the data acquisition module, as the source of data inflow, has its operation closely linked to the overall system architecture. From Figure 1 As can be seen, the data acquisition module is connected to a four-channel single-channel ADC acquisition circuit (ADC chip is AD9280). Based on its own characteristics, the ADC chip can flexibly select single-ended or differential input mode within the operating voltage range, and acquire the input data of the analog instrument circuit with a maximum conversion rate of 32MSPS and a data bit width of 8 bits to obtain parallel data.

[0087] Reference Figure 2 The data acquisition module flowchart shows that the acquired parallel data is then sent to the FIFO module for buffering and alignment. In the FIFO module, when the write enable (wr_en) signal goes high on the corresponding clock edge (based on the system clock setting and coordinated with the overall clock management), data is written to the FIFO bit by bit under precise clock signal control. Simultaneously, the FIFO module continuously monitors the buffer status through internal logic circuits, using status signals such as full and almost_full to determine the data buffer status and prevent data overflow. For example, when the almost_full signal is valid, the system can pause data acquisition or adjust the data flow according to a preset strategy to ensure the stability of the data buffer.

[0088] When data needs to be read, the read enable (rd_en) signal goes high, and the FIFO outputs the buffered data sequentially, converting it into AXI-Stream data. This conversion process prepares the data format for subsequent data transfer to the PS via DMA, enabling data to flow efficiently within the system.

[0089] II. Data Transmission and DMA Control

[0090] like Figure 1 , Figure 6 , Figure 7 As shown, after being converted into AXI-Stream data, the data enters the data transmission module, where the core component, the DMA control unit, begins to play a crucial role. Based on... Figure 6 The four-channel DMA design architecture allows the four channels of the DMA control unit to independently receive different AXI-Stream data streams, and each is equipped with a FIFO to buffer the data stream.

[0091] During system startup, the ARM core performs a full initialization of the DMA control unit (e.g., Figure 7(As shown). First, different interrupt numbers are carefully assigned to the four channels. For example, interrupt number 10 is assigned to channel 1, interrupt number 11 is assigned to channel 2, etc. This measure ensures that an interrupt notification can be accurately sent to the ARM core after the data transmission of each channel is completed, so that the ARM core can know the data transmission status in a timely manner and perform subsequent processing.

[0092] Then, set the various parameters of the DMA engine, including the address of the DMA engine for each channel, such as setting the DMA engine address of channel 1 to 0x30000000, the memory address for sending data to be the data storage address of the corresponding channel of the data acquisition module, the length of the data to be sent to be determined according to the actual amount of data acquired, and specifying the DMA transfer direction as from the FIFO cache to the DDR memory.

[0093] When the AXI-Stream data stream from the data acquisition module is input to the AD9208_Stream IP core at the front end of each channel of the DMA control unit ( Figure 6 (The location and connection relationship are clearly shown in the image). These IP cores convert the data format to the AXI-Stream data format supported by the AXI4 bus and then store it in the corresponding FIFO buffer. Next, the ARM core initiates the DMA send command. The DMA control unit drives the data from the FIFO buffer to the specified address unit of the DDR memory through the S2MM interface according to preset parameters.

[0094] During transmission, the DMA uses a Direct transfer mode. Its buffer length register is 23 bits wide, and its address register is 32 bits wide to match the AXI bus (ZYNQ uses a 32-bit bus width). The DMA's s_axi_lite_aclk uses the 50MHz clock frequency of the ZYNQ GP interface, and the m_axi__s2mm interface uses the 100MHz clock frequency of the ZYNQ HP interface. Reset is performed using a Global low-level reset. Eight-channel DMA requires eight DMA interrupts. A Connect IP core combines four DMA interrupts into one data interrupt, which is then connected to the ZYNQ core's IRQ_F2P interrupt interface. Figure 6 This integration and connection process is presented in detail to ensure the efficiency and accuracy of interruption handling during data transmission and to guarantee stable data transmission within the system.

[0095] III. Data Storage and System Collaboration

[0096] Data transferred via DMA is ultimately stored in DDR3 memory on the PS side. Figure 1It is evident that DDR3 storage is closely interconnected with the ARM hard core and Ethernet module. During data storage, the ARM core can further process or manage the stored data according to system requirements, such as classifying, labeling, or performing preliminary data analysis operations.

[0097] Simultaneously, the stored data can interact with the host computer via the Ethernet module. When the host computer requires data, the system can read the corresponding data from the DDR3 storage according to the host computer's instructions and transmit the data to the host computer via the Ethernet module. This process involves a series of operations such as Ethernet module initialization, TCP connection establishment, and data transmission (as described in the Ethernet module implementation process above). Working in conjunction with the data processing module, it realizes complete lifecycle management of data throughout the system, from acquisition, transmission, and storage to interaction with the host computer, ensuring that the system can efficiently and accurately complete the processing tasks of analog instrument circuit test data.

[0098] The embodiments described above are merely preferred embodiments of the present invention and are not intended to limit the scope of the present invention. Various modifications and improvements made by those skilled in the art to the technical solutions of the present invention without departing from the spirit of the present invention should fall within the protection scope defined by the claims of the present invention.

[0099] Abbreviation Glossary

[0100]

[0101]

Claims

1. A multi-functional analog instrument test acquisition card based on ZYNQ, comprising a ZYNQ-7000 series main control chip, characterized in that: The main control chip has a PS terminal and a PL terminal. The PS terminal is responsible for storing raw data and transmitting network data, and includes an ARM hard core, large-capacity DDR3 storage and TCP Ethernet. The PL (Programmer) module is responsible for data acquisition, output, and buffering. The data acquisition module uses a four-channel single-channel ADC acquisition circuit. The ADC chip is AD9280, which has a maximum conversion rate of 32MSPS and an 8-bit data width. It also integrates a sample-and-hold amplifier and a power reference source. It can select single-ended or differential input mode according to actual needs. This module is used to buffer, align and convert the acquired parallel data into AXI-Stream data through the FIFO module, and then transfer it to the PS end through DMA. The signal output module mainly consists of a DDS, including a phase accumulator, a phase modulator, a waveform data table ROM, and an AD9708 digital-to-analog converter. It is used to receive waveform data generated by the host computer, convert it into an analog signal, and then output it. The FIFO cache module, built on RAM, features first-in-first-out characteristics and requires no address lines, enabling efficient data writing and reading operations under clock control. The data transmission module includes a DMA control unit with four channels. Each channel independently receives different AXI-Stream data streams and uses a FIFO buffer. The ARM core can initialize the DMA control unit and assign different interrupt numbers. Data directly accesses the specified address unit of DDR memory via the S2MM interface. The DMA adopts the Direct transfer mode. Its buffer length register has a bit width of 23 bits and the address bit width is 32 bits. s_axi_lite_aclk uses the 50MHz clock frequency of the ZYNQ GP interface, and the m_axi__s2mm interface uses the 100MHz clock frequency of the ZYNQ HP interface. The reset is a Global low-level reset. The Ethernet module uses a ZYNQ as the client and a PC as the server. It employs the lwip protocol stack from the Xilinx embedded development environment SDK. First, the Ethernet lwip protocol stack is initialized, followed by the initialization of TCP configuration parameters, network address, port number, and storage space. Data from the four channels is transmitted to the host computer via channel traversal. Before data transmission on each channel, a TCP connection request is initiated to the PC via the network port connection function tcp_client_connect, and a three-way handshake is completed to establish the connection. After transmission is complete, the Tcp_Flag signal is raised.

2. The ZYNQ-based multifunctional analog instrument test acquisition card according to claim 1, characterized in that, The ZYNQ-7000 series main control chip operates on the XC7Z020 core board. It manages the clock by calling the matching IP core to ensure that each module operates at the required clock frequency and to ensure clock synchronization of the entire test board system.

3. The ZYNQ-based multi-functional analog instrument test acquisition card according to claim 1, characterized in that, In the data acquisition module, registers are configured via ARM, all acquired channel data are sorted sequentially and stored in a FIFO, and then DMA is used to read the data in the FIFO and transmit it to the PS-side DDR3.

4. The ZYNQ-based multi-functional analog instrument test acquisition card according to claim 1, characterized in that, The DMA control unit front end is equipped with a pre-written AD9208_Stream IP core for each channel, which is used to convert data into AXI-Stream data format supported by the AXI4 bus.

5. The multi-functional analog instrument test acquisition card based on ZYNQ according to claim 1, characterized in that, Eight-way DMA requires eight DMA interrupts. A Connect IP core is used to combine four DMA interrupts into one data stream, which is then connected to the ZYNQ core's IRQ_F2P interrupt interface.

6. The ZYNQ-based multi-functional analog instrument test acquisition card according to claim 1, characterized in that, The multi-channel DMA initializes four cache spaces to store data frames, with the initial address at memory address 128MB. Each cache space is 4MB, for a total of 16MB of cache space is initialized.

7. A method for acquiring test data of analog instrument circuits based on ZYNQ, using the ZYNQ-based multi-functional analog instrument test acquisition card as described in any one of claims 1 to 6, characterized in that, Includes the following steps: The input data of the analog instrument circuit is acquired using a four-channel single-channel ADC acquisition circuit. The ADC chip is AD9280. This chip can select single-ended input or differential input according to actual needs within the operating voltage range, and acquire data at a maximum conversion rate of 32MSPS. The data bit width is 8 bits, and it integrates a sample-and-hold amplifier and a power reference source. The collected parallel data is buffered and aligned using a FIFO module to match its data bit width before being converted into AXI-Stream data. The AXI-Stream data is transferred to the DDR3 memory on the PS side via the DMA control unit. The four channels of the DMA control unit receive different AXI-Stream data streams, and each channel uses a FIFO for buffering. The DMA uses a Direct transfer mode. After the ARM core initializes the DMA control unit and assigns an interrupt number, the data is transferred through the S2MM interface according to the preset address units. The length register of the buffer is 23 bits wide, and the address is 32 bits wide. The s_axi_lite_aclk of the DMA uses a 50MHz clock frequency of the ZYNQ GP interface, and the m_axi__s2mm interface uses a 100MHz clock frequency of the ZYNQ HP interface. The reset is a Global low-level reset.

8. A method for outputting test signals for analog instrument circuits based on ZYNQ, using the ZYNQ-based multi-functional analog instrument test acquisition card as described in any one of claims 1 to 6, characterized in that, Includes the following steps: The host computer generates waveform data and converts it into a COE file in memory format; The host computer sets signal parameters via Ethernet and sends COE file data to the ZYNQ-based analog instrument circuit test acquisition card; The signal output module in the acquisition card receives data and writes it into the waveform data table ROM. This module is composed of a DDS, including a phase accumulator, a phase modulator, a waveform data table ROM, and an AD9708 digital-to-analog converter. After the data is read from the ROM, the digital signal is converted into an analog signal by the AD9708 digital-to-analog converter and then output as a signal.

9. A method for transmitting test data for analog instrument circuits based on ZYNQ, using the ZYNQ-based multi-functional analog instrument test acquisition card as described in any one of claims 1 to 6, characterized in that, Includes the following steps: In the ZYNQ-based analog instrument circuit test acquisition card, the DMA control unit receives AXI-Stream data streams from the data acquisition module. Each channel of the DMA control unit is equipped with an AD9208_Stream IP core at the front end, which is used to convert the data into the AXI-Stream data format supported by the AXI4 bus. The ARM core initializes the DMA control unit, including assigning different interrupt numbers to each channel and setting the parameters of the DMA engine, including the address of the channel DMA engine, the memory address for sending data, the length of data to be sent, and the DMA transfer direction. The DMA control unit transmits data from multiple channels directly to a specified address in the DDR memory via the S2MM interface according to the set parameters. The interrupts of the eight-channel DMA are integrated through the Connect IP core and connected to the IRQ_F2P interrupt interface of the ZYNQ core. During the transmission, the DMA adopts the Direct transmission mode. The length register of the buffer is 23 bits wide and the address is 32 bits wide. The s_axi_lite_aclk of the DMA adopts the 50MHz clock frequency of the ZYNQ GP interface, and the m_axi__s2mm interface adopts the 100MHz clock frequency of the ZYNQ HP interface. The reset adopts the Global low-level reset.

10. A method for Ethernet communication in testing analog instrument circuits based on ZYNQ, using the ZYNQ-based multi-functional analog instrument test acquisition card as described in any one of claims 1 to 6, characterized in that, Includes the following steps: In the ZYNQ-based analog instrument circuit test acquisition card, Xilinx's embedded development environment SDK is used, and lwip protocol is selected as the Ethernet protocol stack for Ethernet lwip protocol stack initialization. Initialize TCP configuration parameters, network address, port number, and storage space; The data from the four channels in the acquisition card is transmitted to the host computer in sequence through channel traversal. Before the data transmission of each channel, the ZYNQ terminal initiates a TCP connection request to the PC host computer acting as the server through the network port connection function tcp_client_connect, and completes the three-way handshake to establish a TCP network connection. After the data transmission of each channel is completed, the Tcp_Flag signal is raised.

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