Read-write request processing method, protocol conversion module, electronic equipment and storage medium

Abstract

The embodiment of the invention provides a read-write request processing method, a protocol conversion module, electronic equipment and a storage medium, and relates to the technical field of chips. The method comprises the steps that a protocol conversion module is arranged in a processor cluster, an original read-write request is converted into a first read-write request conforming to a CHI protocol through a first conversion module in the protocol conversion module, and a corresponding transmission channel is distributed to the first read-write request; and the request queue module orderly sends the received first read-write request, and the second conversion module recombines the first read-write request information to a second read-write request conforming to the CHI protocol, and allocates a corresponding channel for the second read-write request. According to the embodiment of the invention, the internal data channel (AXI or similar AXI) is directly converted into the CHI interface in the processor cluster, the internal circuit resources of the processor cluster are reused, the circuit area is saved, and the access path time delay is reduced.

Description

Technical Field

[0001] The present disclosure relates to the field of chip technology, and in particular to a read / write request processing method, a protocol conversion module, an electronic device, and a storage medium. Background Art

[0002] SOC chip (System on Chip) is a chip that integrates multiple functional modules and can be used in multiple fields such as servers and vehicles.

[0003] At present, many large-scale SOC chip systems use NOC (Network onChip) that supports cache consistency, and most of them are implemented based on the ARM AMBA5 (Advanced MicrocontrollerBus Architecture, a bus architecture) CHI (Coherent Hub Interface, a protocol interface) cache consistency interconnect protocol.

[0004] However, except for the CPU (Central Processing Unit) in SOC, which supports the CHI protocol interface, the IP (Intellectual Property) of most other processors (hereinafter referred to as XPU) devices do not support the CHI protocol interface. In the existing technology, the conventional AMBA AXI (Advanced eXtensibleInterface) protocol interface is first converted to the CHI protocol interface through a bridge module, and then connected to such NOC. The introduction of the bridge module will cause the consumption of circuit area and the increase of access latency, and the performance is low. Summary of the invention

[0005] The embodiments of the present disclosure provide a read / write request processing method, a protocol conversion module, an electronic device, and a storage medium, which can solve the problem in the prior art that the introduction of a bridge module causes consumption of circuit area and increase of access delay. The technical solutions provided by the present disclosure are as follows: According to one aspect of an embodiment of the present disclosure, a read / write request processing method is provided, which is applied to a protocol conversion module in a processor cluster, the processor cluster further comprising at least one processor core, the protocol conversion module being connected to a downstream module, any processor core supporting an AXI protocol or an internal data path associated with the AXI protocol, and the downstream module supporting a CHI protocol; The protocol conversion module includes a first conversion module, a processing module and a second conversion module, and the processing module reuses the internal circuit resources of the processor cluster; The method comprises: By means of the first conversion module, at least one memory access path corresponding to each processor core is merged into a target memory access path, a target read / write request transmitted by the target memory access path is received, and the target read / write request is split based on the requirements of the CHI protocol to obtain at least one first read / write request; for each first read / write request, a first target channel for transmitting the first read / write request is determined, and the first read / write request is sent to a processing module in the protocol conversion module through the first target channel; Allocate the first read / write request to any cache unit in the request queue module in the processing module through the processing module; send the first read / write request to the second conversion module through any cache unit when a preset sending condition is met; The information of the first read / write request is reassembled through the second conversion module to obtain a second read / write request named in accordance with the CHI protocol; a second target channel for transmitting the second read / write request is determined, and the second read / write request is sent to the downstream module through the second target channel.

[0006] Optionally, the processing module includes a write data cache module, a request queue module and a read data cache module; the processor cluster includes an original write data cache module, an original request queue module and an original read data cache module; The write data cache module reuses the circuit resources of the original write data cache module, the request queue module reuses the circuit resources of the original request queue module, and the read data cache module reuses the circuit resources of the original read data cache module.

[0007] Optionally, the method further comprises: For each cache unit in the request queue module, the cache unit stores an access address corresponding to each first read / write request received; The step of sending the first read / write request to the second conversion module in the protocol conversion module by any of the cache units when a preset sending condition is met includes: If any cache unit determines that there is no address conflict based on the access address of the first read / write request, the first read / write request is sent to the second conversion module, so that the second conversion module sends the first read / write request to the downstream module.

[0008] Optionally, sending the first read / write request to the second conversion module includes: If it is determined by any cache unit that the first read / write request is a write request, after receiving a write data ready notification for the first read / write request sent by a write data cache module, the first read / write request is sent to the second conversion module.

[0009] Optionally, the sending the first read / write request to the downstream module further includes: Receiving a first response to the first read / write request through any cache unit; If the first response is a retransmission response and it is detected that the number of transmission credits is greater than zero, resending the first read / write request to the downstream module; The transmission credit quantity is determined based on a credit counter in the second conversion module.

[0010] Optionally, the method further comprises: In the case where the first read / write request is a write request, if the first response is a write data sending identification response, a write data sending instruction is sent to a write data cache module through any cache unit, so that the write data cache module sends the write data corresponding to the write request to the downstream module; When a completion response to the write data is received, a write response corresponding to the write request is returned to the first conversion module, so that the first conversion module returns the write response to the processor core.

[0011] Optionally, the method further comprises: In the case where the first read-write request is a read request, if the first response includes read data corresponding to the read request, the read data returned by the downstream module is received through the read data cache module, and the received read data is cached.

[0012] Optionally, the method further includes: For each cache unit in the request queue module, the cache unit stores a transmission identifier corresponding to each first read / write request received; The received read data is cached, and then further comprises: The read data cache module obtains the transmission identifiers corresponding to each cache unit respectively stored therein from the request queue module, determines the read data sending order based on the transmission identifiers corresponding to each cache unit respectively stored therein, and sends at least one cached read data in sequence to the first conversion module according to the read data sending order, so that the first conversion module returns each read data to the processor in sequence.

[0013] According to another aspect of an embodiment of the present disclosure, a protocol conversion module is provided, the module comprising: A first conversion module is used to merge at least one memory access path corresponding to each processor core into a target memory access path, receive a target read / write request transmitted by the target memory access path, split the target read / write request based on the requirements of the CHI protocol, and obtain at least one first read / write request; for each first read / write request, determine a first target channel for transmitting the first read / write request, and send the first read / write request to the processing module in the protocol conversion module through the first target channel; A processing module, configured to assign the first read / write request to any cache unit in a request queue module in the processing module; and send the first read / write request to the second conversion module through any cache unit when a preset sending condition is met; The second conversion module is used to recombine the information of the first read-write request to obtain a second read-write request named in accordance with the CHI protocol; determine a second target channel for transmitting the second read-write request, and send the second read-write request to the downstream module through the second target channel.

[0014] According to another aspect of an embodiment of the present disclosure, an electronic device is provided, which includes a memory, a processor, and a computer program stored in the memory and executable on the processor, and the processor implements the steps of any one of the above-mentioned read and write request processing methods when executing the program.

[0015] According to another aspect of the embodiments of the present disclosure, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, the steps of any of the above-mentioned read and write request processing methods are implemented.

[0016] According to one aspect of an embodiment of the present disclosure, a computer program product is provided, which includes a computer program. When the computer program is executed by a processor, the steps of any of the above-mentioned read and write request processing methods are implemented.

[0017] The technical solution provided by the embodiments of the present disclosure has the following beneficial effects: A protocol conversion module is built into the processor cluster, and the original read / write request is converted into a first read / write request that complies with the CHI protocol through the first conversion module in the protocol conversion module, and a corresponding transmission channel is allocated for the first read / write request. The processing module sends the received first read / write request in order, and the second conversion module renames the first read / write request to a second read / write request that symbolizes the CHI protocol, and a corresponding channel is allocated for the second read / write request. The protocol conversion module enables the internal data channel (AXI or similar AXI) in the processor cluster to be directly converted to the CHI interface. By arranging the protocol conversion module inside the processor cluster, the protocol conversion module can reuse the internal circuit resources of the processor cluster without using an additional bridge module, thereby saving circuit area, reducing the memory access path delay (at least 2 beats, and an estimated saving of 4 to 8 beats), and improving the overall performance of the processor cluster. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the drawings required for describing the embodiments of the present disclosure are briefly introduced below.

[0019] Figure 1 A schematic diagram of the system architecture of a chip system provided by an embodiment of the present disclosure; Figure 2 A flowchart of a read / write request processing method provided by an embodiment of the present disclosure; Figure 3 A system architecture diagram of another chip system provided by an embodiment of the present disclosure; Figure 4 A schematic diagram of the system architecture of another chip system provided by an embodiment of the present disclosure; Figure 5 A schematic diagram of a flow chart of a state machine corresponding to a cache unit processing a read and write request provided in an embodiment of the present disclosure; Figure 6 A schematic diagram of the structure of a protocol conversion module provided in an embodiment of the present disclosure; Figure 7 A schematic diagram of the structure of an electronic device provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0020] The embodiments of the present disclosure are described below in conjunction with the drawings in the present disclosure. It should be understood that the implementation methods described below in conjunction with the drawings are exemplary descriptions for explaining the technical solutions of the embodiments of the present disclosure and do not constitute a limitation on the technical solutions of the embodiments of the present disclosure.

[0021] It will be understood by those skilled in the art that, unless specifically stated, the singular forms "one", "said", and "the" used herein may also include plural forms. It should be further understood that the terms "including" and "comprising" used in the embodiments of the present disclosure refer to that the corresponding features can be implemented as the presented features, information, data, steps, operations, elements and / or components, but do not exclude the implementation as other features, information, data, steps, operations, elements, components and / or combinations thereof supported by the technical field. It should be understood that when we say that an element is "connected" or "coupled" to another element, the one element may be directly connected or coupled to the other element, or it may refer to that the one element and the other element establish a connection relationship through an intermediate element. In addition, the "connection" or "coupling" used herein may include wireless connection or wireless coupling. The term "and / or" used herein indicates at least one of the items defined by the term, for example, "A and / or B" or "A, B" indicates that it is implemented as "A", or implemented as "B", or implemented as "A and B".

[0022] In order to make the objectives, technical solutions and advantages of the present disclosure more clear, the embodiments of the present disclosure will be further described in detail below with reference to the accompanying drawings.

[0023] The following describes several exemplary embodiments to illustrate the technical solutions of the embodiments of the present disclosure and the technical effects produced by the technical solutions of the present disclosure. It should be noted that the following embodiments can refer to, draw on or combine with each other, and the same terms, similar features and similar implementation steps in different embodiments will not be described repeatedly.

[0024] Figure 1 A schematic diagram of the system architecture of a chip system provided by an embodiment of the present disclosure is shown in FIG. Figure 1 As shown, the system architecture may include a processor cluster and a downstream module, wherein the processor cluster includes at least one processor core, any processor core supports the AXI protocol (Advanced eXtensible Interface, a protocol interface) or an internal data path related to the AXI protocol, the internal data path related to the AXI protocol may be an internal data path similar to the AXI protocol, and the downstream module supports the CHI protocol. The processor also includes a protocol conversion module, the downstream module includes a NOC and a DDRC (Double Data Rate Controller), the protocol conversion module further includes a first conversion module, a processing module and a second conversion module, and the processing module reuses the internal circuit resources of the processor cluster.

[0025] Figure 2 A flowchart of a read / write request processing method provided by an embodiment of the present disclosure is shown as follows: Figure 2 As shown, the method includes: Step S110, merging at least one memory access path corresponding to each processor core into a target memory access path through a first conversion module, receiving a target read / write request transmitted by the target memory access path, splitting the target memory access path based on the requirements of the CHI protocol, and obtaining at least one first read / write request; for each first read / write request, determining a first target channel for transmitting the first read / write request, and sending the first read / write request to a processing module in the protocol conversion module through the first target channel; Step S120, allocating the first read / write request to any cache unit in the request queue module in the processing module through the processing module; sending the first read / write request to the second conversion module of the protocol conversion module through any cache unit when a preset sending condition is met; Step S130, recombining the information of the first read / write request through the second conversion module to obtain a second read / write request that complies with the CHI protocol naming; determining a second target channel for transmitting the second read / write request, and sending the second read / write request to the downstream module through the second target channel.

[0026] Specifically, in the read / write request processing method provided by the embodiment of the present disclosure, a protocol conversion module is provided in the processor, and the protocol conversion module is used to implement the conversion of the internal data channel (AXI or similar AXI) directly to the CHI interface.

[0027] Among them, the processors in the processor cluster may include NPU (Neural Processing Unit), GPU (Graphics Processing Unit), VPU (Video Processing Unit), etc. The type of processor can be specifically set according to the actual application scenario, and the embodiments of the present disclosure are not limited to this.

[0028] The read / write request processing method provided by the embodiment of the present disclosure is applied to a protocol conversion module in a processor cluster, and the protocol conversion module further includes a first conversion module, a processing module, and a second conversion module.

[0029] Any processor core supports the AMBA AXI protocol or a similar AXI protocol, and the AXI protocol includes a plurality of corresponding first preset channels: AXI AW (write address), AXI W (write data), AXI AR (read address), AXI R (read data) and AXI B (write response). When the processor is performing a data processing task, each processor core sends a read and write request to the first conversion module in the protocol conversion module through the corresponding memory access path.

[0030] The first conversion module can merge at least one memory access path corresponding to each processor core into a target memory access path, receive a target read / write request transmitted by the target memory access path, and split the original read / write request according to the 64-byte address boundary required by the CHI protocol to obtain at least one first read / write request. At the same time, for each first read / write request, the first conversion module can determine the first target channel corresponding to the transmission of the first read / write request, and send the first read / write request to the processing module in the protocol conversion module through the first target channel.

[0031] The processing module includes a request queue module. The request queue module can process read requests and write requests at the same time. The request queue module can include multiple cache units (i.e., slots). The number of cache units included in the request queue module (i.e., the depth of the request queue) is related to the number of CHI requests that the request queue module can issue in parallel. For example, when the request queue module includes 32 cache units, it means that a maximum of 32 CHI requests can be issued in parallel.

[0032] After receiving the first read / write request, the processing module may allocate any cache unit among the multiple cache units in the request queue module to the first read / write request, and the cache unit may send the first read / write request to the second conversion module when detecting that the preset sending condition corresponding to the first read / write request is met. The preset sending condition may be used to indicate that there will be no conflict between the first read / write request and other previously sent read / write requests.

[0033] After receiving the first read / write request, the second conversion module may reassemble the information of the first read / write request to obtain a second read / write request that complies with the naming of the CHI protocol. The CHI protocol may include a plurality of corresponding second preset channels, and the second conversion module may determine a second target channel for transmitting the second read / write request from the plurality of second preset channels of the CHI protocol, and send the second read / write request to a downstream module supporting the CHI protocol through the second target channel, thereby realizing the conversion between the AXI protocol and the CHI protocol.

[0034] The multiple second preset channels corresponding to the CHI protocol may include: CHI RX REQ (receive request), CHI RX DAT (receive data), CHI RX RSP (receive response), CHI TX RSP (send response) and CHI TX DAT (send data).

[0035] It should be noted that when the first conversion module or the second conversion module receives multiple read and write requests, after the multiple read and write requests are converted and processed, the multiple processed read and write requests can be sent sequentially according to preset rules, or the multiple processed read and write requests can be sent sequentially based on the order in which the multiple read and write requests are received. The embodiments of the present disclosure are not limited to this.

[0036] In the disclosed embodiment, a protocol conversion module is built into the processor cluster, and the original read / write request is converted into a first read / write request that complies with the CHI protocol through the first conversion module in the protocol conversion module, and a corresponding transmission channel is allocated for the first read / write request. The processing module sends the received first read / write request in an orderly manner, and the second conversion module renames the first read / write request to a second read / write request that symbolizes the CHI protocol, and a corresponding channel is allocated for the second read / write request. The protocol conversion module enables the internal data channel (AXI or similar AXI) in the processor cluster to be directly converted to the CHI interface. By setting the protocol conversion module inside the processor cluster, the protocol conversion module can reuse the internal circuit resources of the processor cluster without the need to use an additional bridge module, thereby saving circuit area, reducing the memory access path delay (at least 2 beats, and an estimated saving of 4 to 8 beats), and improving the overall performance of the processor cluster.

[0037] As an optional embodiment, Figure 3 A system architecture diagram of a chip system provided by an embodiment of the present disclosure, such as Figure 3 As shown, the processing module includes a write data cache module, a request queue module and a read data cache module; the processor cluster includes an original write data cache module, an original request queue module and an original read data cache module; the write data cache module reuses the circuit resources of the original write data cache module, the request queue module reuses the circuit resources of the original request queue module, and the read data cache module reuses the circuit resources of the original read data cache module.

[0038] Specifically, the processor cluster itself has an original write data cache module, an original request queue module and an original read data cache module. That is to say, even if the existing bridge module is used to convert to the CHI protocol, the processor cluster will include these three modules: the original write data cache module, the original request queue module and the original read data cache module.

[0039] In the disclosed embodiment, since the protocol conversion module is arranged in the processor cluster, the write data cache module in the processing module can reuse the circuit resources of the original write data cache module in the processor cluster, the request queue module in the processing module can reuse the circuit resources of the original request queue module in the processor cluster, and the read data cache module in the processing module can reuse the circuit resources of the read data cache module in the processor cluster, thereby saving circuit area, reducing memory access path delay (at least 2 beats, and an estimated saving of 4 to 8 beats), and improving the overall performance of the processor.

[0040] It should be noted that the write data cache module, request queue module and read data cache module in the protocol conversion module in the embodiment of the present disclosure reuse the circuit resources of the corresponding modules in the processor cluster, and will not reuse the logic of the original modules in the processor cluster.

[0041] As an optional embodiment, the method further includes: For each cache unit in the request queue module, the cache unit stores an access address corresponding to each first read / write request received; When a preset sending condition is met, the cache unit sends the first read / write request to the second conversion module in the protocol conversion module, including: If the cache unit determines that there is no address conflict based on the access address of the first read / write request, the first read / write request is sent to the second conversion module, so that the second conversion module sends the first read / write request to a downstream module.

[0042] Specifically, for each cache unit in the request queue module, the cache unit may store the access address corresponding to each first read / write request received.

[0043] After receiving the first read-write request sent by the first conversion module, the request queue module can allocate a cache unit for the first read-write request. When receiving the first read-write request, the cache unit can determine whether there is an address conflict for the first read-write request based on the access address corresponding to the first read-write request, that is, whether other read-write requests that have been sent access the same address as the first read-write request. If it is detected that there is no address conflict for the first read-write request, the first read-write request is sent to the second conversion module. The second conversion module reassembles the information of the first read-write request to obtain a second read-write request named in accordance with the CHI protocol, and determines the second target channel for transmitting the second read-write request by arbitrating and distributing the second read-write request, and sends the second read-write request to the downstream module through the second target channel.

[0044] Optionally, it is possible to detect whether there is an address conflict in the first read / write request based on a linked list, and multiple cache units can be used to construct a linked list based on the same address, each linked list represents a corresponding address conflict, and each cache unit includes the position information of the first read / write request processed by the corresponding cache unit in the linked list and the identifier (slot ID) corresponding to the next cache unit, and the position information includes whether the first read / write request processed by the cache unit is the head of the linked list, whether it is the tail of the linked list, etc. When the first read / write request processed by any cache unit is at the head of the linked list, it can be determined that there is no address conflict, and the first read / write request can be sent.

[0045] In the embodiment of the present disclosure, the access address of the received first read / write request is saved by a cache unit, and whether there is an address conflict is determined based on the access address. When it is determined that there is no address conflict for the first read / write request, the first read / write request is sent, thereby ensuring the orderly sending of multiple read / write requests.

[0046] As an optional embodiment, sending the first read / write request to the second conversion module includes: If the cache unit determines that the first read / write request is a write request, after receiving a write data ready notification for the first read / write request sent by the write data cache module, the first read / write request is sent to the second conversion module.

[0047] Specifically, for any cache unit, after receiving the first read / write request, the cache unit can also determine the type of the first read / write request. If the first read / write request is detected to be a read request, the first read / write request can be sent to the downstream module when it is determined that the first read / write request has no address conflict.

[0048] If it is detected that the first read-write request is a write request, it is necessary not only to determine that the first read-write request has no address conflict, but also to receive the write data ready notification sent by the write cache module for the first read-write request, which means that the write data corresponding to the first read-write request is ready. Only when the above two conditions are met can the first read-write request be sent to the second conversion module, and then to the downstream module through the second conversion module.

[0049] That is, when the write data cache module receives complete write data corresponding to a write request, it can send a write data ready notification corresponding to the write data to the request queue module, wherein the write data ready notification can be used to indicate that the write data has been completely cached in the write data cache module.

[0050] As an optional embodiment, the first read / write request is sent to a downstream module, and then the method further includes: receiving, by the cache unit, a first response to a first read / write request; If the first response is a retransmission response and the number of transmission credits is detected to be greater than zero, the first read / write request is resent to the downstream module; The number of transmission credits is determined based on a credit counter in the second conversion module.

[0051] Specifically, for any cache unit, after the cache unit sends the first read / write request to the second conversion module, the second conversion module reassembles and arbitrates the first read / write request and then sends the reassembled second read / write request to the downstream module.

[0052] After receiving the second read / write request, the downstream module returns the first response corresponding to the second read / write request to the processor. The downstream module can send the first response to the second conversion module, and send the first response to the cache unit (i.e., the cache unit that processes the first read / write request) through the second conversion module. After receiving the first response, the cache unit can determine the type of the first response. If it is determined that the first response is a retransmission response, it means that the downstream module has not processed the second read / write request, and the second read / write request needs to be resent to the downstream module.

[0053] The CHI protocol is based on credit for transmission. The transmission credit number can be used to represent the number of requests that can be processed by the downstream module. A credit counter can be set in the second conversion module. The credit counter can be used to update the transmission credit number. The credit counter can update the transmission credit number according to the processing of the downstream module. For example, when the downstream module notifies that a request can be processed, the credit counter will increase the transmission credit number by 1. At the same time, when the request queue performs a retransmission operation, the credit counter will reduce the transmission credit number by 1.

[0054] When the cache unit determines that the first response is a retransmission response and detects that the number of transmission credits is greater than zero, it means that the downstream module can process the retransmission request. The first read-write request can be retransmitted. The retransmission process of the first read-write request can be found in the description of the transmission process of the first read-write request above and will not be repeated here.

[0055] In the SOC system, the data stream corresponding to the NPU / VPU is often of lower priority, while the data stream corresponding to the CPU / DPU is often of higher priority. For example, when the NPU sends a large number of read requests that are blocked in the downstream module queue, since the protocol conversion module in the processor cluster implements a retransmission mechanism, the downstream module can discard the read requests sent by the NPU, receive higher-priority read requests from the CPU, and request the NPU to retransmit the previously discarded requests when the queue is relatively idle, so as to alleviate the congestion, thereby optimizing the performance resource allocation in the system, ensuring the memory access performance of the CPU / DPU, and thus ensuring that the CPU will not cause functional abnormalities due to performance issues.

[0056] In the disclosed embodiment, the protocol conversion module in the processor cluster utilizes the retransmission mechanism of the CHI protocol and can cooperate with the processing nodes in the downstream cache consistency NOC module to implement a flow control mechanism based on the retransmission mechanism. Supporting retransmission can be an extended functional feature of the processor cluster itself, thereby enhancing the functional characteristics of the processor cluster itself based on the CHI protocol characteristics, and further optimizing the overall performance of multiple XPU IPs in the chip system when concurrently accessing memory.

[0057] As an optional embodiment, the method further includes: In the case where the first read / write request is a write request, if the first response is a write data sending identification response, a write data sending instruction is sent to a write data cache module through any cache unit, so that the write data cache module sends the write data corresponding to the write request to a downstream module; When a completion response to the write data is received, a write response to the write request is returned to the first conversion module, so that the first conversion module returns the write response to the processor core.

[0058] Specifically, for any cache unit, after the cache unit identifies a write request from a first read-write request, when it detects that the write request has no address conflict and receives a write data ready notification sent by a write data cache module, the write request can be sent to a downstream module. When the downstream module can process the write request, a write data sending identifier is returned to the processor cluster as a first response. The write data sending identifier can be used to indicate that the downstream module can execute the write request and indicate the sending of the write data corresponding to the write request. For example, the identifier corresponding to the write data can be used as a write data sending identifier. When the first response returned by the downstream module received by the cache unit is a write data sending identification response, the write data sending instruction can be sent to the write data cache module. When the write data cache module receives the write data sending instruction, the write data indicated by the write data sending instruction is sent to the second conversion module. The second conversion module sends the write data to the downstream module through the data sending channel (CHI TX DAT) in the CHI protocol.

[0059] After receiving the write data, the downstream module can perform a write operation based on the write data. After completing the write operation, the completion response can be returned to the second conversion module. The second conversion module sends the completion response to the cache unit. After the cache unit receives the completion response of the write request, it returns the write response corresponding to the write request to the first conversion module and releases the cache unit for subsequent read and write requests. The first conversion module sends the write response to the processor core through the response channel (AXI B) in the AXI protocol to notify the processor core that the write request has been completed.

[0060] As an optional embodiment, the method further includes: In the case where the first read / write request is a read request, if the first response includes read data corresponding to the read request, the read data returned by the downstream module is received through the read data cache module, and the received read data is cached.

[0061] Specifically, for any cache unit, after the cache unit identifies the first read-write request as a read request, when it detects that the read request has no address conflict, the read request can be sent to the downstream module. After the downstream module reads the read data corresponding to the read request, the read data can be returned to the processor as a first response.

[0062] When the first response returned by the downstream module is read data, the cache unit receives the read data sent by the downstream module through the read data cache module and caches the received read data. The cache unit can be released for subsequent read and write requests.

[0063] As an optional embodiment, the method further includes: For each cache unit in the request queue module, the cache unit stores a transmission identifier corresponding to each first read / write request received; After caching the received read data, it also includes: The read data cache module obtains the transmission identifiers corresponding to each cache unit respectively stored therein from the request queue module, determines the read data sending order based on the transmission identifiers corresponding to each cache unit respectively stored therein, and sends at least one cached read data in sequence to the first conversion module according to the read data sending order, so that the first conversion module returns each read data to the processor in sequence.

[0064] Specifically, for each cache unit in the request queue module, the cache unit may store a transmission identifier corresponding to each received first read / write request.

[0065] Before the read data cache module sends the read data, it can obtain the transmission identifiers corresponding to each cache unit respectively saved from the request queue module, determine the read data sending order based on the transmission identifiers corresponding to each cache unit respectively saved, and send at least one cached read data in sequence to the first conversion module according to the read data sending order. The first conversion module returns the read data to the processor core in sequence through the read data transmission channel (AXI R) in the AXI protocol, so that the processor core can obtain the required data.

[0066] Optionally, when the same transmission identifier appears, the sending order corresponding to different requests with the same transmission identifier can be obtained based on the linked list, and the sending order corresponding to these multiple requests is used as the sending order of the corresponding read data.

[0067] In addition, when the original read / write request is a read request, the first conversion module splits the original read request into multiple first read requests, and for the read data corresponding to the multiple first read requests, the read data cache module can return the read data corresponding to the multiple first read requests to the upstream processor core in sequence. For example, if the original read request is A, which is split into two first read requests A0 and A1, the read data cache module can first send the read data corresponding to A0, and then send the read data corresponding to A1.

[0068] In the disclosed embodiment, the transmission identifier of each received read and write request is saved by the cache unit, and the transmission identifier saved by each cache unit is obtained from the request queue module by the read data cache module, thereby determining the sending order of multiple cached read data, thereby ensuring the orderly transmission of multiple read data.

[0069] Figure 4 A schematic diagram of the system architecture of a chip system provided by an embodiment of the present disclosure is shown in FIG. Figure 4 As shown, the system architecture includes a processor, SOC NOC (i.e., an on-chip interconnect bus based on the CHI protocol) and DDRC. The processor includes a processor core and a protocol interface module. The processor supports the AXI protocol, and the SOC NOC supports the CHI protocol.

[0070] There are multiple AXI protocol channels between the processor core and the first conversion module: AXI AW (write address), AXI W (write data), AXI AR (read address), AXI R (read data) and AXI B (write response).

[0071] There are multiple CHI protocol channels between the SOC NOC and the second conversion module: CHI RX REQ (transmit request), CHI RX DAT (transmit data), CHI RX RSP (transmit response), CHI TX RSP (receive response) and CHI TX DAT (receive data).

[0072] Among them, the first conversion module can be used to perform the functions of arbitration and shaping of the AXI interface or AXI-like interface. The arbitration function includes the need to complete the arbitration function when there are multiple AXI or AXI-like channels, that is, to combine multiple channels into one channel. When there is only one AXI channel as the input channel, it is only necessary to arbitrate the reading and writing of this AXI channel; the shaping function includes splitting the read and write requests according to the 64-byte address boundary required by the CHI protocol.

[0073] The write data cache module can be used to cache the write data sent from the upstream to the downstream, and notify the request queue after receiving the complete write data corresponding to a write request. The read data cache module can be used to cache the read data sent from the downstream to the upstream, and perform order preservation processing according to the transmission identifier stored in the corresponding cache unit in the request queue. The same transmission identifier is returned to the upstream in the original order of issuance, and the read data corresponding to the split read request is continuously sent.

[0074] The second conversion module implements the CHI RN-I interface. The second conversion module contains the channels and signals in the CHI protocol, completes the arbitration and distribution of multiple cache units to each channel, and also needs to record the number of transmission credits required for retransmission. When the number of transmission credits is not 0, it means that a credit response corresponding to the retransmission request is returned. At this time, the corresponding cache unit needs to be notified to resend the request that needs to be retransmitted.

[0075] Each cache unit in the request queue module includes the transmission identifier of the corresponding downlink request to achieve the order preservation required by the CHI protocol; each cache unit stores the access address, transmission identifier, access priority and other information of the corresponding downlink request to achieve the retransmission mechanism required by the CHI protocol; each cache unit maintains a state machine, follows the transmission structure in the CHI protocol, and outputs the CHI interface signal.

[0076] Figure 5 A schematic diagram of a flow chart of a state machine corresponding to a cache unit processing a read and write request provided in an embodiment of the present disclosure, such as Figure 5 As shown, the processing flow of the state machine of the cache unit (ie, slot) for the read / write request includes: the request queue allocates any slot for receiving the read / write request, and after the slot receives the read / write request, it decodes the read / write request to obtain the corresponding request type.

[0077] When the read / write request is a write request, wait for the write data to be ready (i.e., receive notification from the write data cache module that the completed write data has been received), and wait for no address conflict, send the write request to the downstream DDRC, and wait for the corresponding response to be returned. If the received response is a retransmission response, retransmit the write request when the corresponding credit response of the downstream is returned; if the received response is a data identification response, send the write data to the downstream, wait until the corresponding comp response (i.e., completion response) is returned, return the write response to the first conversion module, and release the slot for subsequent requests to occupy.

[0078] When the read-write request is a read request, the read request is sent to the downstream while waiting for no address conflict. If the corresponding response received is a retransmission response, the read request is retransmitted while waiting for the corresponding credit response from the downstream to return. If read data corresponding to the read request is received, the read data is returned to the first conversion module, and the slot is released for subsequent requests to occupy.

[0079] It should be noted that, in order to meet the needs of certain application scenarios, the request queue module can be further divided into a read request queue module and a write request queue module. The state machine of the slot in the read request queue module executes Figure 5 In the method for read requests, the state machine of the slot in the write request queue module executes Figure 5 Method for write requests in .

[0080] It should be noted that in the embodiment of the present disclosure, the request queue module in the protocol conversion module can reuse the circuit resources in the request queue module in the processor cluster, but each cache unit in the request queue module in the protocol conversion module executes Figure 5 The provided method, that is, each cache unit in the request queue module in the protocol conversion module does not reuse the logic of the request queue module in the processor cluster.

[0081] like Figure 4 As shown, when the DDRC core supports the AXI protocol, based on the read and write request processing method provided in any embodiment of the present disclosure, a CHI HN-I module can be set accordingly to realize the functions of retransmission and arbitration, wherein a retransmission calculator can also be set to record the number of retransmissions, and a downstream write data cache module, a downstream request queue module, a downstream read data cache module and an AXI interface or an arbitration shaping module of an AXI-like interface can be set to realize the conversion between the CHI protocol and the AXI protocol.

[0082] In the disclosed embodiment, by setting a protocol conversion module in the XPU peripheral IP, the XPU peripheral IP implements the CHI protocol interface, so that it can directly access the cache consistency NOC, replacing the current cascading method through the bridge module, thereby bringing benefits such as circuit area and memory access latency, and utilizing the CHI protocol characteristics to further optimize resource allocation in the SOC system.

[0083] Figure 6 A schematic diagram of the structure of a protocol conversion module provided in an embodiment of the present disclosure is shown in FIG. Figure 6 As shown, the module includes: The first conversion module 210 is used to merge at least one memory access path corresponding to each processor core into a target memory access path, receive a target read / write request transmitted by the target memory access path, split the target read / write request based on the requirements of the CHI protocol, and obtain at least one first read / write request; for each first read / write request, determine a first target channel for transmitting the first read / write request, and send the first read / write request to the processing module in the protocol conversion module through the first target channel; The processing module 220 is used to assign the first read / write request to any cache unit in the request queue module in the processing module; and send the first read / write request to the second conversion module through any cache unit when a preset sending condition is met; The second conversion module 230 is used to recombine the information of the first read / write request to obtain a second read / write request named in accordance with the CHI protocol; determine a second target channel for transmitting the second read / write request, and send the second read / write request to the downstream module through the second target channel.

[0084] As an optional embodiment, the processing module includes a write data cache module, a request queue module and a read data cache module; the processor cluster includes an original write data cache module, an original request queue module and an original read data cache module; The write data cache module reuses the circuit resources of the original write data cache module, the request queue module reuses the circuit resources of the original request queue module, and the read data cache module reuses the circuit resources of the original read data cache module.

[0085] As an optional embodiment, the cache unit is further used to: store the access address corresponding to each received first read / write request; If it is determined based on the access address of the first read / write request that there is no address conflict, the first read / write request is sent to the second conversion module, so that the second conversion module sends the first read / write request to the downstream module.

[0086] As an optional embodiment, the cache unit is further used to: if it is determined that the first read / write request is a write request, after receiving a write data ready notification for the first read / write request sent by the write data cache module, send the first read / write request to the second conversion module.

[0087] As an optional embodiment, the cache unit is further configured to: receiving a first response to the first read / write request; If the first response is a retransmission response and it is detected that the number of transmission credits is greater than zero, resending the first read / write request to the downstream module; The transmission credit quantity is determined based on a credit counter in the second conversion module.

[0088] As an optional embodiment, the cache unit is further configured to: In the case where the first read / write request is a write request, if the first response is a write data sending identification response, a write data sending instruction is sent to a write data cache module through any cache unit, so that the write data cache module sends the write data corresponding to the write request to the downstream module; When a completion response to the write data is received, a write response corresponding to the write request is returned to the first conversion module, so that the first conversion module returns the write response to the processor core.

[0089] As an optional embodiment, the cache unit is further configured to: In the case where the first read-write request is a read request, if the first response includes read data corresponding to the read request, the read data returned by the downstream module is received through the read data cache module, and the received read data is cached.

[0090] As an optional embodiment, the cache unit is further configured to: Saving a transmission identifier corresponding to each first read / write request received; The read data cache module is also used to obtain the transmission identifiers corresponding to each cache unit respectively saved in the request queue module, determine the read data sending order based on the transmission identifiers corresponding to each cache unit respectively saved in the cache unit, and send at least one cached read data in sequence to the first conversion module according to the read data sending order, so that the first conversion module returns each read data to the processor in sequence.

[0091] The device of the embodiment of the present disclosure can execute the method provided by the embodiment of the present disclosure, and its implementation principle is similar and has corresponding technical effects. The actions performed by each module in the device of each embodiment of the present disclosure correspond to the steps in the method of each embodiment of the present disclosure. For the detailed functional description of each module of the device, please refer to the description in the corresponding method shown in the previous text, which will not be repeated here.

[0092] In the embodiments of the present disclosure, the term "module" or "unit" refers to a computer program or a part of a computer program that has a predetermined function and works together with other related parts to achieve a predetermined goal, and can be implemented in whole or in part by using software, hardware (such as processing circuits or memories), or a combination thereof. Similarly, a processor (or multiple processors or memories) can be used to implement one or more modules or units. In addition, each module or unit can be part of an overall module or unit that includes the function of the module or unit.

[0093] In an embodiment of the present disclosure, an electronic device is provided, including a memory, a processor, and a computer program stored in the memory, and the processor executes the above computer program to implement the steps of the method provided by any optional embodiment of the present disclosure. Compared with the prior art, it can be achieved that: by building a protocol conversion module in a processor cluster, the original read and write request is converted into a first read and write request that complies with the CHI protocol through a first conversion module in the protocol conversion module, and a corresponding transmission channel is allocated for the first read and write request, the processing module sends the received first read and write request in order, the second conversion module renames the first read and write request to a second read and write request of the symbol CHI protocol, and a corresponding channel is allocated for the second read and write request, the protocol conversion module enables the internal data channel (AXI or similar AXI) of the processor cluster to be directly converted to the CHI interface, and by setting the protocol conversion module inside the processor cluster, the protocol conversion module can reuse the internal circuit resources of the processor cluster without using an additional bridge module, thereby saving circuit area, reducing the memory access path delay (at least 2 beats, and an estimated saving of 4 to 8 beats), and improving the overall performance of the processor cluster.

[0094] In an alternative embodiment, an electronic device is provided, such as Figure 7 As shown, Figure 7 The electronic device 4000 shown includes: a processor 4001 and a memory 4003. The processor 4001 and the memory 4003 are connected, such as through a bus 4002. Optionally, the electronic device 4000 may also include a transceiver 4004, which may be used for data interaction between the electronic device and other electronic devices, such as data transmission and / or data reception. It should be noted that in actual applications, the transceiver 4004 is not limited to one, and the structure of the electronic device 4000 does not constitute a limitation on the embodiments of the present disclosure.

[0095] Processor 4001 may be a CPU (Central Processing Unit), a general-purpose processor, a DSP (Digital Signal Processor), an ASIC (Application Specific Integrated Circuit), an FPGA (Field Programmable Gate Array) or other programmable logic devices, transistor logic devices, hardware components or any combination thereof. It may implement or execute various exemplary logic blocks, modules and circuits described in conjunction with the disclosure of the present invention. Processor 4001 may also be a combination that implements computing functions, such as a combination of one or more microprocessors, a combination of a DSP and a microprocessor, etc.

[0096] The bus 4002 may include a path to transmit information between the above components. The bus 4002 may be a PCI (Peripheral Component Interconnect) bus or an EISA (Extended Industry Standard Architecture) bus. The bus 4002 may be divided into an address bus, a data bus, a control bus, etc. For ease of representation, Figure 7 Only one thick line is used in the diagram, but this does not mean that there is only one bus or only one type of bus.

[0097] The memory 4003 may be a ROM (Read Only Memory) or other types of static storage devices that can store static information and instructions, a RAM (Random Access Memory) or other types of dynamic storage devices that can store information and instructions, or an EEPROM (Electrically Erasable Programmable Read Only Memory), a CD-ROM (Compact Disc Read Only Memory) or other optical disk storage, optical disk storage (including compressed optical disk, laser disk, optical disk, digital versatile disk, Blu-ray disk, etc.), magnetic disk storage media, other magnetic storage devices, or any other medium that can be used to carry or store computer programs and can be read by a computer, without limitation herein.

[0098] The memory 4003 is used to store the computer program for executing the embodiment of the present disclosure, and the execution is controlled by the processor 4001. The processor 4001 is used to execute the computer program stored in the memory 4003 to implement the steps shown in the above method embodiment.

[0099] Among them, electronic devices include but are not limited to: mobile terminals such as mobile phones, laptops, digital broadcast receivers, PDAs (personal digital assistants), PADs (tablet computers), PMPs (portable multimedia players), vehicle-mounted terminals (such as vehicle-mounted navigation terminals), wearable devices, etc., and fixed terminals such as digital TVs, desktop computers, etc.

[0100] An embodiment of the present disclosure provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the steps and corresponding contents of the aforementioned method embodiment can be implemented.

[0101] The embodiments of the present disclosure also provide a computer program product, including a computer program, which can implement the steps and corresponding contents of the aforementioned method embodiments when executed by a processor.

[0102] It should be understood that, although the flowchart of the embodiment of the present disclosure indicates each operation step by arrows, the implementation order of these steps is not limited to the order indicated by the arrows. Unless clearly stated herein, in some implementation scenarios of the embodiment of the present disclosure, the implementation steps in each flowchart can be executed in other orders according to demand. In addition, some or all of the steps in each flowchart may include multiple sub-steps or multiple stages based on the actual implementation scenario. Some or all of these sub-steps or stages can be executed at the same time, and each sub-step or stage in these sub-steps or stages can also be executed at different times. In scenarios with different execution times, the execution order of these sub-steps or stages can be flexibly configured according to demand, and the embodiment of the present disclosure does not limit this.

[0103] The above is only an optional implementation method for some implementation scenarios of the present disclosure. It should be pointed out that for ordinary technicians in this technical field, without departing from the technical concept of the scheme of the present disclosure, other similar implementation methods based on the technical ideas of the present disclosure are also within the protection scope of the embodiments of the present disclosure.

Claims

1. A method for processing a read / write request, characterized in that: A protocol conversion module applied to a processor cluster, the processor cluster further comprising at least one processor core, the protocol conversion module being connected to a downstream module, any processor core supporting an AXI protocol or an internal data path associated with the AXI protocol, the downstream module supporting a CHI protocol; the protocol conversion module comprising a first conversion module, a processing module, and a second conversion module, the processing module reusing internal circuit resources of the processor cluster; The method comprises: By means of the first conversion module, at least one memory access path corresponding to each processor core is merged into a target memory access path, a target read / write request transmitted by the target memory access path is received, and the target read / write request is split based on the requirements of the CHI protocol to obtain at least one first read / write request; for each first read / write request, a first target channel for transmitting the first read / write request is determined, and the first read / write request is sent to a processing module in the protocol conversion module through the first target channel; Allocate the first read / write request to any cache unit in the request queue module in the processing module through the processing module; send the first read / write request to the second conversion module through any cache unit when a preset sending condition is met; The information of the first read / write request is reassembled through the second conversion module to obtain a second read / write request named in accordance with the CHI protocol; a second target channel for transmitting the second read / write request is determined, and the second read / write request is sent to the downstream module through the second target channel.

2. The method according to claim 1, characterized in that: The processing module includes a write data cache module, a request queue module and a read data cache module; the processor cluster includes an original write data cache module, an original request queue module and an original read data cache module; The write data cache module reuses the circuit resources of the original write data cache module, the request queue module reuses the circuit resources of the original request queue module, and the read data cache module reuses the circuit resources of the original read data cache module.

3. The method according to claim 1, characterized in that The method further comprises: For each cache unit in the request queue module, the cache unit stores an access address corresponding to each first read / write request received; The step of sending the first read / write request to the second conversion module in the protocol conversion module by any of the cache units when a preset sending condition is met includes: If any cache unit determines that there is no address conflict based on the access address of the first read / write request, the first read / write request is sent to the second conversion module, so that the second conversion module sends the first read / write request to the downstream module.

4. The method according to claim 3, characterized in that The sending the first read / write request to the second conversion module includes: If it is determined by any cache unit that the first read / write request is a write request, after receiving a write data ready notification for the first read / write request sent by a write data cache module, the first read / write request is sent to the second conversion module.

5. The method according to claim 3, characterized in that: The sending of the first read / write request to the downstream module further includes: Receiving a first response to the first read / write request through any cache unit; If the first response is a retransmission response and it is detected that the number of transmission credits is greater than zero, resending the first read / write request to the downstream module; The transmission credit quantity is determined based on a credit counter in the second conversion module.

6. The method according to claim 5, characterized in that The method further comprises: In the case where the first read / write request is a write request, if the first response is a write data sending identification response, a write data sending instruction is sent to a write data cache module through any cache unit, so that the write data cache module sends the write data corresponding to the write request to the downstream module; When a completion response to the write data is received, a write response corresponding to the write request is returned to the first conversion module, so that the first conversion module returns the write response to the processor core.

7. The method according to claim 5, characterized in that The method further comprises: In the case where the first read-write request is a read request, if the first response includes read data corresponding to the read request, the read data returned by the downstream module is received through the read data cache module, and the received read data is cached.

8. The method according to claim 7, characterized in that Said also includes: For each cache unit in the request queue module, the cache unit stores a transmission identifier corresponding to each first read / write request received; The received read data is cached, and then further comprises: The read data cache module obtains the transmission identifiers corresponding to each cache unit respectively stored therein from the request queue module, determines the read data sending order based on the transmission identifiers corresponding to each cache unit respectively stored therein, and sends at least one cached read data in sequence to the first conversion module according to the read data sending order, so that the first conversion module returns each read data to the processor in sequence.

9. A protocol conversion module, characterized in that: include: A first conversion module is used to merge at least one memory access path corresponding to each processor core into a target memory access path, receive a target read / write request transmitted by the target memory access path, split the target read / write request based on the requirements of the CHI protocol, and obtain at least one first read / write request; for each first read / write request, determine a first target channel for transmitting the first read / write request, and send the first read / write request to the processing module in the protocol conversion module through the first target channel; A processing module, configured to assign the first read / write request to any cache unit in a request queue module in the processing module; and send the first read / write request to the second conversion module through any cache unit when a preset sending condition is met; The second conversion module is used to recombine the information of the first read-write request to obtain a second read-write request named in accordance with the CHI protocol; determine a second target channel for transmitting the second read-write request, and send the second read-write request to the downstream module through the second target channel.

10. An electronic device comprising a memory, a processor and a computer program stored in the memory, characterized in that: The processor executes the computer program to implement the steps of the method according to any one of claims 1 to 8.

11. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 8 are implemented.

12. A computer program product, comprising a computer program, characterized in that When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 8 are implemented.

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