Device for synchronizing symbol clock in data transmission and transmission system

Abstract

The invention relates to a device and a transmission system for synchronizing symbol clocks during data transmission between a sender and a receiver, the device having an estimation means (30) and a symbol synchronizer (40). An estimation unit (30) receives a first signal (S1) generated by a sender (10) and estimates a phase deviation (POFF) and / or a frequency deviation (FOFF) between a symbol clock of the sender (10) and a symbol clock of a receiver (20) on the basis of the first signal, generates the first signal (S1) on the basis of the symbol clock of the sender, and analyzes and evaluates the first signal in the receiver on the basis of the symbol clock of the receiver. The device (5) initializes the symbol synchronizer (40) on the basis of the evaluated phase deviation (POFF) and / or the evaluated frequency deviation (FOFF). The symbol synchronizer (40) receives a second signal (S2) generated by the sender (10) in order to generate, on the basis of the second signal (S2), an output signal (SO) representing symbols transmitted inside the second signal (S2) synchronized with the symbol clock of the receiver (20).

Description

Technical Field

[0001] The invention relates to a device for synchronizing a symbol clock in a data transmission between a sender and a receiver and a transmission system having such a device. Background Art

[0002] Transmission systems are known from the prior art in which the sender and receiver are not synchronized for data transmission by means of a separate clock line, so that the symbol clock on the receiver side must be synchronized with respect to the symbol clock on the sender side by means of the data transmission signal itself, since the clock generators in the sender and receiver each operate independently of one another and can therefore have frequency and phase shifts relative to one another.

[0003] For this purpose, a feedback symbol synchronizer known from the prior art can be used, which usually consists of a symbol clock error detector, an adjustable interpolator, an interpolation controller and a loop filter. Such feedback symbol synchronizers have the following advantages: they can be implemented with relatively little overhead, that is, they require relatively few hardware resources and / or software resources. On the other hand, such feedback symbol synchronizers usually have a long settling time before a sufficiently accurate symbol clock synchronization is achieved due to the existing control loop. In principle, a small inherent noise of the feedback symbol synchronizer is expected. However, due to the small control bandwidth required for this, the settling time is disadvantageously increased. The settling time and the small inherent noise require a trade-off and cannot be improved simultaneously in the usual way.

[0004] In contrast, feed-forward symbol synchronizers are known which, due to the absence of a regulation loop, can achieve a comparatively faster symbol clock synchronization. However, the implementation of such feed-forward symbol synchronizers is usually associated with higher resource requirements in terms of hardware and / or software.

[0005] Rice, Michael, “Digital Communications: A Discrete-Time Approach”, Upper Saddle River, NJ: Prentice Hall, 2008” also discloses a feedback symbol synchronizer. Summary of the invention

[0006] According to a first aspect of the present invention, a device for synchronizing a symbol clock during data transmission between a sender and a receiver is provided.

[0007] It should be pointed out that the invention is particularly directed to symbol clock synchronization between a sender and a receiver, which are not synchronized with one another via a separate clock line but are instead synchronized solely on the basis of the transmitted data signal.

[0008] The device has an estimation component and a symbol synchronizer, which can be constructed from a large number of logical and / or physical subunits. In addition, the estimation component and / or the symbol synchronizer and / or their respective subunits can also be completely constructed as a software implementation and / or completely constructed as a hardware implementation and / or constructed as a combination of software implementation and hardware implementation.

[0009] Furthermore, the various implementations may also be put into practice based on one or more computing units, which may be configured as ASICs, FPGAs, processors, digital signal processors, microcontrollers, etc., for example.

[0010] According to the present invention, the estimation component is configured to receive a first signal generated by a sender (for example, a predefined data preamble set for symbol clock synchronization or a signal different therefrom) and estimate a phase offset and / or a frequency offset between a symbol clock of the sender and a symbol clock of the receiver based on the first signal, wherein the first signal is generated based on the symbol clock of the sender and is analyzed and evaluated in the receiver based on the symbol clock of the receiver.

[0011] The device is configured to initialize a symbol synchronizer configured as a feedback symbol synchronizer based on an estimated phase deviation and / or an estimated frequency deviation. The symbol synchronizer is, for example, a feedback symbol synchronizer known from the prior art, which is further configured to be initialized via a suitable interface with the aid of estimated values ​​determined for the phase deviation and / or the frequency deviation.

[0012] Here, the symbol synchronizer and the estimation component can receive the first signal in parallel, because the symbol synchronizer is reset to a defined state by initialization after the estimation of the frequency deviation and / or phase deviation is completed. In this case, it may be advantageous to reset all memory variables and / or state variables of the symbol synchronizer to the basic initialization during initialization. Alternatively, the sender's transmission signal (especially the useful signal) may be directed to the symbol synchronizer only after the initialization performed by the estimation component is completed. For this purpose, a corresponding logical and / or physical switch may be provided at the input of the symbol synchronizer.

[0013] It should be noted that, in the case where the estimation component is configured to perform both the estimation of the phase deviation and the estimation of the frequency deviation, the first subunit of the estimation component configured to estimate the phase deviation and the second subunit of the estimation component configured to estimate the frequency deviation can obtain estimated values ​​for the phase deviation and for the frequency deviation at different time points, and the initialization of the symbol synchronizer does not necessarily have to be performed after both estimated values ​​exist. Alternatively, initialization can also be performed at different time points, for example, once the corresponding estimated values ​​exist.

[0014] It should also be pointed out that it is advantageous if a processing process that is identical for two subunits within the respective signal processing chains of the subunits is performed only once for the two subunits, by providing corresponding processing process results to both subunits (regardless of whether these corresponding results are calculated in the first subunit, in the second subunit or in a component different from them), in order to save required computing and / or memory resources for the device.

[0015] In addition, the device, in particular the estimation component, can have a common estimation value selector for the first subunit and the second subunit and / or a separate estimation value selector for the first subunit and the second subunit, and the estimation value selector is configured to select respectively suitable estimation values ​​for the phase deviation and / or frequency deviation from a large number of estimation values ​​generated over a certain period of time, and these estimation values ​​are subsequently used for initialization of the symbol synchronizer.

[0016] The symbol synchronizer is configured to receive a second signal generated by the sender in order to generate an output signal based on the second signal, the output signal representing the symbol transmitted within the second signal synchronized with the symbol clock of the receiver. In other words, the second signal is configured for the actual useful data transmission between the sender and the receiver, while the first signal is preferably configured only for determining the phase deviation and / or frequency deviation, that is, for symbol clock synchronization. However, this does not explicitly exclude that the first signal may also contain useful information.

[0017] After the symbol synchronizer is initialized according to the invention, a large number of additional useful signals (e.g., a third signal, a fourth signal, etc.) can be received in a manner similar to the second signal, for example, to transmit a larger amount of data from the sender to the receiver. In addition, the corresponding first signal can be transmitted from the sender to the receiver before each useful signal (which can also be composed of a large number of fragmented individual signals) and / or according to a predefined synchronization interval and / or according to a predefined standard, in order to re-perform symbol clock synchronization.

[0018] This can be advantageous if, for example, there is a longer interruption in the transmission of the useful signal, due to which the synchronization between sender and receiver can drift relative to each other. In the case of receivers that are set up to receive useful signals from different senders, it can also be advantageous or necessary to resynchronize by means of a "first signal sent by the corresponding sender" performed upstream when data transmission changes from one sender to the next.

[0019] In summary, the device according to the present invention presents a particular advantage, namely, by initializing with the aid of an estimation component for phase deviation and / or frequency deviation, the start-up phase of the feedback symbol synchronizer can be significantly shortened compared to a conventional symbol synchronizer, thereby enabling lossless reception of a useful signal transmitted by a sender correspondingly earlier than in the prior art. In addition, the response time / reaction time in a system with such a device can be reduced, achieving reliability of data transmission, etc.

[0020] The subject matter of the present invention is also a preferred development of the present invention.

[0021] In an advantageous embodiment of the invention, the estimation component is constructed as a feedforward estimation component, because in this way, a particularly resource-saving and / or fast estimation of the phase deviation and / or the frequency deviation can be performed. In particular, when a feedforward estimation component is used, the processing time for estimating the phase deviation and / or the frequency deviation may be shorter than the symbol synchronizer start-up time until a synchronous symbol clock is reached between the sender and the receiver when the symbol synchronizer is initialized without the aid of the estimation component. This explicitly does not exclude that an estimation component based on a feedback structure can also achieve a shorter start-up time than a symbol synchronizer that is not initialized according to the invention.

[0022] The first signal is particularly preferably a predefined synchronization signal, which may also be referred to as a pre-synchronization code or a training signal, for example. In this way, the first signal can be advantageously matched to the characteristics of the corresponding implementation of the estimation component in terms of the symbol sequence and / or the number of symbols contained. When the predefined first signal of the device is known, it can also be achieved that a suitable selection time point for the corresponding estimated value of the estimated value selector that may exist is obtained in accordance with the first signal. This explicitly does not exclude that the estimation component can also achieve a favorable estimate of the phase deviation and / or frequency deviation based on a non-predefined first signal (for example, based on a random data signal and / or a useful signal). It is also preferred that the symbol rate of the first signal is equal to or less than the carrier frequency set for transmitting the first signal and the second signal.

[0023] In another advantageous embodiment of the invention, the estimation component is configured to estimate the phase deviation by converting sample values ​​representing the first signal (which are preferably generated from the first signal by an A / D converter of the device and / or the receiver) into complex sample values ​​by means of an IQ demodulation preferably known from the prior art, whose reference frequency corresponds to the symbol clock of the receiver, in particular to the carrier frequency described, by determining the respectively corresponding phase deviation value for each complex sample value and determining the time offset values ​​corresponding to these phase deviation values ​​between the symbol clock of the sender and the symbol clock of the receiver based on the respectively determined phase deviation values. These time offset values ​​can then be used in the symbol synchronizer in order to determine suitable new sampling time points (preferably at the subsampling level) for the first signal, for example in the interpolator. In this regard, it should be pointed out that the sampling rate of the sample values ​​can advantageously represent oversampling relative to the symbol rate, wherein the sampling rate can further advantageously be converted (in particular reduced) to the target sampling rate during or at the end of the processing chain of the estimation component and / or the symbol synchronizer. The phase deviation is determined, for example, based on an inverse tangent calculation applied to the complex sample values. Furthermore, depending on the specific implementation of the respective phase deviation estimation, further signal processing steps may be provided in order to carry out suitable scaling and / or range shifting of the result, for example within the processing chain.

[0024] Alternatively or additionally, the estimation component can advantageously be configured to estimate the frequency deviation by converting the sample values ​​representing the first signal into complex sample values ​​by means of an IQ demodulation corresponding to the symbol clock of the receiver with its reference frequency, by determining the phase deviation value corresponding to each complex sample value, by avoiding jumps caused by overflow between successive phase deviation values ​​(that is, when exceeding the value range provided for the phase deviation value, for example, from -π to +π) (i.e., unwrapping), by converting the phase deviation values ​​into a continuously extending variation curve of the phase deviation values ​​and calculating the changes between the successive converted phase deviation values, which represent the corresponding frequency deviation. With regard to the sampling rate and the possible oversampling, reference is made to the above description on determining the phase deviation, which description is also applicable in this respect when determining the frequency deviation. With regard to the possible phase deviation calculation and, if necessary, further processing steps, reference is also made to the above description on determining the phase deviation.

[0025] In another advantageous embodiment of the present invention, the device is configured to determine a time point at which the estimated value for the phase deviation and / or frequency deviation currently determined in the estimation component is selected for initialization of the symbol synchronizer, based on the reception time point of the first signal and / or the duration of the first signal and / or the processing duration for estimating the phase deviation and / or the frequency deviation and / or the minimum accuracy requirement for the estimated phase deviation and / or the frequency deviation. For this purpose, for example, the estimated value selector described above can be used.

[0026] Particularly preferably, the estimation component additionally has at least one filter, in particular a low-pass filter, which is configured to reduce the noise contained in the first signal. Such filtering can be performed, for example, after the corresponding IQ demodulation is performed in the first subunit and / or the second unit of the estimation component and before the corresponding phase information is calculated based on the complex sampled values. Such a filter can be constructed, for example, as a filter with a sliding average value, which advantageously calculates an average value with respect to a predefined number of sampled values, which is equal to or less than the number of sampled values ​​representing the entire first signal. Alternatively or additionally, in a processing chain for estimating frequency deviation, filtering can be set directly before calculating the variation between successive converted phase deviation values. Alternatively or additionally, filtering can be set at another position in the corresponding processing chain for estimating phase deviation and / or frequency deviation, and / or filtering different from filtering with a sliding average value can be used.

[0027] According to a second aspect of the invention, a transmission system having a sender and a receiver is provided, wherein the receiver comprises a device according to the first inventive aspect. The sender is configured to generate a first signal and a second signal (and preferably another signal containing a useful signal) based on a symbol clock of the sender and transmit these signals to the receiver. The receiver is configured to receive symbols representing data from the sender based on the first signal and the second signal. These features, feature combinations and the advantages derived therefrom obviously correspond to what has been explained in conjunction with the first-mentioned inventive aspect, so that reference can be made to the above explanations in order to avoid repetitions.

[0028] In an advantageous configuration of the transmission system according to the present invention, the transmission system has at least two senders, which are respectively configured to generate at least a first signal and a corresponding second signal and transmit these signals to a receiver in a non-conflicting manner (for example, by means of a time multiplexing method, or by means of a multiplexing method different from the ratio), and the receiver is configured to receive symbols representing data from the corresponding sender based on the corresponding first signal and the second signal.

[0029] The transmission system according to the invention is, for example, an ultrasonic system and / or a radar system, and / or a vehicle system and / or a power line transmission system and / or a baseband transmission system and / or a transmission system different therefrom. In the case where the transmission system is, for example, an ultrasonic system of a vehicle, a large number of ultrasonic sensors arranged in the vehicle, which act as senders in the sense of the invention here (these ultrasonic sensors are arranged, for example, in the front area and / or the rear area of ​​the vehicle) can be connected to a central controller which acts as a receiver in the sense of the invention via a network on information technology. This does not exclude that bidirectional communication can also be provided between the ultrasonic sensors and the central controller. In this case, all participants in the transmission system advantageously utilize the device according to the invention. It is known in conjunction with such ultrasonic systems that the individual ultrasonic sensors transmit data to the central controller in sequence by a time multiplexing method. Since the individual ultrasonic sensors usually do not use a common clock basis, the device according to the invention can be particularly advantageously used in such ultrasonic systems for such data communication, because according to the invention, the corresponding symbol clock of the sender can be matched particularly quickly in the receiver, thereby also enabling a short reaction time to be achieved when performing environmental detection based on the ultrasonic system. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] The embodiments of the present invention are described in detail below with reference to the accompanying drawings. In the accompanying drawings:

[0031] Figure 1 A block diagram showing an embodiment of the transmission system according to the invention having the device according to the invention;

[0032] Figure 2 A block diagram showing an embodiment of an estimation component for estimating a phase deviation according to the present invention;

[0033] Figure 3 A block diagram showing an embodiment of an estimation component for estimating a frequency deviation according to the present invention; and

[0034] Figure 4 A block diagram showing an embodiment of a sampling value selector according to the present invention is shown. DETAILED DESCRIPTION

[0035] Figure 1 The block diagram shows an exemplary embodiment of the transmission system according to the invention having the device 5 according to the invention, wherein the device 5 is represented by a computing unit which implements the functional blocks of the device 5 described below on the basis of a computer program executed by the computing unit.

[0036] The device 5 is configured to synchronize the symbol clock when data is transmitted between the first sender 10, the second sender 10' and the receiver 20, wherein the device 5 is arranged in the receiver 20. The senders 10, 10' are ultrasonic sensors of the vehicle's environment detection system, respectively, and these senders are connected to the receiver 20 by wire, and the receiver is a central controller of the vehicle for receiving and analyzing the environment information detected by the ultrasonic sensor.

[0037] It is pointed out that for the sake of clarity, further components of the receiver 20 which are provided, for example, for preprocessing and / or postprocessing of data received by means of a data transmission between the sender 10 , 10 ′ and the receiver 20 , are not shown and described here.

[0038] The device 5 has an estimation component 30 and a symbol synchronizer 40, wherein the estimation component 30 is configured to receive the first signals S1 generated by the senders 10, 10' respectively without overlapping in time, and to estimate the phase deviation POFF and frequency deviation FOFF between the respective symbol clocks of the senders 10, 10' (based on which the corresponding first signal S1 is generated) and the symbol clock of the receiver 20 (based on which the first signal S1 is evaluated in the receiver 20) based on the first signal S1. The first signal S1 is designed here as a predefined preamble whose symbol rate is equal to or less than the carrier frequency provided for transmitting the first signal S1.

[0039] For this purpose, the estimation component 30 has a first subunit 32 configured to determine the phase deviation POFF and a second subunit 34 configured to determine the frequency deviation FOFF. In addition, the estimation component 30 has an estimated value selector 36 configured to determine a time point TS at which the estimated values ​​for the phase deviation POFF and the frequency deviation FOFF currently present in the subunits 32, 34 are suitable for initializing the symbol synchronizer 40.

[0040] Furthermore, the device 5 is designed to initialize the symbol synchronizer 40 , which is designed here as a conventional feedback symbol synchronizer 40 , based on the estimated phase deviation POFF and the estimated frequency deviation FOFF.

[0041] The symbol synchronizer 40 is configured to receive a second signal S2 generated by the first transmitter 10 and a second signal S2' generated by the second transmitter 10' so as to generate corresponding output signals SO, SO' based on the second signals S2, S2', which output signals represent symbols transmitted within the second signals S2, S2' synchronized with the symbol clock of the receiver 20.

[0042] It should be pointed out that for the sake of clarity, the A / D converter (and possibly further preprocessing units) of the device 5, which converts the signals S1, S2, S2' transmitted in analog form by the sender 10, 10' into digital signals S1, S2, S2' for further processing within the device 5, is not shown here. Preferably, such an A / D converter is connected in such a way that it supplies the converted signals S1, S2, S2' both to the symbol synchronizer 40 and to the estimation component 30.

[0043] The symbol synchronizer 40 has the following components: an adaptable interpolator 90, into which the signals S1, S2, S2' of the sender 10, 10' are fed; a sampling value selector 130, by which the sampling value which is most suitable for representing the corresponding symbol is selected from a large number of sampling values ​​for each transmitted symbol (that is, there is an oversampling of the individual symbols here). The selection is preferably carried out in such a way that the sampling value with the highest signal-to-noise ratio in terms of signal amplitude is selected for each symbol.

[0044] Furthermore, the symbol synchronizer 40 has a symbol clock error detector 110 which is configured to calculate a symbol clock deviation between the respective symbol clock of the sender 10 , 10 ′ and the symbol clock of the receiver 20 based on an algorithm known from the prior art.

[0045] Furthermore, the symbol synchronizer 40 has a loop filter 120 which is implemented on the basis of a PI controller and which is provided according to the invention to be initialized with the aid of a frequency offset value FOFF.

[0046] Finally, the symbol synchronizer 40 also has an interpolation control device 100, which is configured according to the present invention to be initialized by means of a phase offset value or by means of a time offset value POFF corresponding to the phase offset value and to control the interpolator 90 and the sampling value selector 130 in a manner known from the prior art.

[0047] Figure 2 A block diagram of an embodiment of an estimation component 30 for estimating a phase deviation POFF according to the present invention is shown, wherein this part of the estimation component 30 represents the estimation component 30 in Figure 1 The first subunit 32 described in .

[0048] As in Figure 1 The first signal S1 described in the figure is an oversampled discrete signal which is fed into a component 50 for IQ demodulation known from the prior art, the reference frequency of which corresponds to the symbol clock of the receiver 20, so as to convert the real sample values ​​representing the first signal S1 into complex sample values ​​60 represented by I-data I and Q-data Q respectively.

[0049] The complex sample values ​​60 are then fed to a low-pass filter 80 implemented as a sliding average filter in order to reduce undesired noise components contained in the complex sample values ​​60 .

[0050] Subsequently, based on an inverse tangent calculation (arctan(I / Q)), a corresponding phase offset value POFF is determined from the complex sample values ​​60 , which is initially represented by a value range of −π to +π.

[0051] The phase offset value POFF is then scaled by a factor of −1 / π in order to convert the phase offset value POFF into the value range of −1 to +1.

[0052] Through the subsequent modulo calculation mod(x+2,2), the corresponding scaled phase deviation value POFF is shifted to the value range of 0 to +2, where x represents the corresponding scaled phase deviation value POFF.

[0053] After the modulo calculation, the phase offset value POFF is subsequently scaled by means of the factor Ts / (2K) to a value range between 0 and Ts, wherein K corresponds to the number of sample values ​​per symbol and Ts corresponds to the symbol time interval.

[0054] Finally, based on a plurality of phase offset values ​​POFF determined successively in time, a phase offset value POFF suitable for initializing the symbol synchronizer 40 is selected. Figure 1 described in Figure 1 And subsequently in Figure 4 This selection is made at the time point TS determined by the estimated value selector 36 described in .

[0055] Figure 3 A block diagram of an embodiment of an estimation component 30 for estimating a frequency deviation FOFF according to the present invention is shown, wherein this part of the estimation component 30 represents the estimation component 30 in Figure 1 The second subunit 34 described in .

[0056] As in Figure 1 The first signal S1 described in the figure is an oversampled discrete signal which is fed into a component 50 for IQ demodulation known from the prior art, the reference frequency of which corresponds to the symbol clock of the receiver 20, so as to convert the real sample values ​​representing the first signal S1 into complex sample values ​​60 represented by I-data I and Q-data Q, respectively.

[0057] The complex sample values ​​60 are then fed to a low-pass filter 80 implemented as a sliding average filter in order to reduce undesired noise components contained in the complex sample values ​​60 .

[0058] Subsequently, based on an inverse tangent calculation (arctan(I / Q)), a corresponding phase offset value POFF is determined from the complex sample values ​​60 , which is initially represented by a value range of −π to +π.

[0059] In the subsequent unwrapper 70 , jumps between successive phase deviation values ​​POFF at the value range boundary due to overflow are avoided by converting the phase deviation POFF into a continuously extending profile of the phase deviation POFF within a correspondingly enlarged value range.

[0060] The converted phase deviation POFF is subsequently scaled by a factor of −K / 2π, wherein K corresponds to the number of sampling values ​​per symbol.

[0061] To further reduce noise, Figure 3 In the processing chain of , a further filter 80 is provided, which can be implemented, for example, identically to or differently from the filtering in the preceding filter 80 of the block diagram.

[0062] In the subsequent processing steps in the processing chain, the sampled values ​​processed as above are differentiated by subtracting the respective successive sampled values ​​from one another. For this purpose, a delay element Z with negative feedback is provided. -1 By means of the delay element, the respectively preceding sampling value is subtracted from the respectively currently processed sampling value. The variation between the successively converted phase deviations POFF determined in this way represents the corresponding frequency deviation FOFF.

[0063] Finally, a frequency offset value FOFF suitable for initializing the symbol synchronizer 40 is selected from a plurality of frequency offset values ​​FOFF determined successively in time. Figure 1 described in Figure 1 And subsequently in Figure 4 This selection is made at the time point TS determined by the estimated value selector 36 described in .

[0064] Figure 4 A block diagram showing an embodiment of a sampling value selector 130 according to the present invention is shown. The sampling value selector 130 is described above. Figures 1 to 3 The sampling value selector 130 is configured as follows.

[0065] As in Figure 1The first signal S1 described in the figure is an oversampled discrete signal which is fed into a component 50 for IQ demodulation known from the prior art, the reference frequency of which corresponds to the symbol clock of the receiver 20, so as to convert the real sample values ​​representing the first signal S1 into complex sample values ​​60 represented by I-data I and Q-data Q, respectively.

[0066] exist Figure 4 In the subsequent blocks of the block diagram in , the absolute value square of the corresponding complex sample value 60 is calculated.

[0067] The absolute value squared value is then fed to a low-pass filter 80 implemented as a sliding average filter in order to reduce the noise component contained in the absolute value squared value.

[0068] The corresponding output value from the low-pass filter 80 is compared in a block of a threshold value comparison 140 with a predefined threshold value, wherein the threshold value is determined in such a way that exceeding the threshold value marks the beginning of the corresponding first signal S1 .

[0069] The time point TS described in the above figure is obtained from the starting time point of the first signal S1 by means of the delay unit 150 arranged later, in that the processing time length according to the estimation component 30 (see Figure 1 , 2 and 3) and a delay time determined according to the duration of the first signal S1.

Claims

1. A device (5) for synchronizing a symbol clock when data is transmitted between a sender (10) and a receiver (20), the device comprising: - an estimation component (30), and - a symbol synchronizer (40), in, The estimation component (30) is configured to: - receiving a first signal (S1) generated by said sender (10), and - estimating a phase offset (POFF) and / or a frequency offset (FOFF) between a symbol clock of the sender (10) and a symbol clock of the receiver (20) based on the first signal, The first signal (S1) is generated based on the symbol clock of the sender, and the first signal (S1) is analyzed and evaluated in the receiver (20) based on the symbol clock of the receiver. - the device (5) is configured to initialize the symbol synchronizer (40) configured as a feedback symbol synchronizer (40) based on the estimated phase deviation (POFF) and / or the estimated frequency deviation (FOFF), and - the symbol synchronizer (40) is arranged to receive a second signal (S2) generated by the sender (10) in order to generate an output signal (SO) based on the second signal (S2), which output signal represents the symbols transmitted within the second signal (S2) synchronized with the symbol clock of the receiver (20).

2. The device according to claim 1, wherein: - the estimation component (30) is a feed-forward estimation component (30), and / or - The processing time for estimating the phase deviation (POFF) and / or the frequency deviation (FOFF) is shorter than the start-up time of the symbol synchronizer (40) until a synchronized symbol clock is reached between the sender (10) and the receiver (20) when the symbol synchronizer (40) is initialized without the aid of the estimation component (30).

3. The device (5) according to any one of the preceding claims, wherein: The first signal (S1) is a predefined synchronization signal, and / or The symbol rate of the first signal (S1) is equal to or lower than a carrier frequency set for transmitting the first signal (S1) and the second signal (S2).

4. The device (5) according to any one of the preceding claims, wherein: The estimation means (30) is arranged to estimate the phase deviation (POFF) in such a way that: - converting the sampled values ​​representing the first signal (S1) into complex sampled values ​​(60) by means of IQ demodulation (50), the reference frequency of the IQ demodulation corresponding to the symbol clock of the receiver (20), - obtaining a corresponding phase deviation value (POFF) for each of the complex sample values ​​(60), and - determining a time offset value corresponding to the phase offset value (POFF) between the symbol clock of the sender (10) and the symbol clock of the receiver (20) based on the respectively determined phase offset value (POFF).

5. The device (5) according to one of the preceding claims, wherein: The estimation means (30) is arranged to estimate the frequency deviation (FOFF) in such a way that: - converting the sampled values ​​representing the first signal (S1) into complex sampled values ​​(60) by means of an IQ demodulation (50), the reference frequency of the IQ demodulation corresponding to the symbol clock of the receiver (20), - obtaining a corresponding phase deviation value (POFF) for each complex sample value (60), - avoiding overflow-induced jumps between successive phase deviation values ​​(POFF) by converting the phase deviation values ​​(POFF) into a continuously extending profile of the phase deviation values ​​(POFF), and - calculating the change between successive converted phase offset values ​​(POFF), said change representing the corresponding frequency offset (FOFF).

6. The device (5) according to any one of the preceding claims, wherein: The device (5) is configured to: - the time point of receiving the first signal (S1), and / or - the duration of said first signal (S1), and / or - a processing duration for estimating said phase offset (POFF) and / or frequency offset (FOFF), and / or - Minimum accuracy requirements for the estimated phase offset (POFF) and / or frequency offset (FOFF) A time point (TS) is determined at which the estimated value currently determined in the estimation component (30) for the phase offset (POFF) and / or the frequency offset (FOFF) is selected for initializing the symbol synchronizer (40).

7. The device (5) according to any one of the preceding claims, wherein: The estimation component (30) additionally has at least one filter (80) which is arranged to reduce noise contained in the first signal (S1).

8. A transmission system, comprising: - the sender (10), and - a recipient (20) having a device (5) according to one of the preceding claims, in, - the sender (10) is configured to generate the first signal (S1) and the second signal (S2) based on a symbol clock of the sender (10) and transmit the signals (S1, S2) to the receiver (20), and The receiver (20) is arranged to receive symbols representing data from the sender (10) based on the first signal (S1) and the second signal (S2).

9. The transmission system according to claim 8, wherein: The transmission system has at least two senders (10, 10'), each of which is configured to generate at least the first signal (S1) and a corresponding second signal (S2, S2') and to transmit these signals to the receiver (20) in a non-collision manner, and The receiver (20) is arranged to receive symbols representing data from a corresponding sender (10) based on the corresponding first signal (S1) and second signal (S2, S2').

10. The transmission system according to claim 8 or 9, wherein: The transmission system is: - Ultrasonic system, and / or - radar systems, and / or - vehicle systems, and / or - power line transmission systems, and / or -Baseband transmission system.

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