Voltage divider circuit using non-volatile memory device, comparator, and analog-to-digital converter
By designing voltage divider circuits and comparators using nonvolatile memory devices, the large area and high power consumption of ADC design caused by CMOS comparators are solved, and a smaller and lower power consumption ADC design is achieved.
Patent Information
- Application Number
- CN202380075167.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2023-01-18
- Filing Date
- 2023-10-25
- Publication Date
- 2025-06-06
AI Technical Summary
In existing ADC designs, CMOS comparators are complex and huge, resulting in large chip area and high power consumption, making them difficult to be suitable for applications that require a large number of comparators.
Nonvolatile memory devices, such as memristor devices, MRAM, phase change memory devices, etc., are used to design voltage divider circuits and comparators to compare analog input voltages and reference voltages through the resistance state of nonvolatile memory devices.
A smaller ADC design than traditional CMOS comparators is achieved, reducing power consumption, and improving design flexibility and manufacturing process capacity.
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Figure CN120113157A_ABST
Abstract
Description
CROSS-REFERENCE TO RELATED APPLICATIONS
[0001] The present disclosure claims priority to U.S. patent application No. 18 / 156,171, filed on January 18, 2023, entitled “VOLTAGE DIVIDER CIRCUIT USING NON-VOLATILE MEMORY DEVICE,” which is a continuation-in-part of U.S. patent application No. 18 / 147,576, filed on December 28, 2022, entitled “COMPARATOR AND ANALOG-TO-DIGITAL CONVERTER USING NON-VOLATILE MEMORY DEVICE,” which claims priority to U.S. Provisional Application No. 63 / 380,901, filed on October 25, 2022, entitled “Memristor-Based Comparator for Analog-to-Digital Converter,” each of which is incorporated in its entirety into the present application. Technical Field
[0002] Embodiments of the present disclosure relate generally to semiconductor devices, and more particularly, to a voltage divider circuit using a nonvolatile memory device. Background Art
[0003] An analog-to-digital converter (ADC) is a device or system that can convert an analog signal into a digital signal. It is a fundamental component of many modern electronic devices. A comparator is a fundamental component of many types of ADCs. The comparator can compare two inputs and output an output voltage that represents a logical "1" or a logical "0". Summary of the invention
[0004] The following is a brief summary of the present disclosure, which is used to provide a basic understanding of some aspects of the present disclosure. The summary is not an extensive overview of the present disclosure. The summary is not intended to identify the key or important factors of the present disclosure, nor is it intended to illustrate any scope of the specific matters of the present disclosure or any scope of the claims. The sole purpose of the summary is to present some concepts of the present disclosure as a language simplification of the more detailed description presented later.
[0005] According to one or more aspects of the present disclosure, a device is provided. The device may include a resistor ladder circuit of one or more first non-volatile memory devices. When the resistor ladder circuit is connected to a predefined voltage or a predefined current, multiple taps of the resistor ladder circuit generate multiple reference voltages. The one or more first non-volatile memory devices include at least one of a memristor device, an MRAM (magnetoresistive random access memory) device, a phase change memory (PCM) device, a floating gate, or a spintronic device.
[0006] In some embodiments, the apparatus further comprises a plurality of switches connected to a plurality of taps in the resistor ladder circuit.
[0007] In some embodiments, the apparatus further comprises a first comparator connected to a first tap in the resistor ladder circuit, wherein the first tap in the resistor ladder circuit generates a first reference voltage in the plurality of reference voltages.
[0008] In some embodiments, the first comparator includes a second non-volatile memory device.The first comparator generates a first digital output indicative of a result of a comparison between an analog input voltage and the first reference voltage.
[0009] In some embodiments, the first digital output represents a first resistance state of the second non-volatile memory device in response to the first reference voltage and the analog input voltage being applied to the first comparator.
[0010] In some embodiments, before the first reference voltage and the analog input voltage are applied to the first comparator, the first nonvolatile memory device is programmed to an initial resistance state, wherein the initial resistance state includes a high resistance state or a low resistance state.
[0011] In some embodiments, the first digital output indicates whether the first resistance state of the first non-volatile memory device is a high resistance state or a low resistance state.
[0012] In some embodiments, the apparatus further comprises an encoder for generating one or more binary values based at least in part on the first digital output generated by the first comparator.
[0013] In some embodiments, the first non-volatile memory device includes at least one of a memristor device, an MRAM (magnetoresistive random access memory) device, a phase change memory (PCM) device, a floating gate, or a spintronic device.
[0014] In some embodiments, the apparatus further comprises a second comparator connected to a second tap in the resistor ladder circuit, wherein the second tap in the resistor ladder circuit generates a second reference voltage among the plurality of reference voltages.
[0015] In some embodiments, the second comparator includes a third non-volatile memory device.The second comparator generates a second digital output indicating a comparison result between an analog input voltage and the second reference voltage.
[0016] In some embodiments, the second digital output represents a second resistance state of the third non-volatile memory device in response to the second reference voltage and the analog input voltage being applied to the second comparator.
[0017] In some embodiments, the second digital output indicates whether the second resistance state of the second non-volatile memory device is a high resistance state or a low resistance state.
[0018] According to one or more aspects of the present disclosure, a device is provided. The device includes: a first comparator of a first non-volatile memory device. The first comparator is used to: receive a first reference voltage and an analog input voltage as input; and generate a first digital output indicating a result of a comparison between the analog input voltage and the first reference voltage. The first digital output represents a resistance state of the first non-volatile memory device in response to the first reference voltage and the analog input voltage being applied to the first comparator.
[0019] In some embodiments, the apparatus further comprises an encoder that generates one or more binary values based at least in part on the first digital output generated by the first comparator.
[0020] In some embodiments, the first non-volatile memory device includes at least one of a memristor device, an MRAM (magnetoresistive random access memory) device, a phase change memory (PCM) device, a floating gate, or a spintronic device.
[0021] In some embodiments, before the first reference voltage and the analog input voltage are applied to the first comparator, the first non-volatile memory device may be programmed to an initial resistance state. In some embodiments, the initial resistance state includes a high resistance state or a low resistance state.
[0022] In some embodiments, the first digital output indicates whether the first resistance state of the first non-volatile memory device is a high resistance state or a low resistance state.
[0023] In some embodiments, the apparatus further comprises a voltage divider circuit to generate a plurality of reference voltages, wherein the plurality of reference voltages includes the first reference voltage.
[0024] In some embodiments, the voltage divider circuit includes a plurality of non-volatile memory devices connected in series.
[0025] According to one or more aspects of the present disclosure, a method for performing analog-to-digital conversion is provided. The method includes applying a first reference voltage to a first comparator including a first non-volatile memory device; applying an analog input voltage to the first comparator; and using the first comparator to generate a first digital output indicating a comparison result between the analog input voltage and the first reference voltage. The first digital output represents a first resistance state of the first non-volatile memory device in response to the first reference voltage and the analog input voltage being applied to the first comparator.
[0026] In some embodiments, the method further includes generating, by an encoder, one or more binary values based at least in part on the first digital output.
[0027] In some embodiments, the method further includes programming the first nonvolatile memory device to an initial resistance state before the first reference voltage and the analog input voltage are applied to the first comparator, wherein the initial resistance state includes a high resistance state or a low resistance state.
[0028] In some embodiments, the method further includes programming the first non-volatile memory device to the initial resistance state after generating the first digital output.
[0029] In some embodiments, the method further includes applying a second reference voltage and the analog input voltage to a second comparator including a second nonvolatile memory device; and generating a second digital output indicating a comparison result between the analog input voltage and the second reference voltage using the second comparator.
[0030] In some embodiments, the method further includes generating a plurality of reference voltages including the first reference voltage using a voltage divider circuit, wherein the voltage divider circuit includes at least one non-volatile memory device. BRIEF DESCRIPTION OF THE DRAWINGS
[0031] The present disclosure will be more fully understood from the detailed description given below and the accompanying drawings of various embodiments of the present disclosure. However, the accompanying drawings should not be used to limit the present disclosure to specific embodiments, but are only for explanation and understanding.
[0032] Figure 1 is a schematic diagram showing an example ADC according to some embodiments of the present disclosure;
[0033] Figure 2 is a circuit diagram illustrating an example ADC including example reading circuits and programming circuits according to some embodiments of the present disclosure;
[0034] Figure 3A is a circuit diagram showing an example voltage divider circuit according to some embodiments of the present disclosure;
[0035] Figure 3B It is shown that some embodiments of the present disclosure include Figure 3A Circuit diagram of an example ADC with a voltage divider circuit;
[0036] Figure 4A and Figure 4B is a circuit diagram showing example read and write circuits according to some embodiments of the present disclosure;
[0037] Figure 5A , Figure 5B and Figure 6 is a flowchart illustrating an example process of performing analog-to-digital conversion according to some embodiments of the present disclosure. DETAILED DESCRIPTION
[0038] The present disclosure provides a voltage divider circuit, a comparator and ADCs using a non-volatile memory device. The non-volatile memory device may be and / or include a two-terminal device having non-volatility and programmable resistance. Examples of the non-volatile memory device include a memristor device (also known as a resistive random access memory (ReRAM or RRAM)), a magnetoresistive random access memory (MRAM) device, a phase-change memory (PCM) device, a floating gate, a spintronic device, and the like. The non-volatile memory device may be in an original state and have an initial high resistance before being subjected to a suitable electrical stimulus (e.g., a voltage or current signal applied to the RRAM device). The RRAM device may be adjusted from the original state to a lower resistance state by a formation process or from a high-resistance state (HRS) to a low-resistance state (LRS) by a setting process. The formation process may refer to programming the device from the original state. The setup process may refer to programming the device from a high resistance state (HRS). The resistance of the non-volatile memory device may be electrically switched between a high resistance state and a low resistance state in response to an appropriate programming signal applied to the non-volatile memory device (e.g., by applying a voltage greater than a threshold switching voltage of the non-volatile memory device).
[0039] According to one or more aspects of the present disclosure, the voltage divider circuit may include a resistor ladder circuit of one or more non-volatile memory devices. In some embodiments, the non-volatile memory device may be connected in series between two voltages. Each tap of the resistor ladder circuit may generate a reference voltage that may be provided to other devices (e.g., comparators, transistors, operational amplifiers, etc.) as input.
[0040] Compared with existing resistor ladders of poly-resistors, diffused resistors and other types of conventional resistors, the resistor ladder circuits disclosed in the present disclosure have a smaller size. The resistance of the non-volatile memory device can be relatively high (e.g., a resistance value of hundreds of milliohms), so the total current through the resistor ladder circuit can be low and suitable for low power applications. The voltage divider circuit design disclosed in the present disclosure can achieve adjustable reference voltage by adjusting the non-volatile memory device in the resistor ladder circuit to achieve later compensation or adjustment, thereby improving design flexibility and manufacturing process capacity.
[0041] Comparators are essential components of many ADCs. The comparator can compare two inputs and generate an output indicating the comparison result. Many ADCs use complementary metal oxide semiconductor (CMOS) comparators. However, CMOS comparators usually use multiple transistors and have large device sizes to produce accurate comparison results. Therefore, CMOS comparators may not be suitable for ADCs or other applications that require a large number of comparators. For example, a flash ADC may require 2n-1 comparators for n-bit conversion. Therefore, an 8-bit flash ADC may have to use 255 comparators to generate an 8-bit digital output, which may be impractical because it requires a huge chip area and very high power consumption.
[0042] The present disclosure provides comparators and ADCs using nonvolatile memory devices. In some embodiments, the comparator may include at least one nonvolatile memory device. Before the comparator compares the analog input voltage with the reference voltage, the nonvolatile memory device may be programmed to an initial resistance state (e.g., HRS or LRS). The reference voltage and the analog input voltage may then be applied to the comparator. The voltage across the nonvolatile memory device may correspond to the difference between the analog input voltage and the reference voltage. The nonvolatile memory device may be in HRS or LRS according to the voltage across the nonvolatile memory device. Therefore, the resistance state of the nonvolatile memory device applied in response to the analog input voltage and the reference voltage may indicate a comparison result of the analog input voltage and the reference voltage. The comparator may generate a digital output indicating the resistance state of the nonvolatile memory device as a comparison result between the analog input voltage and the reference voltage. The electronic output may be, for example, a voltage signal indicating whether the nonvolatile memory device is in HRS or LRS.
[0043] In some embodiments, ADC may include one or more comparators described in the present disclosure. Each comparator may include at least one non-volatile memory device. Before performing analog-to-digital conversion, each non-volatile memory device in the comparator may be programmed to an initial resistance state (e.g., HRS, LRS, etc.). Then the analog input voltage and multiple reference voltages may be applied to the comparator for comparison. Each non-volatile memory device may be in LRS or HRS according to the voltage at both ends of the non-volatile memory device. Each comparator may generate a digital output representing the comparison result performed by the comparator (e.g., a voltage signal or current signal indicating whether the non-volatile memory device is in HRS or LRS). In some embodiments, the digital output generated by the comparator may be converted to a binary value by an encoder.
[0044] The comparators and / or ADCs described herein can be used to implement flash ADCs, pipeline ADCs (e.g., to implement an initial coarse adjustment stage before a fine adjustment stage), and any other suitable application using a comparator. The ADC design described in the present disclosure uses a non-volatile memory device (e.g., a two-terminal device such as a memristor device) to replace a CMOS comparator with a complex and bulky circuit. Even considering the reading and programming circuits in the ADC design, the ADC design described in the present disclosure is still much smaller than existing flash ADC designs. By using a non-volatile memory device, the comparator described in the present disclosure can be more robust to fluctuations in input voltage and / or reference voltage with non-volatility and IV (current-voltage) curves.
[0045] Figure 1 is a schematic diagram illustrating an example 100 of an analog-to-digital converter (ADC) according to some embodiments of the present disclosure.
[0046] As shown, ADC 100 may include a voltage divider circuit 110, one or more comparators 120 (e.g., comparators 120a, 120b, ..., 120n), one or more programming circuits 130, an encoder 140, and any other suitable components for implementing an ADC using a non-volatile memory device as described in the present disclosure. More or fewer components may be included in ADC 100 without loss of versatility. For example, two or more of the components of ADC 100 may be combined into a single module, or one of the components may be divided into two or more modules. In some embodiments, read circuits 123a-n may not be implemented as part of comparators 120a-n.
[0047] The voltage divider circuit 110 may include one or more resistors, non-volatile memory devices, switches, and / or any other suitable components for implementing voltage division and / or any other suitable functions for generating a reference voltage applied to the comparator 120. In some embodiments, the voltage divider circuit 110 may include a resistor ladder circuit. In one embodiment, the resistor ladder circuit may include a plurality of resistors (e.g., Figure 1 In another embodiment, the resistor ladder circuit and / or voltage divider circuit 110 may include a plurality of resistors R11, R12, R13, ..., R1n connected in series. Figure 3A For example, one or more of the resistors R11, R12, R13, ..., R1n may be replaced by one or more nonvolatile memory devices.
[0048] like Figure 1 As shown, the voltage divider circuit 110 can be connected between two voltages. For example, the first resistor R11 or the first non-volatile memory device can be connected to a first predefined voltage Vrefp1. The nth resistor R1n or the nth non-volatile memory device can be connected to a second predefined voltage Vrefp2. In some embodiments, the nth resistor or the non-volatile memory device can be grounded.
[0049] In some embodiments, each tap of the resistor ladder circuit may generate a different voltage for use as a reference voltage applied to comparator 120, for example Figure 1 Reference voltages Vref1, Vref2, ..., Vrefn are shown. The reference voltage Vref1 may represent the full-scale analog input level of the ADC 100. Each of the reference voltages Vref2, ..., Vrefn may represent a portion of the full-scale analog input level of the ADC 100 (e.g., 1 / 3 of the full-scale analog input level of the ADC 100, 2 / 3 of the full-scale analog input level of the ADC 100, etc.).
[0050] Each comparator 120a-n may receive an analog input voltage Vin and a respective reference voltage as input, compare the inputs, and generate an output signal indicating a comparison result. Each comparator 120a-n may include at least one non-volatile memory device 121a-n. Each non-volatile memory device 121a-n may be a two-terminal non-volatile memory device having a non-volatile resistor, such as a memristor device (also known as a resistive random access memory (ReRAM or RRAM)), a magnetoresistive random access memory (MRAM), a phase change memory (PCM) device, a floating gate, a spintronic device, etc.
[0051] Each comparator 120a-n may further include a digital output 127a-n that may generate and / or output a comparison result performed by the corresponding comparator. As described in more detail below, each digital output 127a-n may indicate a resistance state (e.g., HRS, LRS, etc.) of the corresponding non-volatile memory device in response to applying a reference voltage (e.g., Vref1, Vref2, ..., Vrefn) and an analog input voltage Vin to the comparator including the corresponding non-volatile memory device. In some embodiments, the read circuit 123a-n may be and / or include a combination of Figure 2 In some embodiments, the read circuits 123a-n may include one or more portions of the read circuits 223a-n. Figure 4B One or more circuits 400b.
[0052] To convert the analog input voltage Vin into a digital signal, the programming circuit 130 may program each non-volatile memory device 121a-n to an initial resistance state (e.g., by applying a suitable programming voltage to each non-volatile memory device 121a-n). The initial resistance state may be HRS or LRS. In some embodiments, the programming circuit 130 may include a combination of the following: Figure 4A The one or more circuits 400a are described. Each circuit 400a can be used to program the non-volatile memory devices 121a-n to a suitable resistance.
[0053] A comparison process may be performed by the comparator 120 comparing the analog input voltage Vin with each of a plurality of continuous reference voltages (e.g., reference voltages Vref1, Vref2, ..., Vrefn). The analog input voltage Vin and the reference voltages Vref1, Vref2, ..., Vrefn may be applied to each comparator 120a-n as input for comparison. Figure 1 As shown, the first reference voltage Vref1 and the analog input voltage Vin may be applied to the first comparator 120a (e.g., through switches 113a and 115a, respectively). The second reference voltage Vref2 and the analog input voltage Vin may be applied to the second comparator 120b (e.g., through switches 113b and 115b, respectively). The nth reference voltage Vrefn and the analog input voltage Vin may be applied to the nth comparator 120n (e.g., through switches 113n and 115n, respectively).
[0054] The voltage across the specific nonvolatile memory device 121a-n may correspond to the difference between the analog input voltage Vin and the reference voltage applied to the comparator including the nonvolatile memory device. The specific nonvolatile memory device may be in HRS or LRS according to the voltage across the nonvolatile memory device. Therefore, the resistance and / or resistance state of the specific nonvolatile memory device 121a-n (e.g., whether the nonvolatile memory device remains in the initial resistance state) may indicate the comparison result of the Vin and the corresponding reference voltage (e.g., whether the difference between the Vin and the corresponding reference voltage is greater than the threshold voltage shown).
[0055] The read circuits 123a, 123b, ..., 123n may generate and / or output digital outputs 127a, 127b, ..., 127n indicating the comparison results performed by the corresponding comparators 120a-n. Each digital output 127a-n may be a voltage signal, a current signal, etc. that may indicate whether the non-volatile memory device 121a-n is in an initial resistance state. For example, the digital output 127a may indicate the first resistance state of the non-volatile memory device 121a in response to the reference voltage Vref1 and the analog input voltage Vin applied to the first comparator 120a. As another example, the digital output 127b may indicate the second resistance state of the non-volatile memory device 121b in response to the reference voltage Vref2 and the analog input voltage Vin applied to the second comparator 120b. The digital outputs 127a-n may be and / or include a combination of the following: Figure 2 The digital outputs 227a-n.
[0056] In some embodiments, the ADC 100 may further include an encoder 140 for encoding the digital outputs 127a, 127b, ..., 127n into a desired digital format. The encoder 140 may generate one or more binary values (e.g., bits B0, B1, ..., Bn) based on the digital outputs 127a, 127b, ..., 127n. Each binary value may be a logical "0" or a logical "1". In some embodiments, the encoder may include error correction logic for suppressing bubble errors. In some embodiments, the encoder 140 may include a priority encoder that can compress multiple binary inputs into a smaller number of outputs. In some embodiments, the encoder 140 may be omitted from the ADC 100.
[0057] After completing the above ADC analog-to-digital conversion process, the programming circuit 130 may program the nonvolatile memory devices 121 a - n to an initial resistance state for performing the next analog-to-digital conversion (eg, the next conversion of an analog signal to a digital signal).
[0058] Figure 2 is a circuit block diagram illustrating an example ADC 200 including an example comparator and a read circuit according to some embodiments of the present disclosure.
[0059] As shown, ADC 200 may include a combination of Figure 1 The voltage divider circuit 110 described above. The ADC 200 may further include one or more comparators 220 (comparators 220a, 220b, ..., 220n). Each of the comparators 220 may include one or more non-volatile memory devices (e.g., non-volatile memory devices 221a, 221b, ..., 221n). The non-volatile memory devices 221a-n may correspond to Figure 1 Each of the comparators 220a-n may further include a read circuit 223a, 223b, ..., 223n, one or more capacitors (e.g., capacitors C1, C2, ..., Cn), one or more switches (e.g., switches 235a, 235b, ..., 235n), and / or any other suitable components for performing a comparison of two input voltages using a non-volatile memory device as described in the present disclosure.
[0060] Each read circuit 223a-n may include one or more inverters (e.g., inverters 225a, 225b, ..., 225n) and / or any other suitable components for determining the resistance and / or resistance state of the non-volatile memory device (e.g., by generating one or more signals indicating whether each non-volatile memory device is in HRS or LRS). In some embodiments, one or more of the inverters 225 may be replaced by another type of circuit that can generate a digital output based on an input, such as a buffer.
[0061] In order to convert analog signals into digital signals, the programming circuit ( Figure 2 1 and 2 (not shown) to program each nonvolatile memory device 221a-n to an initial resistance state (eg, HRS or LRS).
[0062] In the first processing cycle, the reference voltage and the threshold voltage Vth may be applied to each capacitor C1, C2, ..., Cn. For example, switches 231a, 231b, ..., 231n may be closed to connect the first end of each capacitor C1, C2, ..., Cn to the corresponding reference voltage Vref1, Vref2, ..., Vrefn. Switches 233a, 233b, ..., 233n may be closed to connect the second end of each capacitor C1, C2, ..., Cn to the threshold voltage Vth. At the end of the first processing cycle, the charge accumulated on the corresponding capacitor C1, C2, ..., Cn may correspond to the difference between the threshold voltage Vth and the corresponding reference voltage applied to the capacitor.
[0063] In the second processing cycle, the analog input voltage Vin may be applied to each capacitor C1, C2, ..., Cn. For example, switches 231a-n and 233a-n may be opened, while switches 235a, 235b, ..., 235n may be closed to connect the first end of each capacitor C1, C2, ..., Cn to the analog input voltage Vin. Figure 2 The voltage Vbi (e.g., Vb1, Vb2, ..., Vbn) shown may be Vth+(Vin-Vrefi), where i=1, 2, ..., n. Therefore, the voltage across the corresponding non-volatile memory device 221a-n may correspond to the difference between the analog input voltage Vin and the reference voltage applied to the comparator including the non-volatile memory device. The resistance and / or resistance state of the given non-volatile memory device may or may not change according to the difference between the reference voltage and Vin. For example, if the difference between Vin and the reference voltage applied to the non-volatile memory device is not greater than a specific trigger voltage, the non-volatile memory device may remain in an initial resistance state. If the difference between Vin and the reference voltage applied to the non-volatile memory device is greater than a specific trigger voltage, the non-volatile memory device may switch from the initial resistance state to a resistance state different from the initial resistance state. The non-volatile memory device may be in LRS or HRS according to the voltage across the non-volatile memory device.
[0064] In the third processing cycle, switches 237a, 237b, ..., 237n can be closed to connect a resistor (e.g., resistor R21, R22, ..., R2n) between voltage Vdd and corresponding non-volatile memory device 221a-n. The voltage Vbi can be higher or lower than the trigger voltage of the inverter. The resistance value of the resistor R21, R22, ..., R2n can be a value between the resistance value of the non-volatile memory 221a-n in LRS and the resistance value of the non-volatile memory device 221a-n in HRS. In the third processing cycle, switches 231a-n, 235a-n and 233a-n can be opened. The input (Vbi) of the inverter connected to the non-volatile memory device can be high or low according to the resistance state of the non-volatile memory device. For example, if the non-volatile memory device connected to the inverter is in LRS, the input applied to the inverter 225a-n can be low. Similarly, if the non-volatile memory device connected to the inverter is in HRS, then the input applied to the inverter 225a-n may be high.
[0065] The inverters may then output voltages 227a-n (eg, signals D0, D1, ..., Dn, as shown) representing logic levels opposite to their inputs Vbi. Figure 2 In some embodiments, the inverters 225a-n may be implemented by buffers or any other suitable components that can generate digital outputs based on inputs applied to the inverters 225a-n.
[0066] In some embodiments, the nonvolatile memory devices 221a-n may be programmed to an initial resistance state to perform the next analog-to-digital conversion during the fourth processing cycle. For example, a suitable programming voltage may be applied to each nonvolatile memory device 221a-n to program the nonvolatile memory device 221a-n to an initial resistance state (e.g., HRS or LRS). The ADC 200 may perform analog-to-digital conversion on another analog signal by performing the operations performed in the first processing cycle to the third processing cycle.
[0067] Figure 3A is a circuit block diagram showing an example voltage divider circuit 301 according to some embodiments of the present disclosure.
[0068] As shown, the voltage divider circuit 301 may include a resistor ladder circuit 310, one or more switches SW1, SW2, ..., SWn, and / or any other suitable components for performing a voltage division or voltage generation function. The resistor ladder circuit 310 may include a plurality of non-volatile memory devices 311a, 311b, ..., 311n. In some embodiments, the non-volatile memory devices are connected in series. The resistor ladder circuit 310 may receive a predefined voltage or a predefined current to generate a plurality of reference voltages. For example, the resistor ladder circuit 310 may be connected between a first voltage Vref and a second voltage to generate a voltage such as Figure 3A The reference voltages Vref1, Vref2, ..., Vrefn shown in . The first nonvolatile memory device 311a can be connected to a first voltage (e.g., a reference voltage Vref). The nth nonvolatile memory device 311n can be connected to an nth voltage (e.g., ground). When the resistor ladder circuit 310 is connected to the predefined voltage or the predefined current, each tap 313a, 313b, ..., 313n of the resistor ladder circuit (e.g., a connection point between the nonvolatile memory devices 311a-n) can generate a different voltage that can be used as a reference voltage Vref1, Vref2, ..., Vrefn. Each nonvolatile memory device 311a, 311b, ..., 311n can be programmed to a desired resistance value by applying a suitable programming voltage to the nonvolatile memory device (e.g., by a suitable circuit that can be used to apply a programming voltage, such as Figure 4A In some embodiments, one or more non-volatile memory devices 311a-n may be programmed to a desired high resistance to reduce DC current and power consumption of a device (e.g., ADC) using the voltage divider circuit 301. For example, one or more non-volatile memory devices 311a-n may be programmed to tens of milliohms, hundreds of milliohms, or thousands of milliohms for implementing applications with nanoampere current consumption.
[0069] Figure 3B FIG. 4 is a circuit block diagram showing an ADC 300 in some embodiments according to the present disclosure.
[0070] As shown, ADC 300 may include a combination of Figure 3A The resistor ladder circuit 310 and / or the voltage divider circuit 301. The non-volatile memory devices 311a, 311b, ..., 311n in the resistor ladder circuit 310 may also be referred to as "a first non-volatile memory device" or "a first plurality of non-volatile memory devices" in the present disclosure. The ADC 300 may further include a combination of Figure 2The one or more comparators 220 (comparators 220a, 220b, ..., 220n) and the non-volatile memory devices 221a-n in the comparators 220a-n may also be referred to as "a second plurality of non-volatile memory devices" in the present disclosure. Figure 3B Each comparator 220 shown may be combined with Figure 2 The reference voltage is compared to the analog input voltage as described in .
[0071] As shown in the figure, each tap 313a-n in the resistor ladder circuit 310 can be connected to a first end of a corresponding switch 231a, 231b, ..., 231n. The second end of the switch is connected to a corresponding comparator 220a, 220b, ..., 220n. Therefore, each comparator 220a-n can be connected to a tap of the resistor ladder circuit 310 for generating a corresponding reference voltage Vref1, Vref2, ..., Vrefn. For example, the first comparator 220a can be connected to the first tap 313a in the resistor ladder circuit 310. The first comparator 220 can include a non-volatile memory device 221a (also referred to as a "second non-volatile memory device"). In combination Figure 2 As described in the foregoing, the first comparator 220a may generate a first digital output indicating a comparison result between the analog input voltage and the first reference voltage. For another example, the second comparator 220b may be connected to the second tap 313b in the resistor ladder circuit 310. The second comparator 220b may include a non-volatile memory device 221b (also referred to as a "third non-volatile memory device"). Figure 2 As described above, the second comparator 220b may generate a second digital output indicating a comparison result between the analog input voltage and the second reference voltage.
[0072] Figure 3B ADC 300 and Figure 2 The ADC 200 in the embodiment can perform analog-to-digital conversion in substantially the same manner. In a first processing cycle, a reference voltage and a threshold voltage Vth can be applied to each capacitor C1, C2, ..., Cn. At the end of the first processing, the charge accumulated on the corresponding capacitor C1, C2, ..., Cn can correspond to the difference between the threshold voltage Vth and the corresponding reference voltage applied to the capacitor. In a second processing cycle, an analog input voltage Vin can be applied to each capacitor C1, C2, ..., Cn through switches 235a, 235b, ..., 235n, respectively. Figure 3BThe voltage Vbi (e.g., Vb1, Vb2, ..., Vbn) shown in can be Vth+(Vin-Vrefi), where i=1, 2, ..., n. Therefore, the voltage across the corresponding non-volatile memory device 221a-n can correspond to the difference between the analog input voltage Vin and the reference voltage applied to the comparator including the non-volatile memory device. The resistance and / or resistance state of the given non-volatile memory device may or may not change depending on the difference between the reference voltage and Vin. The non-volatile memory device can be in LRS or HRS depending on the voltage across the non-volatile memory device.
[0073] In the third processing cycle, switches 237a, 237b, ..., 237n may be closed to connect a resistor (e.g., resistors R21, R22, ..., R2n) between voltage Vdd and the corresponding non-volatile memory device 221a-n. The voltage Vbi may be higher or lower than the trigger voltage of the inverter. The resistors R21, R22, ..., R2n may be values between the resistance value of the non-volatile memory device 221a-n at LRS and the resistance value of the non-volatile memory device 221a-n at HRS. Switches 231a-n, 235a-n, and 233a-n may be opened in the third processing cycle. The input of the inverter (Vbi) connected to the non-volatile memory device may be high or low depending on the resistance state of the non-volatile memory device. The inverter may output a voltage 227a-n (e.g., such as Vbi) representing the opposite logic level of its input Vbi. Figure 2 In some embodiments, the nonvolatile memory device may be programmed to an initial resistance state in the fourth processing cycle.
[0074] Figure 4A is a schematic diagram showing a circuit example 400a for programming a non-volatile memory device according to some embodiments of the present disclosure.
[0075] As shown, the non-volatile memory device 401 can be connected in series to a transistor 403. The non-volatile memory device 401 and the transistor 403 can also be referred to as a one-transistor-one-resistor (1T1R) configuration 400. The transistor 403 can include three terminals, which are labeled as a gate (G), a source (S), and a drain (D). In some embodiments, a first terminal 4011 (e.g., a first electrode) of the non-volatile memory device 401 can be connected to the drain of the transistor 403. The transistor 403 can act as a selector and a current controller, which can set the current compliance of the non-volatile memory device 401 during programming. The gate voltage of the transistor 403 can set the current compliance of the non-volatile memory device 401 during programming, and thus can control the conductivity and analog behavior of the non-volatile memory device 401. For example, in order to program the nonvolatile memory device 401 to a low resistance state (e.g., to set the nonvolatile memory device 401 or to program the nonvolatile memory device 401 to a relatively low resistance value), a setting signal (e.g., a voltage signal, a current signal) may be applied to the second terminal 4013 of the nonvolatile memory device. Another voltage (also referred to as a selection voltage, a word line voltage, or a gate voltage) may be applied to the gate of the transistor to open the gate and set the current compliance, while the source of the transistor 403 may be grounded. In order to program the nonvolatile memory device 401 to a high resistance state (e.g., to reset the nonvolatile memory device 401 from the low resistance state to a high resistance state or to program the nonvolatile memory device 401 to a higher resistance value), a gate voltage may be applied to the gate of the transistor 403 to open the transistor gate. At the same time, a reset signal may be applied to the source of the transistor 403, while the second terminal 4013 of the nonvolatile memory device may be grounded.
[0076] Figure 4B 4 is a schematic diagram showing an example 400b of a circuit for reading the resistance value and / or resistance state of a non-volatile memory device in some embodiments of the present disclosure. As shown in the figure, the non-volatile memory device 401 can be connected to a transimpedance amplifier (TIA) 405, which can perform current-to-voltage conversion and output a voltage value Vout. In order to read the resistance value and / or resistance state of the non-volatile memory device, voltages VG, VS and VR can be applied to the gate of the transistor 403, the source of the transistor 403 and the TIA 405, respectively. The TIA 405 can be connected to a feedback resistor 407. The output voltage Vout of the TIA 405 can represent the current flowing through the non-volatile memory device and can therefore represent the resistance value and / or resistance state of the non-volatile memory device 401.
[0077] Figure 5A 1 is a flow chart showing an example process 500a for performing analog-to-digital conversion according to some embodiments of the present disclosure. The process 500 may be implemented using an ADC (eg, ADC 100, ADC 200, and / or ADC 300) described in the present disclosure.
[0078] Flow 500a may begin at 500, where one or more non-volatile memory devices in a voltage divider circuit may be programmed to one or more predefined resistance values. The voltage divider circuit may be Figure 3A In some embodiments, the nonvolatile memory device can be adjusted to a predefined resistance value (e.g., using a combination of Figure 4A The circuit 400a) programs each non-volatile memory device.
[0079] In 520, the voltage divider circuit may be connected to a predefined voltage or a predefined current to generate a plurality of reference voltages. For example, the first nonvolatile memory device may be connected to the predefined voltage or current. One terminal of the nth nonvolatile memory device may be grounded.
[0080] In 530, a plurality of comparators may be used to compare the analog input voltage with the plurality of reference voltages. Each comparator may include at least one non-volatile memory device (e.g., Figure 1 The comparators 120a-n and / or Figure 2 Comparators 220a-n in the embodiment of the present invention. For example, the non-volatile memory device in the comparator can be programmed to an initial resistance state. The initial resistance state can be HRS or LRS. The corresponding reference voltage and the analog input voltage can be applied to each comparator. For example, a first reference voltage, a second reference voltage, and an nth reference voltage among a plurality of continuous reference voltages can be applied to the first non-volatile memory device, the second non-volatile memory device, and the nth non-volatile memory device as a first input, respectively. The analog input voltage can be applied to each of the first non-volatile memory device, the second non-volatile memory device, and the nth non-volatile memory device as a second input. In some embodiments, implementing comparison by each comparator can involve performing a combination of the following steps: Figure 6 One or more of the operations described.
[0081] At 540, one or more digital outputs indicative of the comparison results may be generated. Each digital output may correspond to a resistance state of a non-volatile memory device. The digital outputs may be combined Figure 1 The digital outputs 127a-n and / or in combination Figure 2 The digital outputs 227a-n can be read by one or more read circuits (e.g. Figure 2 The read circuit 225a-n in the non-volatile memory device may generate a voltage signal, a current signal, etc., which may indicate the resistance state of the non-volatile memory device.
[0082] In some embodiments, in 550, a digital signal representing the analog input voltage may be generated. The digital signal may be generated based at least in part on a digital output generated by a comparator (e.g., a first digital output generated by the first comparator, a second digital output generated by the second comparator, etc.). In some embodiments, the digital signal may be the digital output. In some embodiments, the digital signal may be generated by the Figure 1 The encoder 140 generates (eg, by converting the digital output into a binary value in a suitable format).
[0083] Figure 5B FIG. 5 is a flow chart showing an example process 500 b of performing analog-to-digital conversion according to some embodiments of the present disclosure. The process 500 b may be implemented using the ADC described in the present disclosure (eg, ADC 100 and / or ADC 200 ).
[0084] Process 500b begins at 560, where a plurality of comparators may be used to compare an analog input voltage to a plurality of reference voltages. Each comparator may include at least one non-volatile memory device (e.g., Figure 1 The comparators 120a-n and / or Figure 2 The comparators 220a-n in the embodiment of the present invention may be programmed to an initial resistance state of the non-volatile memory device in the comparator. The initial resistance state may be HRS or LRS. A corresponding reference voltage and an analog input voltage may be applied to each of the comparators. For example, a first reference voltage, a second reference voltage, and an nth reference voltage among a plurality of continuous reference voltages may be applied to a first non-volatile memory device, a second non-volatile memory device, and an nth non-volatile memory device as a first input, respectively. The analog input voltage may be applied to each of the first non-volatile memory device, the second non-volatile memory device, and the nth non-volatile memory device as a second input. In some embodiments, performing comparison by each comparator may involve performing a combination of the following steps: Figure 6 Perform one or more of the actions described in .
[0085] In 570, one or more digital outputs indicative of the comparison results may be generated. Each digital output may correspond to a resistance state of a non-volatile memory device. The digital outputs may be combined Figure 1 The digital outputs 127a-n and / or in combination Figure 2 The digital outputs 227a-n described in the embodiment of the present invention can be read by one or more reading circuits (e.g., Figure 2 The read circuit 225a-n in the non-volatile memory device may generate a voltage signal, a current signal, etc., which may indicate the resistance state of the non-volatile memory device.
[0086] In some embodiments, in 580, a digital signal representing the analog input voltage may be generated. The digital signal may be generated based at least in part on a digital output generated by a comparator (e.g., a first digital output generated by the first comparator, a second digital output generated by the second comparator, etc.). In some embodiments, the digital signal may be the digital output. In some embodiments, the digital signal may be generated by the Figure 1 The encoder 140 in generates (e.g., by converting the digital output into a binary value in a suitable format).
[0087] refer to Figure 6 , a flow chart showing an example process 600 of performing analog-to-digital conversion using a comparator including a non-volatile memory device is shown. The process 600 can be performed by combining Figure 1-2 The comparators 120a-n and / or comparators 220a-n are performed.
[0088] Process 600 may begin at 610, where the non-volatile memory devices may be programmed to an initial resistance state. For example, a suitable programming voltage (e.g., a reset voltage, a set voltage, etc.) may be applied to each non-volatile memory device to program the non-volatile memory device to an initial resistance state. In some embodiments, the programming voltage may be applied to the non-volatile memory device to provide a voltage level at which the non-volatile memory device is programmed to an initial resistance state. Figure 1 The programming circuit 130 and / or Figure 4A One or more circuits 400a in are applied to the nonvolatile memory device.
[0089] At 620, a reference voltage may be applied to the comparator. Figure 2 As described in the above, the reference voltage can be applied to the first terminal of the capacitor connected to the nonvolatile memory device. The threshold voltage can be combined with Figure 2 The voltage applied to the second end of the capacitor.
[0090] At 630, the analog input voltage may be applied to the comparator. Figure 2 The analog input voltage Vin is applied to the first end of the capacitor.
[0091] In 640, the comparator may output a digital output indicating a comparison result between the analog input voltage and the reference voltage. The digital output may be a voltage signal or a current signal indicating whether the non-volatile memory device is in an initial resistance state in response to the reference voltage and the analog input voltage being applied to the comparator. The digital output may be, for example, a voltage signal or a current signal indicating whether the non-volatile memory device is in an LRS or HRS. The digital output may be Figure 1 Digital outputs 127a-n and / or Figure 2 In some embodiments, the resistor (e.g., Figure 2 The resistors R21, R22, ..., R2n in the embodiment may be connected to the non-volatile memory and / or an inverter generating a digital output. Figure 2 As described in the foregoing, the resistor R21 may be connected to the nonvolatile memory device 221a and / or the inverter 225a to generate a voltage Vb1. Vb1 may be higher or lower than the trigger voltage of the inverter 225a according to the resistance state of the nonvolatile memory device 221a. The resistance value of the resistor R21 may be a value between the resistance value of the nonvolatile memory device 221a in LRS and the resistance value of the nonvolatile memory device 221a in HRS.
[0092] In some embodiments, the process 600 may return to 610 after executing 640. For example, the nonvolatile memory device may be programmed to the initial resistance state to perform the next analog-to-digital conversion.
[0093] For the sake of brevity of explanation, the method of the present disclosure is depicted and described as a series of actions. However, actions according to the present disclosure can occur in various orders and / or simultaneously, and occur together with other actions that are not proposed and described in the present disclosure. In addition, not all actions of explanation can be required to realize the method according to the disclosed subject matter. In addition, those skilled in the art will understand and recognize that the method can be represented as a series of mutual states via state diagrams or events alternatively.
[0094] As used herein, the terms "approximately," "about," and "substantially" may refer to within a normal tolerance range in the art, in some embodiments within ±20% of a target size, in some embodiments within ±10% of a target size, in some embodiments within ±5% of a target size, and in some embodiments within ±2% of a target size. The terms "approximately" and "about" may include a target size.
[0095] The present disclosure has been described in detail in the above description. However, it is obvious that the present disclosure can be implemented without these specific details. In some examples, in order to highlight the content of the present invention, well-known structures and devices are shown in the form of block diagrams rather than specific details.
[0096] The terms "first", "second", "third", "fourth", etc. used in this document are marks used to distinguish different components and may not necessarily have the ordinal meaning of the numerical numbers used.
[0097] The word "example" or "exemplary" as used herein means serving as an example, instance or illustration. Any aspect or design described herein as "example" or "exemplary" is not necessarily to be understood as being more preferred or advantageous than other aspects or designs. On the contrary, the purpose of using the words "example" or "exemplary" is to present the concept in a concrete way. In this application, the term "or" means including "or" rather than excluding "or". That is, unless otherwise specified or as can be seen from the context, "X includes A or B" means any natural inclusive permutation and combination. That is, if X includes A; X includes B; or X includes both A and B, then in any of the above cases, "X includes A or B" is satisfied. In addition, "a" and "an" used in this application and the appended claims should generally be understood as "one or more", unless otherwise specified or as can be clearly indicated from the context as being directed to a singular form. "One embodiment" or "an embodiment" mentioned in this specification means that a specific feature, structure or characteristic associated with the embodiment is included in at least one embodiment. Therefore, the phrases "one embodiment" or "an embodiment" appearing in different places in this specification do not necessarily all refer to the same embodiment.
[0098] Although it is obvious to those skilled in the art that additional changes and modifications may be made to the present disclosure after understanding the above description, it should be understood that any specific embodiments shown and described by way of illustration should not be considered limiting. Therefore, the details of various embodiments are not intended to limit the scope of the claims, which themselves merely describe the disclosed technical features.
Claims
1. A device, include: A resistor ladder circuit of one or more first non-volatile memory devices, wherein a plurality of taps of the resistor ladder circuit generate a plurality of reference voltages when the resistor ladder circuit is connected to a predefined voltage or a predefined current, wherein the one or more first non-volatile memory devices include at least one of a memristor device, a magnetoresistive random access memory (MRAM) device, a phase change memory (PCM) device, a floating gate, or a spintronic device.
2. The apparatus of claim 1, further comprising a plurality of switches connected to a plurality of taps in the resistor ladder circuit. 3 . The apparatus of claim 1 , further comprising a first comparator connected to a first tap in the resistor ladder circuit, wherein the first tap in the resistor ladder circuit generates a first reference voltage among the plurality of reference voltages. 4 . The apparatus of claim 3 , wherein the first comparator comprises a second non-volatile memory device, wherein the first comparator generates a first digital output indicative of a result of a comparison between an analog input voltage and the first reference voltage. 5 . The apparatus of claim 4 , wherein the first digital output represents a first resistance state of the second nonvolatile memory device in response to the first reference voltage and the analog input voltage being applied to the first comparator.
6. The device according to claim 5, in, Before the first reference voltage and the analog input voltage are applied to the first comparator, the first nonvolatile memory device is programmed to an initial resistance state, wherein the initial resistance state includes a high resistance state or a low resistance state. 7 . The apparatus of claim 5 , wherein the first digital output indicates whether the first resistance state of the first nonvolatile memory device is a high resistance state or a low resistance state.
8. The device according to claim 4, further comprising: include: An encoder is configured to generate one or more binary values based at least in part on the first digital output generated by the first comparator.
9. The apparatus of claim 4, wherein the first non-volatile memory device comprises at least one of a memristor device, an MRAM device, a PCM device, a floating gate, or a spintronic device.
10. The device according to claim 3, further comprising: include: A second comparator is connected to a second tap in the resistor ladder circuit, wherein the second tap in the resistor ladder circuit generates a second reference voltage among the plurality of reference voltages.
11. The apparatus of claim 10, wherein the second comparator comprises a third non-volatile memory device, wherein the second comparator generates a second digital output indicative of a comparison result between an analog input voltage and the second reference voltage.
12. The apparatus of claim 11, wherein the second digital output represents a second resistance state of the third nonvolatile memory device in response to the second reference voltage and the analog input voltage being applied to the second comparator. 13 . The apparatus of claim 12 , wherein the second digital output indicates whether the second resistance state of the second nonvolatile memory device is a high resistance state or a low resistance state.