Low-power-consumption test method and device for solid state disk based on FPGA prototype verification

Abstract

The invention discloses a low-power-consumption test method and device for a solid state disk based on FPGA prototype verification, and the method comprises the steps: a PC host transmits a signal for entering low power consumption and transmits the signal to an FPGA mainboard, and the FPGA mainboard starts to start a low-power-consumption process after receiving the signal; the FPGA main board controls the daughter board to back up the data of the power-down area in the Flash medium; the FPGA main board is used for keeping and processing special signals in the FPGA main board; the FPGA mainboard carries out reset operation on a power-down area in the test system; the FPGA mainboard executes isolation operation of the power-down area; and the FPGA mainboard carries out power-down operation on the power-down area. According to the method, the low-power-consumption process is verified based on the FPGA prototype verification platform, the risk can be effectively released before the Tapeout of the chip, and meanwhile the low-power-consumption debugging process after the chip returns can be accelerated.

Description

Technical Field

[0001] The present invention relates to the technical field of solid state drives, and more specifically to a low power consumption test method and device for solid state drives based on FPGA prototype verification. Background Art

[0002] Currently, when verifying the low power consumption of SSD - Solid State Drives SOC chips, it is all carried out in the EDA virtual environment. This method is very slow and cannot be combined with the real business scenario. This leads to the fact that the personnel writing the firmware program for the SSD cannot verify the low power consumption process in the real business scenario before the chip is produced. They can only test after the chip production is completed. In this way, if there is a risk in terms of low power consumption, it cannot be discovered and solved in advance, and the risk accumulates until the chip is produced and exposed, resulting in the inability to effectively release the risk of low power consumption. Summary of the Invention

[0003] The purpose of the present invention is to overcome the deficiencies of the prior art and provide a low power consumption test method and device for solid state drives based on FPGA prototype verification.

[0004] To achieve the above purpose, the present invention adopts the following technical solutions:

[0005] In the first aspect, the present invention provides a low power consumption test method for solid state drives based on FPGA prototype verification. The method is implemented based on an FPGA prototype verification low power consumption test system. The FPGA prototype verification low power consumption test system includes an FPGA main board, a daughter board, and a PC host. The FPGA main board is connected to the PC host and the daughter board, and the daughter board is connected to the Flash medium of the solid state drive. The method includes:

[0006] The PC host sends a signal to enter the low power consumption state and transmits it to the FPGA main board. After receiving the signal, the FPGA main board starts the low power consumption process;

[0007] The FPGA main board controls the daughter board to back up the data in the power - off - capable area of the Flash medium;

[0008] The FPGA main board performs a holding process on the special signals inside it;

[0009] The FPGA main board performs a reset operation on the power - off - capable area in the test system;

[0010] The FPGA main board performs an isolation operation on the power - off - capable area;

[0011] The FPGA main board performs a power - off operation on the power - off - capable area.

[0012] Further, the FPGA main board controls the daughter board to back up the data in the power-failurable area of the Flash medium, including:

[0013] The daughter board reads the data related to the power-failurable area in the Flash medium according to the instruction of the FPGA main board;

[0014] Save the data related to the power-failurable area.

[0015] Further, the special signals include control signals and status signals.

[0016] Further, when the value of the control signal changes from 0 to 1, the retention cell saves the control signal.

[0017] Further, the FPGA main board performs the isolation operation of the power-failurable area, including:

[0018] Select logic units to construct the logic circuits of analog OR gates and NAND gates;

[0019] Program and configure the selected logic units to make them realize the logic functions of analog OR gates and NAND gates;

[0020] Connect the relevant signals to be isolated to the input ends of the configured logic circuits of analog OR gates and NAND gates;

[0021] Set the clamping value of the logic circuit according to the isolation requirements of the power-failurable area;

[0022] Process the relevant signals to be isolated by controlling the logic circuit according to the set clamping value.

[0023] Further, it also includes:

[0024] During cold start, start the LFSR data generate to perform pseudo-random filling of the SRAM with data.

[0025] Further, it also includes:

[0026] The PC host sends an additional signal to exit the low-power state to the FPGA main board. After receiving this signal, the FPGA main board starts the process of exiting the low-power state;

[0027] Power on the power-failurable area that the FPGA was powered off before;

[0028] The FPGA main board cancels the isolation operation of the power-failurable area;

[0029] The FPGA main board performs a de-reset operation on the power-failurable area;

[0030] The FPGA main board performs a reply operation on the special signals inside it;

[0031] The FPGA main board control daughter board restores the data in the power-off area of the backup Flash medium.

[0032] In a second aspect, the present invention further provides a solid-state drive based on FPGA prototype verification low-power test device, which operates based on the FPGA prototype verification low-power test system. The FPGA prototype verification low-power test system includes an FPGA main board, a daughter board, and a PC host. The FPGA main board is connected to the PC host and the daughter board, and the daughter board is connected to the Flash medium of the solid-state drive; the device includes:

[0033] A low-power startup unit, which is used for the PC host to send a signal to enter low power and transmit it to the FPGA main board. After receiving the signal, the FPGA main board starts to initiate the low-power process;

[0034] A data backup unit, which is used for the FPGA main board to control the daughter board to back up the data in the power-off area of the Flash medium;

[0035] A holding unit, which is used for the FPGA main board to perform a holding process on its internal special signals;

[0036] A reset unit, which is used for the FPGA main board to perform a reset operation on the power-off area in the test system;

[0037] An isolation unit, which is used for the FPGA main board to perform an isolation operation on the power-off area;

[0038] A power-off operation unit, which is used for the FPGA main board to perform a power-off operation on the power-off area.

[0039] In a third aspect, the present invention further provides a computer device, including a memory, a processor, and a computer program stored on the memory and executable on the processor. When the processor executes the computer program, it implements the solid-state drive based on FPGA prototype verification low-power test method as described above.

[0040] In a fourth aspect, the present invention further provides a computer-readable storage medium. The storage medium stores a computer program, and the computer program includes program instructions. When the program instructions are executed by a processor, the processor is caused to execute the solid-state drive based on FPGA prototype verification low-power test method as described above.

[0041] The beneficial effects of the present invention compared with the prior art are as follows: The solid-state drive is based on an FPGA prototype verification low-power consumption test method, which is implemented based on an FPGA prototype verification low-power consumption test system. The FPGA prototype verification low-power consumption test system includes an FPGA main board, a daughter board, and a PC host. The FPGA main board is connected to the PC host and the daughter board, and the daughter board is connected to the Flash medium of the solid-state drive. The method includes: The PC host sends a signal to enter the low-power state and transmits it to the FPGA main board. After receiving the signal, the FPGA main board starts the low-power process; The FPGA main board controls the daughter board to back up the data in the power-down area of the Flash medium; The FPGA main board performs a holding process on the special signals inside it; The FPGA main board resets the power-down area in the test system; The FPGA main board performs an isolation operation on the power-down area; The FPGA main board performs a power-down operation on the power-down area. By verifying the low-power process based on the FPGA prototype verification platform, the risks can be effectively released before the chip Tapeout, and at the same time, it can accelerate the low-power debugging process after the chip is returned.

[0042] The above description is only an overview of the technical solution of the present invention. In order to understand the technical means of the present invention more clearly, it can be implemented according to the content of the description. And in order to make the above and other purposes, features and advantages of the present invention more obvious and understandable, the following preferred embodiments are specifically described in detail as follows. Brief Description of the Drawings

[0043] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the following drawings are some embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0044] Figure 1 It is a flowchart of the FPGA prototype verification low-power consumption test method for the solid-state drive provided by the specific embodiment of the present invention;

[0045] Figure 2 It is a schematic block diagram of the FPGA prototype verification low-power consumption test device provided by the specific embodiment of the present invention;

[0046] Figure 3 It is a schematic block diagram of a computer device provided by the specific embodiment of the present invention;

[0047] Figure 4 It is an architecture diagram of the FPGA prototype verification low-power consumption test system provided by the specific embodiment of the present invention;

[0048] Figure 5Schematic diagram of isolation FPGA processing provided by a specific embodiment of the present invention;

[0049] Figure 6 Schematic diagram of retention cell FPGA processing provided by a specific embodiment of the present invention;

[0050] Figure 7 Schematic diagram of FPGA sram processing provided by a specific embodiment of the present invention. Specific embodiments

[0051] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

[0052] It should be understood that when used in this specification and the appended claims, the terms "comprises" and "comprising" indicate the presence of the described features, wholes, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, wholes, steps, operations, elements, components, and / or their combinations.

[0053] It should also be understood that the terms used in the specification of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention. As used in the specification of the present invention and the appended claims, unless the context clearly indicates otherwise, the singular forms "a", "an", and "the" are intended to include the plural forms.

[0054] It should be further understood that the term "and / or" used in the specification of the present invention and the appended claims refers to any combination and all possible combinations of one or more of the associated listed items, and includes these combinations.

[0055] The embodiment of the present invention provides a low-power consumption test method for solid-state drive based on FPGA prototype verification. The method is implemented based on an FPGA prototype verification low-power consumption test system. As Figure 4 shown, the FPGA prototype verification low-power consumption test system includes an FPGA main board, a daughter board, and a PC host. The FPGA main board is connected to the PC host and the daughter board, and the daughter board is connected to the Flash medium of the solid-state drive.

[0056] Specifically, the FPGA main board is responsible for communicating with the PC host and achieving interaction through Sideband signals (clkreq, perst, plp, smbus_scl, smbus_sda). Among them, clkreq is used to cooperate with the PCIe links L1.1&L1.2, perst is the PCIe phy reset signal, plp is the power-down protection signal, and smbus_scl and smbus_sda are smbus signals similar to the I2C protocol. The transmission of these signals enables the FPGA main board to receive host instructions and feedback relevant status information to coordinate the system operation.

[0057] Moreover, special processing is also carried out on the powercell (isolation&retention). For isolation, the actions of an OR gate and a NAND gate are simulated. The signal is clamped to 1 through the OR gate or clamped to 0 through the NAND gate to simulate the isolation cell function of the power domain in ASIC design. For the retention cell, the special signal is saved and output-controlled according to the change of the SAVE signal in the low-power state. At the same time, a random value injection module is added to the SRAM on the FPGA main board. In the cold start and low-power shut-down SRAM mode, the LFSR (Linear Feedback Shift Register) data generate is started to perform pseudo-random filling of the SRAM to simulate the random data state of the actual chip SRAM power-down and power-up again.

[0058] In addition, it coordinates the work of the daughter board and other components to ensure that the entire system operates according to the designed low-power test process, such as controlling the execution of single-item tests, stability tests, and test time FPGA-ASIC correlation in the ASIC low-power test.

[0059] The daughter board serves as a connection bridge between the FPGA main board and the Flash medium to achieve access and operation of the Flash medium. The Flash medium is an important component for storing data. The daughter board is responsible for transmitting the data read / write instructions and the data itself between the FPGA main board and the Flash medium to ensure the normal realization of the storage function.

[0060] The FPGA main board is connected to the PC host and the daughter board, enabling the FPGA main board to perform various operations on the Flash medium of the solid-state drive through the daughter board under the control of the PC host, thereby achieving a comprehensive test and verification of the low-power performance of the solid-state drive. Specifically, the connection between the PC host and the FPGA main board is used to transmit control signals and data to achieve human-computer interaction and control of the test process. The connection between the FPGA main board and the daughter board is used to transmit instructions and data to achieve operations such as reading, writing, and management of the Flash medium.

[0061] As Figure 1 shown, the low-power test method for the solid-state drive based on the FPGA prototype verification includes the following steps: S10 - S60.

[0062] S10. The PC host sends a signal to enter the low-power state and transmits it to the FPGA main board. After receiving this signal, the FPGA main board starts the low-power process.

[0063] The PC host sends a signal to enter the low-power state and transmits it to the FPGA main board through the Sideband signal (such as clkreq, perst, plp, smbus_scl, smbus_sda, etc.). After receiving this signal, the FPGA main board starts the low-power process.

[0064] S20. The FPGA main board controls the daughter board to back up the data in the power-off area of the Flash medium.

[0065] The daughter board reads the relevant data in the Flash medium according to the instruction of the FPGA main board and temporarily stores it in a suitable location.

[0066] In one embodiment, step S20 specifically includes the following steps: S201 - S202.

[0067] S201. The daughter board reads the data related to the power-off area in the Flash medium according to the instruction of the FPGA main board.

[0068] S202. Save the data related to the power-off area.

[0069] For steps S201 - S202, after receiving the instruction of the FPGA main board, the internal Flash controller of the daughter board will parse the instruction. After receiving the data returned by the Flash medium, the Flash controller of the daughter board will temporarily store the data in the cache inside the daughter board.

[0070] S30. The FPGA main board performs a hold process on its internal special signals.

[0071] The special signals inside the FPGA main board cover various types, usually including signals closely related to the system's key functions, status monitoring, and low-power operations. For example, the clock control signal determines the operation rhythm of each module inside the chip, the data transfer control signal is responsible for coordinating the flow of data between different modules, and the status indication signal is used to feedback the current working state of the system, such as busy / idle state, error state, etc. These signals play a key role during the normal operation of the system and when entering and exiting the low-power state.

[0072] Classification basis and method: Classification can be carried out according to the functions and roles of signals. One category is control signals, such as enable signals used to start or stop specific functional modules, mode selection signals for adjusting the system working mode, etc.; another category is status signals, such as data valid signals indicating whether data is effectively transmitted, completion signals reflecting whether a certain operation is completed, etc. Through this classification method, it is convenient to subsequently perform retention processing on different types of special signals in a targeted manner.

[0073] The retention cell is the core hardware unit for implementing the retention of special signals. It is designed based on the principle of a flip-flop and can capture and store the current state of special signals when the system enters the low-power state. The retention cell is integrated in the internal logic resources of the FPGA. There are rich programmable logic blocks inside the FPGA, and the retention cell can be embedded into these logic blocks to work in coordination with other logic units. Through the configuration resources of the FPGA, the special signals that need to be retained can be connected to the corresponding retention cells.

[0074] When the FPGA main board receives the signal to enter the low-power state, before performing other low-power operations (such as resetting and isolating the power-down area), it starts the special signal retention processing flow. At this time, the system will scan and identify the predefined special signals to determine which signals need to be retained.

[0075] For the special signals marked as needing to be retained, the corresponding retention cell performs the state saving operation under the control of the SAVE signal. As mentioned before, when the SAVE signal changes from 0 to 1, the retention cell captures and locks the current value of the special signal. In this process, to ensure the accuracy and synchronization of the operation, the generation and transmission of the SAVE signal require strict timing control.

[0076] As Figure 6 shown, under normal functions, the signal passes through directly from the MUX (2-to-1 selector). In the low-power state, the SAVE (save control signal) changes from 0 to 1. At this time, the retention cell will save the signal and then pass through directly from the MUX (2-to-1 selector).

[0077] Through the retention processing of special signals, it is ensured that when the system enters and exits the low-power state, the key control and status information will not be lost. This enables the system to seamlessly resume the previous working state after returning to normal operation, avoiding system restart or incorrect initialization caused by the loss of signal states and ensuring the continuity of the system state. For example, in the above video processing system, it can accurately restore the processing order of video frames and avoid video processing chaos.

[0078] S40. The FPGA main board performs a reset operation on the power-down area in the test system.

[0079] In the test system built by the FPGA main board, the division of the power-down area is based on system function and power consumption management requirements. Generally speaking, the parts that do not need to work temporarily in the low-power state and will not affect the key state of the system and subsequent recovery after power-down are designated as the power-down area.

[0080] This step ensures that the relevant power-down area returns to the initial state, preparing for subsequent low-power operations.

[0081] S50. The FPGA main board performs an isolation operation on the power-down area.

[0082] The FPGA main board performs an isolation operation to isolate the power-down area from other areas. As Figure 5 shown, "isolation" means isolating a certain part or signal from other parts to prevent signal interference, crosstalk, or to achieve specific logic functions and circuit control, etc. For example, in this solution, by using logic circuits such as OR gates and NAND gates, the relevant signals are processed, and through clamping operations, it reaches an effect similar to isolation, making the signal in a specific state (clamped to 1 or 0), so as to achieve the control of the signal and isolation from other parts, avoiding unnecessary influence on other circuit parts or being interfered by other signals, etc.

[0083] In one embodiment, step S50 specifically includes the following steps: S501 - S505.

[0084] S501. Select logic units to construct a logic circuit simulating an OR gate and a NAND gate.

[0085] The PGA internally has rich logic unit resources, such as lookup tables (LUTs), flip-flops (FFs), etc. When selecting logic units to construct an analog logic circuit, the availability of resources, performance, and the complexity of logic implementation need to be considered.

[0086] Taking the lookup table as an example, assume using an input lookup table to construct an analog OR gate. Connect two input signals to the two input pins of the lookup table respectively, and the output pin of the lookup table serves as the output of the analog OR gate. For the construction of the NAND gate, also connect two input signals to the lookup table input pins, but by setting the stored content of the lookup table, make its output conform to the logic function of the NAND gate. Multiple lookup tables can be cascaded to achieve a more complex logic circuit structure.

[0087] S502. Program and configure the selected logic units to make them implement the logic functions of an analog OR gate and a NAND gate.

[0088] The programming configuration of an FPGA is usually completed through specialized development tools, such as Xilinx ISE, Altera Quartus, etc. These tools provide two ways, namely a graphical interface and a hardware description language (HDL), for logic design and configuration. Taking the graphical interface as an example, in the tool, draw a logic circuit diagram, drag the selected logic units (such as lookup tables) into the design interface, and connect the wires according to the logic connection methods of analog OR gates and NAND gates. Then, by setting the attributes of the lookup table, such as input / output pin mapping and stored content (i.e., truth table), the corresponding logic functions are implemented.

[0089] S503. Connect the relevant signals that need to be isolated to the input terminals of the configured logic circuits of analog OR gates and NAND gates.

[0090] First, it is necessary to clarify which signals need to be isolated. These signals are usually those that are transmitted between the power-down area and other areas and may interfere with other areas or be affected by other areas when the power-down area loses power. For example, data bus signals, control signals, etc. By analyzing the functions and circuit structures of the system, determine the list of signals to be isolated. In the design of an FPGA, these signals can be identified through signal naming rules, module interface definitions, etc.

[0091] Utilize the routing resources of the FPGA for signal connection. In the FPGA development tool, signal connection is achieved through a routing tool or by using port mapping statements in the hardware description language.

[0092] S504. Set the clamping value of the logic circuit according to the isolation requirements of the power-down area.

[0093] The setting of the clamping value depends on the isolation requirements of the power-down area and the requirements of other areas for the signal. If other areas need a definite high-level signal when the power-down area loses power, then clamp the output of the logic circuit to a high level (usually 1); conversely, if a low-level signal is required, then clamp it to a low level (usually 0).

[0094] S505. Process the relevant signals to be isolated by controlling the logic circuit according to the set clamping value.

[0095] The control logic circuit is used to ensure that the logic circuit processes the relevant signals according to the set clamping value. The control logic can be implemented through a state machine, combinational logic circuit, etc.

[0096] When the system enters the power-down process in the power-down area, the control logic circuit receives a power-down signal. According to the preset logic, it connects the input of the logic circuit to a fixed clamping signal source, enabling the logic circuit to process relevant signals according to the set clamping value. For example, when powering down in the power-down area, the control logic circuit connects one input of the analog OR gate to a high-level signal source, thereby clamping the output to a high level to achieve isolation processing of relevant signals and prevent signal interference in other areas.

[0097] For step S50, by constructing an analog OR gate and a NAND gate logic circuit and processing relevant signals according to the set clamping value, it is possible to effectively isolate the power-down area from other areas, prevent signal interference generated during power-down in the power-down area from spreading to other areas, and ensure the normal operation of other areas. For example, in the above image acquisition and processing system, interference to the image processing module when the image sensor module powers down is avoided, ensuring the stable operation of the image processing module.

[0098] S60. The FPGA main board performs a power-down operation on the power-down area.

[0099] The FPGA main board sends a notification signal indicating imminent power-down to other modules related to the power-down area. The FPGA main board sends a power-down instruction through the communication interface with the power management chip. At the same time as the power is cut off, the FPGA main board controls the clock controller to stop providing a clock signal to the power-down area.

[0100] For step S60, by performing a power-down operation on the power-down area, the power supply to this area is cut off, causing the relevant circuits and modules to stop working, thereby significantly reducing the overall power consumption of the system.

[0101] In one embodiment, the solid-state drive based on the FPGA prototype verification low-power test method further includes the following step: S70.

[0102] S70. During cold start, start the LFSR data generate to perform pseudo-random filling of data for the SRAM.

[0103] An LFSR is a circuit structure composed of a shift register and feedback logic. The shift register, driven by a clock signal, shifts the stored data bit by bit. The feedback logic generates a feedback value based on the states of certain bits in the shift register and feeds it back to the input of the shift register.

[0104] When implementing an LFSR in an FPGA, the shift register can be formed by cascading multiple flip-flops. Each flip-flop stores one bit of data, and the clock signal is connected to the clock input terminals of all flip-flops simultaneously to ensure that in each clock cycle, all flip-flops perform data shifting operations simultaneously. The feedback logic is implemented through logic gate circuits, such as exclusive-OR gates.

[0105] The LFSR data generate module requires a control logic to start and stop the operation of the LFSR. The control logic can be implemented by a simple state machine. During cold start, the system generates a start signal, which triggers the state machine to enter the start state. In the start state, the state machine enables the clock signal of the LFSR and loads the initial value of the LFSR into the shift register simultaneously. The initial value can be a preset fixed value or a value dynamically generated according to the system configuration. When the amount of data generated by the LFSR reaches the preset value, the state machine receives the data generation completion signal and switches to the stop state, stopping the clock signal of the LFSR, thereby stopping the data generation.

[0106] During cold start, the LFSR needs to be initialized and the initial value is set. The initialization process can be implemented by a hardware circuit. To ensure that the data generated by the LFSR can be accurately written into the SRAM, the operations of the LFSR data generate module and the SRAM need to be carried out in the same clock domain or processed across clock domains through a synchronization circuit.

[0107] As Figure 7 shown, during cold start, start the LFSR (Linear Feedback Shift Register) data generate to perform pseudo-random filling of data in the SRAM. In the low-power shut-down SRAM mode, the FPGA cannot achieve true power-off and also needs to start the LFSR data generate to perform pseudo-random filling of data in the SRAM. After completion, it is equivalent to completing the simulation of SRAM power-off (because when the actual chip SRAM is powered off and then powered on again, the internal data of the SRAM is lost and shows randomness).

[0108] For step S70, by performing pseudo-random filling of the SRAM, the randomness of data in actual applications can be simulated, providing a more realistic data environment for subsequent digital signal processing algorithms, system testing, etc.

[0109] In one embodiment, the low-power test method for the solid-state drive based on the FPGA prototype verification further includes the following steps: S80 - S130.

[0110] S80. The PC host sends an additional signal to exit the low-power state to the FPGA main board. After receiving this signal, the FPGA main board starts the process of exiting the low-power state.

[0111] Transmitted to the FPGA main board through the Sideband signal. After receiving this signal, the FPGA main board starts the process of exiting the low-power state.

[0112] S90, the power-down areas of the FPGA that were previously powered off are powered on to restore the power supply to these areas.

[0113] S100, the FPGA mainboard cancels the isolation operation on the power-off area to restore the normal connection and communication between the power-off area and other areas.

[0114] S110. The FPGA mainboard performs a reset operation on the power-down areas to restore these areas from an initial state to a normal working state.

[0115] S120 and FPGA mainboard perform recovery operations on their internal special signals to restore the previously saved special signal status to the normal working status to ensure the integrity of system functions.

[0116] S130, the FPGA main board controls the sub-board to restore the data in the power-off capable area in the backup Flash medium.

[0117] The daughter board writes the stored backup data back to the corresponding position of the Flash medium according to the instruction, and the system completes the low-power exit process.

[0118] The present invention verifies the low-power process based on an FPGA prototype verification platform, and the risk can be effectively released before the chip Tapeout (the final chip design layout data is delivered to the foundry), while accelerating the low-power debugging process after the chip is returned.

[0119] It should be understood that the order of execution of the steps in the above embodiment does not necessarily mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiment of the present invention.

[0120] The embodiment of the present invention also provides a low-power consumption test device for solid-state hard disk based on FPGA prototype verification, which is used to perform the steps in any embodiment of the above-mentioned low-power consumption test method for solid-state hard disk based on FPGA prototype verification. Figure 2 , Figure 2 A schematic block diagram of a low-power consumption test device 100 for solid-state hard disk based on FPGA prototype verification provided by an embodiment of the present application is shown. The low-power consumption test device 100 for solid-state hard disk based on FPGA prototype verification specifically includes:

[0121] A low-power startup unit 110 is used to send a signal for entering low power consumption from the PC host to the FPGA main board. After receiving this signal, the FPGA main board starts the low-power process; a data backup unit 120 is used for the FPGA main board to control the daughter board to back up the data in the power-off area of the Flash medium; a holding unit 130 is used for the FPGA main board to hold the special signals inside it; a reset unit 140 is used for the FPGA main board to perform a reset operation on the power-off area in the test system; an isolation unit 150 is used for the FPGA main board to perform an isolation operation on the power-off area; a power-off operation unit 160 is used for the FPGA main board to perform a power-off operation on the power-off area.

[0122] In one embodiment, the data backup unit is specifically used for: the daughter board reads the data related to the power-off area in the Flash medium according to the instruction of the FPGA main board; saves the data related to the power-off area.

[0123] In one embodiment, the isolation unit 150 is specifically used for: selecting logic units to construct a logic circuit for simulating an OR gate and a NAND gate; programming and configuring the selected logic units to make them realize the logic functions of an OR gate and a NAND gate; connecting the relevant signals to be isolated to the input ends of the configured logic circuit for simulating an OR gate and a NAND gate; setting the clamping value of the logic circuit according to the isolation requirements of the power-off area; controlling the logic circuit to process the relevant signals to be isolated according to the set clamping value.

[0124] In one embodiment, when the solid-state drive runs based on the FPGA prototype verification low-power test device 100, it further includes: during cold start, starting the LFSR data generate to perform pseudo-random filling of data for the SRAM.

[0125] In one embodiment, when the solid-state drive runs based on the FPGA prototype verification low-power test device 100, it further includes: the PC host sends an additional signal for exiting low power consumption to the FPGA main board. After receiving this signal, the FPGA main board starts the process of exiting low power consumption; performing a power-on operation on the previously powered-off power-off area of the FPGA; the FPGA main board cancels the isolation operation on the power-off area; the FPGA main board performs a de-reset operation on the power-off area; the FPGA main board performs a recovery operation on the special signals inside it; the FPGA main board controls the daughter board to restore the data in the power-off area of the backed-up Flash medium.

[0126] It should be noted that those skilled in the art can clearly understand that the specific implementation processes of the above-mentioned solid-state drive based on the FPGA prototype verification low-power test device 100 and each unit can refer to the corresponding descriptions in the foregoing method embodiments. For the sake of convenience and brevity of description, they will not be elaborated here.

[0127] The above-mentioned solid-state drive based on FPGA prototype verification low-power test device can be implemented in the form of a computer program, and this computer program can run on a computer device as shown in Figure 3 .

[0128] Please refer to Figure 3 . Figure 3 FIG. is a schematic block diagram of a computer device provided by an embodiment of the present application. The computer device 700 may be a server. Among them, the server may be an independent server or a server cluster composed of multiple servers.

[0129] As shown in Figure 3 , the computer device includes a memory, a processor, and a computer program stored on the memory and executable on the processor. When the processor executes the computer program, it implements the steps of the above-mentioned solid-state drive based on FPGA prototype verification low-power test method.

[0130] The computer device 700 includes a processor 720, a memory, and a network interface 750 connected through a system bus 710. Among them, the memory may include a non-volatile storage medium 730 and an internal memory 740.

[0131] The non-volatile storage medium 730 can store an operating system 731 and a computer program 732. When the computer program 732 is executed, the processor 720 can be made to execute the solid-state drive based on FPGA prototype verification low-power test method.

[0132] The processor 720 is used to provide computing and control capabilities to support the operation of the entire computer device 700.

[0133] The internal memory 740 provides an environment for the operation of the computer program 732 in the non-volatile storage medium 730. When the computer program 732 is executed by the processor 720, the processor 720 can be made to execute the solid-state drive based on FPGA prototype verification low-power test method.

[0134] The network interface 750 is used for network communication, such as sending assigned tasks, etc. Those skilled in the art can understand that Figure 3 the structure shown in FIG. is only a block diagram of some structures related to the solution of the present application, and does not constitute a limitation on the computer device 700 to which the solution of the present application is applied. The specific computer device 700 may include more or fewer components than those shown in the figure, or combine some components, or have different component arrangements. Among them, the processor 720 is used to run the program code stored in the memory to implement the solid-state drive based on FPGA prototype verification low-power test method.

[0135] Those skilled in the art can understand thatFigure 3 The embodiments of the computer device shown do not constitute a limitation on the specific composition of the computer device. In other embodiments, the computer device may include more or fewer components than shown in the figure, or combine certain components, or have different component arrangements. For example, in some embodiments, the computer device may include only a memory and a processor. In such an embodiment, the structures and functions of the memory and the processor are the same as those of Figure 3 the embodiments shown and will not be described in detail here.

[0136] It should be understood that in the embodiments of the present application, the processor 720 may be a central processing unit (CPU), and the processor 720 may also be other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. Among them, the general-purpose processor may be a microprocessor or the processor may also be any conventional processor, etc.

[0137] In another embodiment of the present invention, a computer-readable storage medium is provided. The computer-readable storage medium may be a non-volatile computer-readable storage medium. The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, it implements the low-power consumption test method for solid-state drives based on FPGA prototype verification disclosed in the embodiments of the present invention.

[0138] Those skilled in the art can clearly understand that for the convenience and brevity of description, the specific working processes of the above-described devices, apparatuses, and units can refer to the corresponding processes in the foregoing method embodiments and will not be described in detail here. Those of ordinary skill in the art can realize that the units and algorithm steps of each example described in combination with the embodiments disclosed herein can be implemented by electronic hardware, computer software, or a combination of the two. To clearly illustrate the interchangeability of hardware and software, the compositions and steps of each example have been generally described according to functions in the above description. Whether these functions are executed in a hardware or software manner depends on the specific application and design constraints of the technical solution. Professional technicians can use different methods to implement the described functions for each specific application, but such implementation should not be considered to exceed the scope of the present invention.

[0139] In several embodiments provided by the present invention, it should be understood that the disclosed devices, apparatuses, and methods can be implemented in other ways. For example, the device embodiments described above are merely illustrative. For example, the division of the units is only a logical function division. In actual implementation, there may be other division methods, or units with the same function can be aggregated into one unit. For example, multiple units or components can be combined or integrated into another device, or some features can be ignored or not executed. Additionally, the displayed or discussed couplings or direct couplings or communication connections to each other can be indirect couplings or communication connections through some interfaces, devices, or units, or can be electrical, mechanical, or other forms of connection.

[0140] The units described as separate components may or may not be physically separated. The components displayed as units may or may not be physical units, that is, they can be located in one place, or can be distributed to multiple network units. Some or all of the units can be selected according to actual needs to achieve the objectives of the embodiments of the present invention.

[0141] In addition, in each embodiment of the present invention, the functional units can be integrated into one processing unit, or each unit can exist physically alone, or two or more units can be integrated into one unit. The above-mentioned integrated units can be implemented in the form of hardware or in the form of software functional units.

[0142] If the above-mentioned integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a storage medium. Based on this understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods described in each embodiment of the present invention. The aforementioned storage medium includes: various media such as USB flash drives, mobile hard disks, read-only memories (ROMs), magnetic disks, or optical discs that can store program codes.

[0143] As described above, the above are only the specific implementation manners of the present invention, but the protection scope of the present invention is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present invention can easily think of various equivalent modifications or substitutions, and these modifications or substitutions should all be covered within the protection scope of the present invention. Therefore, the protection scope of the present invention should be subject to the protection scope of the claims.

Claims

1. A low-power test method for solid-state hard disk based on FPGA prototype verification, characterized in that: The method is implemented based on an FPGA prototype verification low-power consumption test system, which includes an FPGA mainboard, a daughterboard, and a PC host, wherein the FPGA mainboard is connected to the PC host and the daughterboard, and the daughterboard is connected to a Flash medium of a solid-state hard disk; the method includes: The PC host sends a signal to enter low power consumption and transmits it to the FPGA mainboard. After receiving the signal, the FPGA mainboard starts the low power consumption process. The FPGA main board controls the daughter board to back up the data in the power-off area of ​​the Flash medium; The FPGA mainboard maintains and processes the special signals inside it; The FPGA mainboard performs a reset operation on the power-down area in the test system; The FPGA mainboard performs isolation operations on areas that can be powered off; The FPGA mainboard performs a power-down operation on the power-down capable area.

2. The low-power consumption test method for solid-state hard disk based on FPGA prototype verification according to claim 1 is characterized in that: The FPGA main board controls the sub-board to back up data in the power-off area of ​​the Flash medium, including: The daughter board reads the data related to the power-down area in the Flash medium according to the instruction of the FPGA main board; Save the data related to the power-off area.

3. The low power consumption test method for solid state hard disk based on FPGA prototype verification according to claim 1, characterized in that: The special signals include control signals and status signals.

4. The low power consumption test method for solid state hard disk based on FPGA prototype verification according to claim 3 is characterized in that: When the value of the control signal changes from 0 to 1, the retention cell saves the control signal.

5. The low power consumption test method for solid state hard disk based on FPGA prototype verification according to claim 1, characterized in that: The FPGA mainboard performs isolation operations of the power-down area, including: Select logic cells to construct logic circuits that simulate OR gates and NAND gates; Programming and configuring the selected logic unit to realize the logic functions of analog OR gate and NAND gate; Connect the relevant signals that need to be isolated to the input terminals of the configured analog OR gate and NAND gate logic circuits; Set the clamping value of the logic circuit according to the isolation requirements of the power-down area; The related signals of the isolation processing are processed according to the set clamping value through the control logic circuit.

6. The low power consumption test method for solid state hard disk based on FPGA prototype verification according to claim 1, characterized in that: Also includes: During a cold start, start LFSR data generate to fill the SRAM with pseudo-random data.

7. The low-power consumption test method for solid-state hard disk based on FPGA prototype verification according to claim 1 is characterized in that: Also includes: The PC host sends an additional low-power exit signal to the FPGA mainboard. After receiving the signal, the FPGA mainboard starts the low-power exit process. Power on the previously powered-off area of ​​the FPGA; The FPGA mainboard cancels the isolation operation of the power-down area; The FPGA mainboard performs reset operation on the power-down area; The FPGA mainboard performs a reply operation on the special signal inside it; The FPGA main board controls the daughter board to restore the data in the power-off area of ​​the backup Flash medium.

8. A low-power test device for solid-state hard disk based on FPGA prototype verification, characterized in that: When it is running, it is based on the FPGA prototype verification low power consumption test system, which includes an FPGA mainboard, a daughter board, and a PC host. The FPGA mainboard is connected to the PC host and the daughter board, and the daughter board is connected to the Flash medium of the solid state drive. The device includes: The low-power startup unit is used for the PC host to send a signal to enter low power consumption and transmit it to the FPGA mainboard. After the FPGA mainboard receives the signal, it starts the low-power consumption process; The data backup unit is used for the FPGA mainboard control sub-board to back up the data in the power-off area of ​​the Flash medium; The holding unit is used for the FPGA mainboard to hold special signals inside it; The reset unit is used by the FPGA mainboard to reset the power-down area in the test system; Isolation unit, used for the FPGA mainboard to perform isolation operations on areas that can be powered off; The power-off operation unit is used for the FPGA mainboard to perform power-off operations on the power-off capable area.

9. A computer device, characterized in that: The invention comprises a memory, a processor and a computer program stored in the memory and executable on the processor. When the processor executes the computer program, the low-power consumption test method for solid-state hard disk based on FPGA prototype verification as claimed in any one of claims 1 to 7 is implemented.

10. A computer-readable storage medium, characterized in that: The storage medium stores a computer program, which includes program instructions. When the program instructions are executed by the processor, the processor executes the low-power consumption test method for solid-state hard disk based on FPGA prototype verification as claimed in any one of claims 1 to 7.

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