Test method of built-in self-test system of memory

Abstract

The invention provides a test method for a BIST system of a memory, and belongs to the field of integrated circuits. The test method comprises the following steps: a page buffer test step: a test machine sends a page buffer test command to a controller through a bus, and the controller controls a BIST circuit to test a page buffer and confirms whether the page buffer is damaged; a storage array test step: the test machine sends a storage array test command to the controller through the bus, and the controller controls the BIST circuit to test the storage array; a judgment step: judging whether the storage array is repairable or not by the BIST circuit; a temporary storage step: after the test is completed, the BIST circuit temporarily stores a test result in the page buffer; and a writing step: the controller sends the test result temporarily stored in the page buffer to a test machine through the bus, the test machine sends the test result to the controller through the bus, and the controller writes the test result into the one-time programmable memory. According to the test method, the occupied area of the chip can be reduced, and power consumption is reduced.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuits, and particularly to a test method for a built-in self-test system of a memory. Background Art

[0002] During the manufacturing process of a memory, especially a Phase Change Memory (PCM), it is necessary to test the PCM. When testing the PCM, generally data is written into the storage units of the PCM, and after a period of time, the data is read out from the storage units of the PCM, and then the written data is compared with the read data to determine which storage units in the PCM are abnormal.

[0003] Built-In-SelfTest (BIST) is a common test method. Figure 3 The BIST system of a memory in the prior art is shown. As Figure 3 shown, the memory 900 in the prior art includes: a storage array 91, a controller 92, a MUX (Multiplexer) 93, a BIST circuit 96, a page buffer 97, an eFuse (one-time programmable memory) 98, and a storage circuit 99. When testing, the test station 95 sends a test command to the controller 92 through the bus 94, the controller 92 controls the BIST circuit 96 to test the storage array 91. After the test is completed, the BIST circuit 96 temporarily stores the test result in the storage circuit 99, and then the controller 92 sends the test result temporarily stored in the storage circuit 99 to the test station 95 through the bus 94. Finally, the test station 95 sends the test result to the controller 92 through the bus 94, and the controller 92 writes the test result into the one-time programmable memory 98.

[0004] Among them, the storage circuit 99 is usually a register or an SRAM (Static Random Access Memory), and both the register and the SRAM occupy a relatively large chip area and consume a large amount of power, which is not conducive to the miniaturization of the chip and will also increase the test cost of the chip. Therefore, there is an urgent need in the industry for a BIST system of a memory and its test method that occupy a small chip area and have low power consumption. Summary of the Invention

[0005] The present invention aims to provide a BIST system of a memory and its test method that occupy a small area and have low power consumption.

[0006] The present invention discloses a test method for a BIST system of a memory. The memory includes: a storage array including a plurality of storage units for storing data; a controller electrically connected to the storage array through a multiplexer and electrically connected to a test station through a bus. The built-in self-test system includes: a built-in self-test circuit electrically connected to the controller and electrically connected to the storage array through a multiplexer, and the built-in self-test circuit is used to test the storage array; a page buffer electrically connected to the controller and the built-in self-test circuit, which is used to cache the written data when writing data to the storage array, and is used to temporarily store the test results after the test of the storage array ends; a one-time programmable memory electrically connected to the controller for finally storing the test results.

[0007] The test method includes: a page buffer test step, in which the test station sends a page buffer test command to the controller through the bus, and the controller controls the built-in self-test circuit to test the page buffer to confirm whether the page buffer is damaged; a storage array test step, in which the test station sends a storage array test command to the controller through the bus, and the controller controls the built-in self-test circuit to test the storage array; a determination step, in which the built-in self-test circuit determines whether the storage array is repairable; a temporary storage step, after the test is completed, the built-in self-test circuit temporarily stores the test results in the page buffer; a writing step, the controller sends the test results temporarily stored in the page buffer to the test station through the bus, the test station sends the test results to the controller through the bus, and the controller writes the test results into the one-time programmable memory.

[0008] Through the BIST system of the memory and its test method of the present invention, the chip occupied area can be reduced, the power consumption can be lowered, which is beneficial to the miniaturization of the chip, and the test cost of the chip can also be reduced. Description of the Drawings

[0009] Figure 1 is a schematic block diagram of the BIST system of the memory of the present invention.

[0010] Figure 2 is a flowchart of the test method of the BIST system of the memory of the present invention.

[0011] Figure 3 is a schematic block diagram of the BIST system of the memory in the prior art.

[0012] Symbol Description

[0013] 100, 900 Memory

[0014] 1. 91 Storage Array

[0015] 2. 92 Controller

[0016] 3. 93 MUX

[0017] 4. 94 Bus

[0018] 5. 95 Testing Machine

[0019] 6. 96 BIST Circuit

[0020] 7. 97 Page Buffer

[0021] 8. 98 One - Time Programmable Memory

[0022] 99 Storage Circuit Detailed Embodiment

[0023] The BIST system and its testing method of the memory of the present invention will be specifically described below with reference to the accompanying drawings. Figure 1 is a schematic block diagram of the BIST system of the memory of the present invention. As Figure 1 shown, the memory 100 of the present invention includes: a storage array 1, which includes a plurality of storage units for storing data; a controller 2, which is electrically connected to the storage array 1 through a MUX 3 and is electrically connected to a testing machine 5 through a bus 4. The BIST system includes: a BIST circuit 6, which is electrically connected to the controller 2 and is electrically connected to the storage array 1 through the MUX 3, and the BIST circuit 6 is used to test the storage array 1; a page buffer 7, which is electrically connected to the controller 2 and the BIST circuit 6, and is used to cache the written data when writing data into the storage array 1, and is used to temporarily store the test results when performing BIST on the storage array 1; a one - time programmable memory (eFuse) 8, which is electrically connected to the controller 2 and is used to finally store the test results.

[0024] When performing BIST, the testing machine 5 sends a test command to the controller 2 through the bus 4. The controller 2 controls the BIST circuit 6 to test the storage array 1. After the test is completed, the BIST circuit 6 temporarily stores the test results in the page buffer 7. Then the controller 2 sends the test results temporarily stored in the page buffer 7 to the testing machine 5 through the bus 4. Finally, the testing machine 5 sends the test results to the controller 2 through the bus 4, and the controller 2 writes the test results into the one - time programmable memory 8.

[0025] In the memory of the prior art, the page buffer is usually used to cache the data being written when writing data to the storage array. Specifically, when writing data to the storage array, the data to be written is first transmitted to the controller through the bus, and then the controller writes this data to the storage array. However, the speed of data transmission by the bus is usually greater than the speed of data writing. To solve this problem, usually the bus first sends the data to the controller, and the controller then temporarily stores the data in the page buffer. After all the data has been sent, the controller retrieves this data from the page buffer and then writes it to the storage array.

[0026] That is to say, in the memory of the prior art, the page buffer is only used when writing data to the storage array and is not used during BIST. In the present invention, the page buffer 7 is reused, and during the BIST process, the page buffer 7 is used to temporarily store the test results. Therefore, there is no need to set up a separate storage circuit to temporarily store the test results. This saves space, thereby reducing the chip occupation area of the entire memory, and also reducing power consumption. Therefore, it is beneficial to the miniaturization of the chip and can also reduce the test cost of the chip.

[0027] In addition, the page buffer 7 is a volatile memory, and the data temporarily stored in the page buffer 7 will not be retained after power-off. Therefore, after the BIST is completed, there will be no data stored in the page buffer 7. Therefore, after the BIST is completed, when the memory 100 is put into use and data needs to be written to the storage array 1, it will not affect the data writing.

[0028] Next, the test method of the BIST system of the memory of the present invention will be described. Figure 2 It is a flowchart of the test method of the BIST system of the memory of the present invention. As Figure 2 shown, the test method of the BIST system of the memory of the present invention includes:

[0029] S001, page buffer test step. The test machine 5 sends a page buffer test command to the controller 2 through the bus 4, and the controller 2 controls the BIST circuit 6 to test the page buffer 7 to confirm whether the page buffer 7 is damaged. If so, it is determined that the memory 100 cannot be used. If not, proceed to the next step.

[0030] Among them, any commonly used method in the art can be used to test the page buffer 7, which will not be elaborated here. In the test method of the BIST system of the memory of the present invention, the page buffer 7 is used to store the test results in the subsequent steps of testing the storage array 1. Therefore, if the page buffer 7 itself is damaged, then the subsequent tests cannot be carried out, and the memory 100 cannot be used.

[0031] S002, Storage array test step. The test machine 5 sends a storage array test command to the controller 2 via the bus 4, and the controller 2 controls the BIST circuit 6 to test the storage array 1.

[0032] In this embodiment, when performing BIST, the MUX 3 outputs the signal from the BIST circuit 6, so that the BIST circuit 6 tests the storage array 1. The BIST circuit 6 writes data into each storage cell in the storage array 1. After a period of time, the data is read out from these storage cells, and then it is compared whether the written data is the same as the read data, so as to judge whether the storage cell is abnormal. Any commonly used BIST method in the art can be used for testing, which will not be elaborated here.

[0033] S003, Determination step. The BIST circuit 6 determines whether the storage array 1 is repairable. If there are too many abnormal storage cells in the storage array 1 and they cannot be replaced by redundant storage cells, it is determined to be irreparable and the memory 100 cannot be used. Otherwise, it is determined to be repairable and proceed to the next step.

[0034] S004, Temporary storage step. After the test is completed, the BIST circuit 6 temporarily stores the test results in the page buffer 7. In this embodiment, the test results include: data such as the addresses of the abnormal storage cells and the enable signals of the redundant storage cells for replacing the abnormal storage cells.

[0035] S005, Writing step. The controller 2 sends the test results temporarily stored in the page buffer 7 to the test machine 5 via the bus 4, the test machine 5 sends the test results to the controller 2 via the bus 4, and the controller 2 writes the test results into the one-time programmable memory 8.

[0036] After the BIST is completed and the memory 100 is put into use, when data needs to be written into the memory array 1, first, after the chip is powered on, the controller 2 reads out the previously stored test results (such as the addresses of abnormal memory cells, the enable signals of redundant memory cells replacing the abnormal memory cells, etc.) from the one-time programmable memory 8 and loads them into the internal registers of the controller 2. Then, the data to be written and the starting address of the memory cell are sent to the controller 2 through the bus 4. The controller 2 first temporarily stores the data to be written in the page buffer 7, then enables the MUX 3 to output the signal from the controller 2. The controller 2 then retrieves the data to be written from the page buffer 7 and writes it into the corresponding memory cell in the memory array 1. Here, the bus 4 only sends the starting address to the controller 2, and the other addresses are generated by the controller 2. The generated address is sent to the comparator in the controller 2, and the comparator compares the generated address with the address of the abnormal memory cell loaded in the internal register. If the generated address is exactly the address of the abnormal memory cell, the controller 2 retrieves the enable signal of the redundant memory cell replacing the abnormal memory cell from the internal register, pulls up the enable signal, and writes the data to be written into the redundant memory cell.

[0037] Through the BIST system and its test method of the memory of the present invention, the chip occupation area of the memory can be reduced, and the power consumption can be lowered. Therefore, it is beneficial to the miniaturization of the chip, and the test cost of the chip can also be reduced.

[0038] Although the present invention has been disclosed as above in the form of embodiments, it is not intended to limit the present invention. Any person skilled in the art may make various necessary changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the appended claims.

Claims

1. A method for testing a memory built-in self-test system, characterized in that: The memory (100) comprises: A storage array (1) comprising a plurality of storage cells for storing data; A controller (2) electrically connected to the storage array (1) via a multiplexer (3) and electrically connected to a test machine (5) via a bus (4); The built-in self-test system comprises: A built-in self-test circuit (6) is electrically connected to the controller (2) and is electrically connected to the storage array (1) via a multiplexer (3), wherein the built-in self-test circuit (6) is used to test the storage array (1); A page buffer (7) electrically connected to the controller (2) and the built-in self-test circuit (6), used for caching the written data when writing data to the storage array (1), and for temporarily storing the test results when performing a built-in self-test on the storage array (1); A one-time programmable memory (8), which is electrically connected to the controller (2) and is used to finally store the test result; The test method includes: A page buffer test step, wherein the test machine (5) sends a page buffer test command to the controller (2) via the bus (4), and the controller (2) controls the built-in self-test circuit (6) to test the page buffer (7) to confirm whether the page buffer (7) is damaged; A storage array testing step, wherein the test machine (5) sends a storage array test command to the controller (2) via the bus (4), and the controller (2) controls the built-in self-test circuit (6) to test the storage array (1); A determination step, wherein the built-in self-test circuit (6) determines whether the storage array (1) is repairable; A temporary storage step, after the test is completed, the built-in self-test circuit (6) temporarily stores the test result in the page buffer (7); In a writing step, the controller (2) sends the test result temporarily stored in the page buffer (7) to the test machine (5) via the bus (4), the test machine (5) sends the test result to the controller (2) via the bus (4), and the controller (2) writes the test result into the one-time programmable memory (8).

Images