Low-capacitance TVS (Transient Voltage Suppressor) structure with low clamping voltage and preparation method of low-capacitance TVS structure
Through the low-capacity TVS structure integrating longitudinal SCR and longitudinal PN diodes, the problem of chip area limitation in the prior art is solved, and the matching of high inrush current and low parasitic capacitance is achieved, and the protection devices suitable for high-speed communication and transmission interfaces are suitable.
Patent Information
- Application Number
- CN202510433713.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-04-08
- Publication Date
- 2025-07-11
AI Technical Summary
The existing protective device structures are difficult to match high inrush current and low parasitic capacitors when the chip area is limited, especially in high-speed communication transmission, the demand for low clamp voltage and low parasitic capacitors is not met.
Using an integrated structure of longitudinal SCR and longitudinal PN diodes, a low clamp voltage and low capacitance TVS structure is achieved by forming a specific injection region and deep groove structure on the substrate layer, and forming electrodes in combination with metal wiring.
The matching of high inrush current and low parasitic capacitance is achieved on a small-area chip, and the protection devices suitable for high-speed transmission interfaces have overcome the bottleneck of IPP capabilities in the prior art.
Smart Images
Figure CN120302712A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of semiconductor protection devices, and more particularly, to a low-capacitance TVS structure with a low clamping voltage and a method for manufacturing the same. Background Art
[0002] With the development of semiconductor technology, ICs are developing towards low voltage and are becoming more sensitive to static electricity. In the field of communication transmission, the transmission speed is also getting faster and faster. As a protection device applied to interface surge protection, since it is connected in parallel to the interface, it has a certain impact on communication transmission. Therefore, it is required that the chip has a lower parasitic capacitance; at the same time, as the requirement for the protection level of the board design is getting higher and higher, the requirement for the over-surge capacity of the protection device is also increasing. Generally speaking, the current design requirements for protection devices are low parasitic capacitance, high surge current, and low clamping voltage.
[0003] The existing protection device structure realizes the matching of capacitance and surge current by integrating a diode and an SCR, but usually adopts a lateral SCR structure, and its IPP (peak pulse current) capability is severely restricted by the chip area. Summary of the Invention
[0004] The present invention aims to overcome the defect that the IPP capability of the protection device in the above-mentioned prior art has a performance bottleneck, and provides a low-capacitance TVS structure with a low clamping voltage and a method for manufacturing the same.
[0005] To solve the above technical problems, the technical solution of the present invention is as follows:
[0006] In a first aspect, a low-capacitance TVS structure with a low clamping voltage includes:
[0007] A substrate layer of a first conductivity type, a first buried layer of a first conductivity type, a second buried layer of a second conductivity type, an epitaxial layer of a second conductivity type, a well region of a first conductivity type, a first deep trench, a second deep trench, a first implantation region of a first conductivity type, a second implantation region of a first conductivity type, a third implantation region of a second conductivity type, a fourth implantation region of a second conductivity type, and a fifth implantation region of a second conductivity type; wherein,
[0008] The epitaxial layer is disposed above the substrate layer and in contact with the substrate layer, and the first buried layer and the second buried layer are interposed between the bottom surface of the epitaxial layer and the top surface of the substrate layer;
[0009] A well region is formed at one side top of the epitaxial layer and is in the same longitudinal extension direction as the first buried layer; a first implantation region and a fourth implantation region are formed on the inner top surface of the well region, and the fourth implantation region is distributed on both sides of the first implantation region, and third implantation regions are formed on both outer sides of the well region;
[0010] On the top of the other side of the epitaxial layer, the second implantation region and the fifth implantation region are formed and are in the same longitudinal extension direction as the second buried layer;
[0011] Multiple first deep trenches serving as isolation structures penetrate through the epitaxial layer and extend into the substrate layer, and the second deep trench serving as an electrical connection structure penetrates through the epitaxial layer and the second buried layer and extends into the substrate layer;
[0012] The first implantation region, the fourth implantation region and the second implantation region are connected by metal wirings and jointly form a first electrode, and the fifth implantation region and the second deep trench are connected by metal wirings and jointly form a second electrode with the substrate layer.
[0013] In a second aspect, a preparation method of a low-capacitance TVS structure includes:
[0014] Providing a first-conductivity-type substrate as the substrate layer;
[0015] Forming a first buried layer of the first-conductivity type and a second buried layer of the second-conductivity type on the top of the substrate layer by an implantation method;
[0016] Forming an epitaxial layer of the second-conductivity type on the first buried layer and the second buried layer by an epitaxial growth method;
[0017] Forming a well region of the first-conductivity type by implanting elements of the first-conductivity type on the top of the epitaxial layer; wherein, the well region and the first buried layer are in the same longitudinal extension direction;
[0018] Forming a first implantation region and a second implantation region of the first-conductivity type by implanting elements of the first-conductivity type on the top of the well region and on the top of the side of the epitaxial layer close to the second buried layer, forming a third implantation region, a fourth implantation region and a fifth implantation region of the second-conductivity type by implanting elements of the second-conductivity type; wherein, the first implantation region and the fourth implantation region are formed on the inner top surface of the well region, and the fourth implantation region is distributed on both sides of the first implantation region, the third implantation region is formed on both outer sides of the well region, and the second implantation region and the fifth implantation region are formed on the top of the epitaxial layer and are in the same longitudinal extension direction as the second buried layer;
[0019] In the epitaxial layer, forming a first deep trench and a second deep trench by a silicon etching method; wherein, multiple first deep trenches penetrate through the epitaxial layer and extend into the substrate layer, and an electrically insulating medium is filled in the first deep trenches to serve as an isolation structure; the second deep trench penetrates through the epitaxial layer and the second buried layer and extends into the substrate layer, and a conductive metal is filled in the second deep trench to form an electrical connection structure;
[0020] Through metal wiring, the fourth implantation region, the first implantation region and the second implantation region are connected to form a first electrode, and the fifth implantation region is connected to the second deep trench and jointly forms a second electrode with the substrate layer.
[0021] Compared with the prior art, the beneficial effects of the technical solution of the present invention are:
[0022] The present application discloses a low-capacitance TVS structure with a low clamping voltage. By integrating a vertical SCR and a vertical PN diode, the problem of the area limitation of the lateral structure is solved, the performance bottleneck of the IPP ability is overcome, and finally a perfect match between a high surge current and a low parasitic capacitance is achieved within a small chip volume, and it can be applied to protection devices for high-speed transmission interfaces. Description of the Drawings
[0023] Figure 1 For Embodiment 1 of the present application.
[0024] Figure 2 Another cross-sectional structure diagram of the low-capacitance TVS structure provided in Embodiment 1 of the present application.
[0025] Figure 3 Another cross-sectional structure diagram of the low-capacitance TVS structure provided in Embodiment 1 of the present application.
[0026] Figure 4 The equivalent circuit diagram of the low-capacitance TVS structure provided in Embodiment 1 of the present application.
[0027] Figure 5 The I-V curve interpretation diagram of the low-capacitance TVS structure provided in Embodiment 1 of the present application.
[0028] Figure 6 The flow chart of the preparation method described in Embodiment 2 of the present application.
[0029] Among them, the reference numerals are as follows:
[0030] 101 - Substrate layer; 201 - First buried layer; 202 - Second buried layer; 301 - Epitaxial layer; 401 - Well region; 501 - First deep trench; 502 - Second deep trench; 601 - First implantation region; 602 - Second implantation region; 603 - Third implantation region; 604 - Fourth implantation region; 605 - Fifth implantation region. Detailed Embodiments
[0031] In the description and claims of this application and the above-mentioned drawings, terms such as "first", "second", etc. are used to distinguish similar objects, and do not necessarily describe a specific order or sequence. It should be understood that such terms can be interchanged under appropriate circumstances, which is only a way of distinguishing objects with the same attributes when describing the embodiments of this application. The orientation or positional relationship indicated by terms such as "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. is based on the orientation or positional relationship shown in the drawings, and is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation or be constructed and operated in a specific orientation, so it cannot be understood as a limitation to the present invention. In addition, the terms "comprising" and "having" and any variations thereof are intended to cover non-exclusive inclusion, so that a process, method, system, product or device comprising a series of units does not have to be limited to those units, but may include other units not clearly listed or inherent to these processes, methods, products or devices. The term "determine" broadly covers a variety of actions, which may include obtaining, calculating, computing, processing, deriving, researching, searching (e.g., searching in a table, database or other data structure), ascertaining, and similar actions, and may also include receiving (e.g., receiving information), accessing (e.g., accessing data in a memory) and similar actions, and may also include generating, creating, establishing and similar actions, as well as parsing, selecting, picking and similar actions, etc.
[0032] It should be noted that, unless otherwise clearly stipulated and defined, terms such as "arrange", "install", "connect", "fix", "join" should be understood in a broad sense. Exemplarily, when an element is considered to be "connected" to another element, it can be directly connected to the other element or connected to the other element through an intermediate element. In addition, for the "connection" in the following embodiments, if there is a transmission of electrical signals or data between the connected objects, it should be understood as "electrical connection", "communication connection", etc.
[0033] Regarding any element in the embodiments, the use of terms such as "preferred", "optional", "may", "might", "possibly", etc. means that the element is not required, or alternatively the element is required, and both alternative scenarios are within the scope of the (one or more) embodiments. The relevant definitions of other terms will be given in the following description.
[0034] The drawings are only for illustrative purposes and cannot be construed as a limitation of this patent;
[0035] To better illustrate this embodiment, some components in the drawings are omitted, enlarged or reduced, which does not represent the size of the actual product;
[0036] For those skilled in the art, it is understandable that some well-known structures and their descriptions in the drawings may be omitted.
[0037] The technical solution of the present invention will be further described below in conjunction with the drawings and embodiments.
[0038] Embodiment 1
[0039] This embodiment provides a low-capacitance TVS structure with a low clamping voltage, including:
[0040] A substrate layer of the first conductivity type, a first buried layer of the first conductivity type, a second buried layer of the second conductivity type, an epitaxial layer of the second conductivity type, a well region of the first conductivity type, a first deep trench, a second deep trench, and a first implantation region of the first conductivity type, a second implantation region of the first conductivity type, a third implantation region of the second conductivity type, a fourth implantation region of the second conductivity type, and a fifth implantation region of the second conductivity type; wherein,
[0041] The epitaxial layer is disposed above the substrate layer and in contact with the substrate layer, and the first buried layer and the second buried layer are sandwiched between the bottom surface of the epitaxial layer and the top surface of the substrate layer;
[0042] The well region is formed at the top of one side of the epitaxial layer and is in the same longitudinal extension direction as the first buried layer; the first implantation region and the fourth implantation region are formed on the inner top surface of the well region, and the fourth implantation region is distributed on both sides of the first implantation region, and the third implantation region is formed on both outer sides of the well region;
[0043] The second implantation region and the fifth implantation region are formed at the top of the other side of the epitaxial layer and are in the same longitudinal extension direction as the second buried layer;
[0044] A plurality of the first deep trenches as isolation structures penetrate the epitaxial layer and extend into the substrate layer, and the second deep trench as an electrical connection structure penetrates the epitaxial layer and the second buried layer and extends into the substrate layer;
[0045] The first implantation region, the fourth implantation region and the second implantation region are connected by metal wiring and jointly form a first electrode, and the fifth implantation region and the second deep trench are connected by metal wiring and jointly form a second electrode with the substrate layer.
[0046] It should be noted that in the above embodiment, by integrating the longitudinal SCR and the longitudinal PN diode, the problem of the area restriction of the lateral structure is solved, and the combination of high surge current and low parasitic capacitance on a small-area chip is realized, which can be used as a protection device for high-speed transmission interfaces.
[0047] In some preferred embodiments, the substrate layer is made of a silicon material of the first conduction type, with a resistivity ranging from 0.001 to 0.02 ohm.cm, and the doping element is an element of the first conduction type.
[0048] In some preferred embodiments, the implanting element of the first buried layer is an element of the first conduction type, with an implanting dose of 1.0E13 - 1.0E15 and a diffusion temperature of 1050°C - 1200°C; the implanting element of the second buried layer is an element of the second conduction type, with an implanting dose of 1.0E13 - 1.0E15 and a diffusion temperature of 1050°C - 1200°C.
[0049] In some preferred embodiments, the doping element of the epitaxial layer is an element of the second conduction type, with a resistivity of 100 - 300 ohm.cm.
[0050] In some preferred embodiments, the implanting element of the well region is an element of the first conduction type, with an implanting dose of 1.0E13 - 1.0E15 and a diffusion temperature of 1050°C - 1150°C.
[0051] In some preferred embodiments, the implanting elements of the first implantation region and the second implantation region are elements of the first conduction type, with an implanting dose of 1.0E14 - 1.0E16 and a diffusion temperature of 900°C - 1100°C; and / or, the implanting elements of the third implantation region, the fourth implantation region, and the fifth implantation region are elements of the second conduction type, with an implanting dose of 1.0E14 - 1.0E16 and a diffusion temperature of 900°C - 1100°C.
[0052] In some preferred embodiments, the first deep trench is filled with an electrically insulating dielectric, with a width of 0.5μm - 2.0μm and a depth of 5μm - 30μm; the second deep trench is filled with tungsten metal, with a width of 1.0μm - 4.0μm and a depth of 5μm - 30μm.
[0053] In some preferred embodiments, it further includes a hole dielectric layer covering the top surface of the epitaxial layer and exposing the first implantation region, the second implantation region, the fourth implantation region, the fifth implantation region, and the second deep trench, and the hole dielectric layer adopts a structure of silicon dioxide, silicon nitride, or a combination of the two.
[0054] In some preferred embodiments, AlSiCu, Al, or Ag is used as the electrode metal to form an ohmic contact layer, and the metal thickness is 2μm - 6μm.
[0055] It should be noted that the first conduction type is P-type and the second conduction type is N-type; or, the first conduction type is N-type and the second conduction type is P-type.
[0056] Those skilled in the art should understand that when the first conduction type is P-type and the second conduction type is N-type, the first conduction type element can be a Group III element (such as boron), and the second conduction type element can be a Group V element (such as phosphorus or arsenic);
[0057] When the first conduction type is N-type and the second conduction type is P-type, the first conduction type element can be a Group V element, and the second conduction type element can be a Group III element.
[0058] For the convenience of those ordinary skilled in the art to more clearly understand and implement the low-capacitance TVS structure described in the above embodiments, the following will be described with the first conduction type being P-type and the second conduction type being N-type.
[0059] In some specific implementation processes, such as Figure 2 shown is a unidirectional low-capacitance TVS structure based on a P-type substrate layer (P-Sub). Except for the substrate layer, it includes: a PBL layer (i.e., the first buried layer), an NBL layer (i.e., the second buried layer), an N-EPI layer (i.e., the epitaxial layer), a PWELL region (i.e., the well region), an N+ region, a P+ region, isolation trenches (i.e., the first deep trench, DT1 (Deep Trench-1)), and tungsten plugs (i.e., the second deep trench, DT2 (Deep Trench-2));
[0060] The P+ region includes a P1 region (i.e., the first implantation region) and a P2 region (i.e., the second implantation region), and the N+ region includes an N1 region (i.e., the third implantation region), an N2 region (i.e., the fourth implantation region), and an N3 region (i.e., the fifth implantation region); among them, above the PBL layer, the P1 region is formed on the inner top surface of the PWELL region, 2 N2 regions are distributed on both sides of the P1 region, and 2 N1 regions are distributed on the left and right sides of the PWELL region; above the NBL layer, the P2 region and the N3 region are formed on the top of the N-EPI layer;
[0061] 4 isolation trenches penetrate through the N-EPI layer and extend into the substrate layer, and 2 of the isolation trenches penetrate through the PBL layer, and the other 2 isolation trenches penetrate through the NBL layer; 1 tungsten plug penetrates through the N-EPI layer and the NBL layer and then extends into the substrate layer;
[0062] Through metal wiring, the N2 region, the P1 region, and the P2 region are connected to form a positive electrode (i.e., the first electrode), and the N3 region is connected to the tungsten plug and jointly forms a negative electrode (i.e., the second electrode) with the substrate layer.
[0063] More specifically, the substrate layer material is made of P-type silicon material, its resistivity is between 0.001 - 0.02 ohm.cm, and the doping element is boron.
[0064] More specifically, the implanted element in the PBL layer is boron, the implantation dose is 1.0E13 - 1.0E15, and the diffusion temperature is 1050°C - 1200°C.
[0065] More specifically, the implanted element in the NBL layer is phosphorus or arsenic, the implantation dose is 1.0E13 - 1.0E15, and the diffusion temperature is 1050°C - 1200°C.
[0066] More specifically, the doped element in the N-EPI layer is phosphorus or arsenic, and its resistivity is between 100 - 300 ohm.cm.
[0067] More specifically, the implanted element in the PWELL region is boron, the implantation dose is 1.0E13 - 1.0E15, and the diffusion temperature is 1050°C - 1150°C.
[0068] More specifically, the implanted element in the N1 / N2 / N3 region is phosphorus or arsenic, the implantation dose is 1.0E14 - 1.0E16, and the diffusion temperature is 900°C - 1100°C.
[0069] More specifically, the implanted element in the P1 / P2 region is boron, the implantation dose is 1.0E14 - 1.0E16, and the diffusion temperature is 900°C - 1100°C.
[0070] More specifically, the width of the tungsten plug is 1.0μm - 4.0μm, and the depth is 5μm - 30μm.
[0071] More specifically, the width of the isolation groove is 0.5μm - 2.0μm, and the depth is 5μm - 30μm.
[0072] Further, referring to Figure 3 , the low-capacitance TVS structure further includes a hole dielectric layer, which is a structure of silicon dioxide, silicon nitride, or a combination of the two.
[0073] It should be understood that while covering the N-EPI layer, the hole dielectric layer will have openings to expose the P1 region, the P2 region, the N2 region, and the N3 region for metal wiring.
[0074] Figure 4 shows the equivalent circuit diagram of the unidirectional low-capacitance TVS structure described in the above specific implementation process, and its I-V curve is as Figure 5 shown.
[0075] Figure 5 In
[0076] V RWM : Reverse working voltage, the reverse working voltage;
[0077] I R: Reverse leakage current, reverse leakage current;
[0078] V BR : Reverse breakdown voltage, reverse breakdown voltage;
[0079] I BR : Reverse breakdown current, reverse breakdown current;
[0080] V CL : Clamping voltage, clamping voltage;
[0081] V RRIG : Reverse trigger voltage, reverse trigger voltage;
[0082] I TRIG : Reverse trigger current, reverse trigger current;
[0083] V HOLD : Reverse holding voltage, holding voltage;
[0084] I HOLD : Reverse holding current, holding current;
[0085] I PP : Peak pulse current, peak pulse current;
[0086] V FC : Forward clamping voltage, forward clamping voltage;
[0087] I F : Forward current, forward current;
[0088] V F : Forward voltage, forward voltage.
[0089] Example 2
[0090] This embodiment provides a method for fabricating a low-capacitance TVS structure. Refer to Figure 6 , including:
[0091] Provide a first-conductivity-type substrate as the substrate layer;
[0092] Form a first buried layer of the first conductivity type and a second buried layer of the second conductivity type on the top of the substrate layer by implantation;
[0093] An epitaxial layer of the second conductivity type is formed on the first buried layer and the second buried layer by means of epitaxial growth;
[0094] A well region of the first conductivity type is formed by implanting elements of the first conductivity type on the top of the epitaxial layer; wherein, the well region and the first buried layer are located in the same longitudinal extension direction;
[0095] On the top of the well region and on the top of the side of the epitaxial layer close to the second buried layer, a first implantation region and a second implantation region of the first conductivity type are formed by implanting elements of the first conductivity type, a third implantation region, a fourth implantation region and a fifth implantation region of the second conductivity type are formed by implanting elements of the second conductivity type; wherein, the first implantation region and the fourth implantation region are formed on the inner top surface of the well region, and the fourth implantation region is distributed on both sides of the first implantation region, the third implantation region is formed on the outer sides of the well region, and the second implantation region and the fifth implantation region are formed on the top of the epitaxial layer and are located in the same longitudinal extension direction as the second buried layer;
[0096] In the epitaxial layer, a first deep trench and a second deep trench are formed by a silicon etching method; wherein, a plurality of the first deep trenches penetrate through the epitaxial layer and extend into the substrate layer, and an electrically insulating medium is filled in the first deep trenches to serve as an isolation structure; the second deep trench penetrates through the epitaxial layer and the second buried layer and extends into the substrate layer, and a conductive metal is filled in the second deep trench to form an electrical connection structure;
[0097] Through metal wiring, the fourth implantation region, the first implantation region and the second implantation region are connected to form a first electrode, and the fifth implantation region is connected to the second deep trench and jointly forms a second electrode with the substrate layer.
[0098] It can be understood that the method of this embodiment can be used to implement the device manufacturing of the above-mentioned Embodiment 1. Without conflict, the optional items in the above-mentioned Embodiment 1 are also applicable to this embodiment, so they will not be repeated here.
[0099] For the convenience of those of ordinary skill in the art to more clearly understand and implement the preparation method of the low-capacitance TVS structure described in the above embodiment, the following will describe some specific implementation processes with the first conductivity type being P-type and the second conductivity type being N-type to achieve Figure 3 the structure shown, including:
[0100] S1. Provide a P-type substrate layer;
[0101] S2. Form a PBL layer and an NBL layer by implantation on the front surface of the P-type substrate;
[0102] S3. Form an N-EPI layer on the PBL layer and the NBL layer by epitaxial growth;
[0103] S4. Form a PWELL region by boron implantation above the N-EPI layer;
[0104] S5. Form N1, N2, and N3 regions by phosphorus or arsenic implantation above the N-EPI layer;
[0105] S6. Form P1 and P2 regions by boron implantation on the N-EPI layer;
[0106] S7. In the N-EPI layer, form a deep trench isolation structure DT1 by silicon etching and SiO filling;
[0107] S8. In the N-EPI layer, form a tungsten plug structure DT2 by silicon etching and tungsten filling;
[0108] S9. Deposit SiO2 or other dielectrics on the surface of the N-EPI layer to form a hole dielectric layer;
[0109] S10. Through metal wiring, connect N2, P1, and P2 to form a positive electrode, and connect N3 to DT2 and the substrate to jointly form a negative electrode.
[0110] The same or similar reference numerals correspond to the same or similar components;
[0111] The terms describing the positional relationships in the drawings are for illustrative purposes only and should not be construed as limiting the present application; the structures, ratios, sizes, etc. shown in the drawings are only used to cooperate with the content disclosed in the specification for those skilled in the art to understand and read, and are not used to limit the implementation conditions of the present application, so they do not have technical essence. Any modification of the structure, change of the proportional relationship, or adjustment of the size, without affecting the efficacy and purpose that the present application can achieve, should still fall within the scope covered by the technical content disclosed in the present application.
[0112] It should be noted that, without conflict, the embodiments and features in the embodiments of the present application can be combined with each other.
[0113] In different specific implementations, the method or system described in the present application can be implemented in software, hardware, or a combination thereof. In addition, the order of the steps of the method can be changed, and various elements can be added, reordered, combined, omitted, modified, etc.
[0114] Obviously, the above embodiments of the present application are merely examples for clearly explaining the present application, rather than limitations on the implementation manners of the present application, and are not used to limit the present application. For those of ordinary skill in the art, other different forms of changes or variations can be made on the basis of the above description. Each discrete structure / functional module or unit can be integrated together to form an independent part, or each module can exist alone, or two or more modules can be integrated to form an independent part. The structures and functions of the discrete components can be implemented as combined structures or components. It is not necessary and impossible to enumerate all the implementation manners here. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present application shall be included within the protection scope of the claims of the present application.
Claims
1. A low-capacitance TVS structure with a low clamping voltage, characterized in that Comprising: A substrate layer of a first conductivity type, a first buried layer of a first conductivity type, a second buried layer of a second conductivity type, an epitaxial layer of a second conductivity type, a well region of a first conductivity type, a first deep trench, a second deep trench, and a first implantation region of a first conductivity type, a second implantation region of a first conductivity type, a third implantation region of a second conductivity type, a fourth implantation region of a second conductivity type, and a fifth implantation region of a second conductivity type; wherein, The epitaxial layer is disposed above and in contact with the substrate layer, and the first buried layer and the second buried layer are sandwiched between the bottom surface of the epitaxial layer and the top surface of the substrate layer; A well region is formed at one side top of the epitaxial layer and is in the same longitudinal extension direction as the first buried layer; a first implantation region and a fourth implantation region are formed on the inner top surface of the well region, and the fourth implantation region is distributed on both sides of the first implantation region, and third implantation regions are formed on both outer sides of the well region; A second implantation region and a fifth implantation region are formed at the other side top of the epitaxial layer and are in the same longitudinal extension direction as the second buried layer; A plurality of the first deep trenches as isolation structures penetrate the epitaxial layer and extend into the substrate layer, and the second deep trench as an electrical connection structure penetrates the epitaxial layer and the second buried layer and extends into the substrate layer; The first implantation region, the fourth implantation region and the second implantation region are connected by metal wiring and jointly form a first electrode, and the fifth implantation region and the second deep trench are connected by metal wiring and jointly form a second electrode with the substrate layer.
2. The low-capacitance TVS structure with a low clamping voltage according to claim 1, characterized in that The substrate layer is made of a silicon material of a first conductivity type, with a resistivity ranging from 0.001 - 0.02 ohm.cm, and the doping element is an element of the first conductivity type.
3. A low-capacitance TVS structure with a low clamping voltage according to claim 1, characterized in that, The implanted element of the first buried layer is an element of the first conductivity type, with an implantation dose of 1.0E13 - 1.0E15, and a diffusion temperature of 1050°C - 1200°C; the implanted element of the second buried layer is an element of the second conductivity type, with an implantation dose of 1.0E13 - 1.0E15, and a diffusion temperature of 1050°C - 1200°C.
4. A low-capacitance TVS structure with a low clamping voltage according to claim 1, characterized in that, The doping element of the epitaxial layer is an element of the second conductivity type, with a resistivity of 100 - 300 ohm.cm.
5. A low-capacitance TVS structure with a low clamping voltage according to claim 1, characterized in that, The implanted element of the well region is an element of the first conductivity type, with an implantation dose of 1.0E13 - 1.0E15, and a diffusion temperature of 1050°C - 1150°C.
6. The low-capacitance TVS structure with a low clamping voltage according to claim 1, wherein, The implanted elements of the first implantation region and the second implantation region are elements of the first conductivity type, with an implantation dose of 1.0E14 - 1.0E16, and a diffusion temperature of 900°C - 1100°C; and / or, the implanted elements of the third implantation region, the fourth implantation region and the fifth implantation region are elements of the second conductivity type, with an implantation dose of 1.0E14 - 1.0E16, and a diffusion temperature of 900°C - 1100°C.
7. A low-capacitance TVS structure with a low clamping voltage according to claim 1, characterized in that, The first deep trench is filled with an electrically insulating dielectric, with a width of 0.5μm - 2.0μm and a depth of 5μm - 30μm; the second deep trench is filled with tungsten metal, with a width of 1.0μm - 4.0μm and a depth of 5μm - 30μm.
8. A low-capacitance TVS structure with a low clamping voltage according to claim 1, characterized in that, It further includes a hole dielectric layer covering the top surface of the epitaxial layer and exposing the first implantation region, the second implantation region, the fourth implantation region, the fifth implantation region, and the second deep trench. The hole dielectric layer is made of silicon dioxide, silicon nitride, or a combined structure of both.
9. A low-capacitance TVS structure with a low clamping voltage according to any one of claims 1-8, characterized in that, AlSiCu, Al, or Ag is used as the electrode metal, and an ohmic contact layer is formed with a metal thickness of 2 μm - 6 μm.
10. A preparation method of a low-capacitance TVS structure, characterized in that, It includes: Providing a first-conductivity-type substrate as the substrate layer; Forming a first buried layer of the first-conductivity type and a second buried layer of the second-conductivity type on the top of the substrate layer by implantation; Forming an epitaxial layer of the second-conductivity type on the first buried layer and the second buried layer by epitaxial growth; Forming a well region of the first-conductivity type by implanting a first-conductivity-type element on the top of the epitaxial layer; wherein, the well region and the first buried layer are in the same longitudinal extension direction; Forming a first implantation region and a second implantation region of the first-conductivity type by implanting a first-conductivity-type element on the top of the well region and on the top of the epitaxial layer near the second buried layer side, forming a third implantation region, a fourth implantation region, and a fifth implantation region of the second-conductivity type by implanting a second-conductivity-type element; wherein, the first implantation region and the fourth implantation region are formed on the inner top surface of the well region, and the fourth implantation region is distributed on both sides of the first implantation region, the third implantation region is formed on both outer sides of the well region, the second implantation region and the fifth implantation region are formed on the top of the epitaxial layer and are in the same longitudinal extension direction as the second buried layer; In the epitaxial layer, forming a first deep trench and a second deep trench by a silicon etching method; wherein, a plurality of the first deep trenches penetrate through the epitaxial layer and extend into the substrate layer, and the first deep trenches are filled with an electrically insulating dielectric to serve as an isolation structure; the second deep trench penetrates through the epitaxial layer and the second buried layer and extends into the substrate layer, and the second deep trench is filled with a conductive metal to form an electrical connection structure; Through metal wiring, connecting the fourth implantation region, the first implantation region, and the second implantation region to form a first electrode, and connecting the fifth implantation region and the second deep trench and jointly forming a second electrode with the substrate layer.