Analog integrated circuit wiring method and system, electronic equipment and storage medium

Abstract

The invention discloses an analog integrated circuit wiring method and system, electronic equipment and a storage medium, and the method comprises the steps: obtaining a preset net, and generating a minimum spanning tree according to the preset net; wherein the minimum spanning tree comprises a plurality of preset pin areas; determining pin priority data corresponding to the preset pin area according to a preset sorting mechanism; wherein the preset sorting mechanism is determined through a Manhattan distance algorithm; performing wiring planning through a mode wiring algorithm according to the pin priority data and the minimum spanning tree to obtain preset wiring data; performing design rule inspection on the preset wiring data to obtain an inspection result; and when it is determined that the inspection result is passed, generating a target wiring file according to preset wiring data. According to the embodiment of the invention, the wiring efficiency and quality of the analog integrated circuit can be effectively improved, so that the performance and reliability of the analog integrated circuit are improved. The circuit can be widely applied to the technical field of integrated circuits.

Description

Technical Field

[0001] The present application relates to the field of integrated circuit technology, and in particular, to a method, a system, an electronic device, and a storage medium for routing analog integrated circuits. Background Art

[0002] With the rapid development of integrated circuit manufacturing technology, the integration density and complexity of chips have been significantly improved, and the routing difficulty of VLSI (Very Large Scale Integration) has also increased substantially. The number and density of signal nets in chip design continue to climb, making traditional routing algorithms, such as the maze routing algorithm, face serious performance bottlenecks in high-complexity scenarios. Among them, in the layout design of analog circuits, due to the particularity of analog signals, routing needs to solve more complex problems. The signals of analog circuits are extremely sensitive to path length, impedance matching, and signal interference. Any slight deviation will have a significant impact on signal integrity. In this case, routing not only needs to consider reducing signal delay and phase distortion, but also needs to focus on solving the influence of parasitic capacitance and parasitic inductance on high-frequency signal transmission, so as to optimize the overall performance of the circuit. In related technologies, during the routing process of analog integrated circuits, traditional routing algorithms, such as the maze routing algorithm, can find the global optimal solution through depth-first search, etc., but the efficiency of routing for large-scale pins is low, and the quality of the layout path is generally average, and it is easy to have negative impacts on circuit thermal management such as increased signal propagation delay, decreased electromagnetic interference characteristics, and local heat concentration, resulting in reduced circuit performance and reliability.

[0003] In summary, the technical problems existing in related technologies need to be improved. Summary of the Invention

[0004] The main purpose of the embodiments of the present application is to propose a method, a system, an electronic device, and a storage medium for routing analog integrated circuits, which can effectively improve the efficiency and quality of routing analog integrated circuits, thereby improving the performance and reliability of analog integrated circuits.

[0005] To achieve the above object, on the one hand, an embodiment of the present application proposes a method for routing analog integrated circuits, and the method includes the following steps:

[0006] Obtain a preset net to generate a minimum spanning tree according to the preset net; wherein, the minimum spanning tree includes a plurality of preset pin regions;

[0007] Determine the pin priority data corresponding to the preset pin region according to a preset sorting mechanism; wherein, the preset sorting mechanism is determined by the Manhattan distance algorithm;

[0008] Perform routing planning through a pattern routing algorithm according to the pin priority data and the minimum spanning tree to obtain preset routing data;

[0009] Perform a design rule check on the preset wiring data to obtain a check result;

[0010] When it is determined that the check result is a pass, generate a target wiring file according to the preset wiring data.

[0011] In some embodiments, before performing the step of generating a target wiring file according to the preset wiring data, the method further includes:

[0012] Optimize and trim the preset wiring data through a preset trimming algorithm to obtain optimized wiring data.

[0013] In some embodiments, the step of determining the pin priority data corresponding to the preset pin region according to the preset sorting mechanism includes:

[0014] Determine boundary point distribution data according to the preset pin region;

[0015] Calculate the distance data between the device pins corresponding to the preset pin region and the target region position through the Manhattan distance algorithm according to the boundary point distribution data;

[0016] Determine the pin priority data according to the distance data and a preset signal threshold.

[0017] In some embodiments, the step of performing a wiring plan through a pattern wiring algorithm according to the pin priority data and the minimum spanning tree to obtain the preset wiring data includes:

[0018] Determine a preset characteristic value of a corresponding wiring edge according to the pin coordinate data of the minimum spanning tree;

[0019] Determine a pin region to be wired according to the pin priority data;

[0020] Determine an expected wiring pattern according to the preset characteristic value and the pin region to be wired, so as to perform a wiring plan through the expected wiring pattern to obtain the preset wiring data.

[0021] In some embodiments, the step of determining an expected wiring pattern according to the preset characteristic value and the pin region to be wired, so as to perform a wiring plan through the expected wiring pattern to obtain the preset wiring data includes:

[0022] When it is determined that the pin regions to be routed are on the same routing layer, a corresponding first eigenvalue is determined according to the pin regions to be routed and the preset eigenvalue, so as to perform a first routing planning process on the pin regions to be routed according to the first eigenvalue to obtain a first planning result; when it is determined that the first planning result is that the routing is not completed, a second routing planning process is performed on the pin regions to be routed according to the first planning result to obtain the preset routing data; wherein, the first routing planning process includes a two-dimensional single L-shaped routing mode or a straight-line routing mode, and the second routing planning process includes a two-dimensional double L-shaped routing mode or a two-dimensional Z-shaped routing mode;

[0023] Alternatively, when it is determined that the pin regions to be routed are on different routing layers, a corresponding second eigenvalue is determined according to the pin regions to be routed and the preset eigenvalue, so as to perform a third routing planning process on the pin regions to be routed according to the second eigenvalue to obtain a second planning result; when it is determined that the second planning result is that the routing is not completed, a fourth routing planning process is performed on the pin regions to be routed according to the second planning result to obtain the preset routing data; wherein, the third routing planning process includes a three-dimensional single L-shaped routing mode, a three-dimensional double L-shaped routing mode or a three-dimensional Z-shaped routing mode, and the fourth routing planning process includes a multi-source multi-sink routing mode.

[0024] In some embodiments, after performing the step of determining the pin priority data corresponding to the preset pin regions according to the preset sorting mechanism, the method further includes:

[0025] Determining a first pin region according to the pin priority data; wherein, the first pin region includes the preset pin regions with the same priority;

[0026] Adjusting the pin priority data according to the obstacle distribution density data of the first pin region within the preset region range through a preset activation function.

[0027] In some embodiments, the step of performing a design rule check on the preset routing data to obtain a check result includes:

[0028] Generating a via expansion rectangle according to the via data in the preset routing data;

[0029] Splitting the routing edges in the preset routing data to obtain preset disassembled edges; wherein, the preset disassembled edges include vertical edges and horizontal edges;

[0030] Expanding the preset disassembled edges according to preset expansion parameters to generate disassembled edge expansion rectangles;

[0031] Overlap judgment is respectively performed on the disassembled edge expansion rectangle and the via expansion rectangle according to the historical wiring rectangular area to obtain the inspection result; wherein, the historical wiring rectangular area includes the expanded rectangular area where wiring has been completed.

[0032] To achieve the above object, on the other hand, an embodiment of the present application proposes an analog integrated circuit wiring system, and the system includes:

[0033] A first module, configured to obtain a preset netlist to generate a minimum spanning tree according to the preset netlist; wherein, the minimum spanning tree includes a plurality of preset pin areas;

[0034] A second module, configured to determine pin priority data corresponding to the preset pin areas according to a preset sorting mechanism; wherein, the preset sorting mechanism is determined by the Manhattan distance algorithm;

[0035] A third module, configured to perform wiring planning through a pattern wiring algorithm according to the pin priority data and the minimum spanning tree to obtain preset wiring data;

[0036] A fourth module, configured to perform design rule checking on the preset wiring data to obtain an inspection result;

[0037] A fifth module, configured to generate a target wiring file according to the preset wiring data when it is determined that the inspection result is passed.

[0038] To achieve the above object, on the other hand, an embodiment of the present application proposes an electronic device, and the electronic device includes:

[0039] At least one processor;

[0040] At least one memory, configured to store at least one program;

[0041] When the at least one program is executed by the at least one processor, the at least one processor implements the above method.

[0042] To achieve the above object, on the other hand, an embodiment of the present application proposes a computer-readable storage medium, and the computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the above method is implemented.

[0043] The embodiments of the present application at least include the following beneficial effects: The present application provides a method, a system, an electronic device, and a storage medium for wiring a analog integrated circuit. The solution obtains a preset netlist and generates a minimum spanning tree including several preset pin regions according to the preset netlist. Then, the embodiments of the present invention determine the pin priority data corresponding to the preset pin regions according to a preset sorting mechanism determined by the Manhattan distance algorithm. Further, the embodiments of the present invention perform a wiring plan according to the pin priority data and the minimum spanning tree through a pattern wiring algorithm to obtain preset wiring data, and then perform a design rule check on the preset wiring data to obtain a check result. Correspondingly, when it is determined that the check result passes the check, the embodiments of the present invention generate a target wiring file according to the preset wiring data to complete the wiring of the analog integrated circuit. It is easy to understand that the embodiments of the present invention determine the pin priority data of the preset pin regions through a preset sorting mechanism determined by the Manhattan distance algorithm, so that the wiring can be made more efficient. At the same time, the embodiments of the present invention perform a wiring plan through a pattern wiring algorithm, effectively improving the wiring efficiency and quality of the analog integrated circuit, and performing a design rule check on the preset wiring data, thereby improving the reliability of the wiring of the analog integrated circuit, and further effectively improving the performance and reliability of the generated analog integrated circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] Figure 1 is a flowchart of the method for wiring an analog integrated circuit provided by the embodiments of the present invention;

[0045] Figure 2 is a schematic diagram of the minimum spanning tree provided by the embodiments of the present invention;

[0046] Figure 3 is a schematic diagram for discriminating the coincidence of pin rectangular regions provided by the embodiments of the present invention;

[0047] Figure 4 is a schematic diagram of pattern wiring based on eigenvalues provided by the embodiments of the present invention;

[0048] Figure 5 is a schematic diagram of same-layer pattern wiring provided by the embodiments of the present invention;

[0049] Figure 6 is a schematic diagram of different-layer pattern wiring provided by the embodiments of the present invention;

[0050] Figure 7 is a schematic diagram of multi-source multi-sink pattern wiring provided by the embodiments of the present invention;

[0051] Figure 8 is a schematic diagram of DRC discrimination provided by the embodiments of the present invention;

[0052] Figure 9 is a schematic diagram of the overall process of the method for wiring an analog integrated circuit provided by the embodiments of the present invention;

[0053] Figure 10 It is a schematic structural diagram of the analog integrated circuit wiring system provided by an embodiment of the present invention;

[0054] Figure 11 It is a schematic hardware structure diagram of an electronic device provided by an embodiment of the present invention. Detailed implementation manners

[0055] In order to make the objectives, technical solutions and advantages of the present application clearer, the present application will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application. When the following description refers to the accompanying drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The implementation manners described in the following exemplary embodiments do not represent all implementation manners consistent with the embodiments of the present application. They are only examples of devices and methods consistent with some aspects of the embodiments of the present application as detailed in the appended claims.

[0056] It can be understood that the terms "first", "second", etc. used in the present application may be used herein to describe various concepts, but unless otherwise specified, these concepts are not limited by these terms. These terms are only used to distinguish one concept from another. For example, without departing from the scope of the embodiments of the present application, the first information may also be referred to as the second information, and similarly, the second information may also be referred to as the first information. Depending on the context, the words "if", "when" as used herein may be interpreted as "when...", "while...", or "in response to determining".

[0057] The terms "at least one", "multiple", "each", "any one", etc. used in the present application, at least one includes one, two or more than two, multiple includes two or more than two, each refers to each of the corresponding multiple, and any one refers to any one of the multiple.

[0058] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the technical field to which the present application belongs. The terms used herein are only for the purpose of describing the embodiments of the present application and are not intended to limit the present application.

[0059] Before elaborating on the embodiments of the present application in detail, some nouns and terms involved in the embodiments of the present application will be described first. The nouns and terms involved in the embodiments of the present application are applicable to the following explanations.

[0060] Manhattan Distance: It is a geometric metric used to measure the sum of the absolute axis distances of two points in a standard coordinate system. It only considers the distance on the standard coordinate axis and ignores the distance in the diagonal direction.

[0061] R-tree spatial index algorithm: is a data structure used to efficiently query spatial data. It is a self-balancing tree data structure that organizes spatial data into multi-layer nodes based on the tree structure to quickly locate and access data. Accordingly, the R-tree spatial index algorithm establishes a spatial index through the circumscribed rectangle of a spatial entity.

[0062] Design Rule Checking (DRC): is a physical design process that aims to determine whether the design complies with a series of rules defined by the semiconductor manufacturer or designer, such as key parameters such as line width, line spacing, component spacing, power and ground layout, thereby ensuring the manufacturability and electrical performance of the design.

[0063] With the rapid development of integrated circuit manufacturing technology, the integration and complexity of chips have been significantly improved, and the wiring difficulty of VLSI (very large-scale integrated circuit) has also increased significantly. The number and density of signal line networks in chip design continue to rise, making traditional wiring algorithms, such as maze wiring algorithms, face serious performance bottlenecks in high-complexity scenarios. Among them, in analog circuit layout design, due to the particularity of analog signals, wiring needs to solve more complex problems. The signals of analog circuits are extremely sensitive to path length, impedance matching and signal interference, and any slight deviation will have a significant impact on signal integrity. In this case, wiring should not only consider reducing signal delay and phase distortion, but also focus on solving the impact of parasitic capacitance and parasitic inductance on high-frequency signal transmission, so as to optimize the overall performance of the circuit. In the related art, in the process of analog integrated circuit wiring, traditional wiring algorithms, such as maze wiring algorithms, can find the global optimal solution through depth-first search and other methods, but the efficiency of large-scale pin wiring is low, and the layout path quality is general. It is easy to increase signal propagation delay, reduce electromagnetic interference characteristics, and local heat concentration, which have negative effects on circuit thermal management, resulting in reduced circuit performance and reliability.

[0064] Exemplarily, for instance, although traditional maze routing algorithms can find the global optimal solution through methods such as depth - first search, the curvature of their paths and inefficiency in routing large - scale pins obviously cannot meet the requirements of modern integrated circuits. At the same time, in the layout of analog circuits, the horizontal and vertical coordinates of device pins can reach the order of 100,000, resulting in a sharp increase in the number of grids. In this case, the running time and resource occupancy of the maze algorithm increase exponentially. Additionally, the path curvature of the maze algorithm brings a series of negative impacts, including increased signal propagation delay, decreased electromagnetic interference characteristics, and negative impacts on circuit thermal management due to local heat concentration.

[0065] In view of this, in the embodiments of the present application, a method, system, electronic device, and storage medium for analog integrated circuit routing are provided. This solution obtains a preset netlist to generate a minimum spanning tree including several preset pin regions according to the preset netlist. Then, the embodiments of the present invention determine the pin priority data corresponding to the preset pin regions according to a preset sorting mechanism determined by the Manhattan distance algorithm. Further, the embodiments of the present invention perform routing planning through a pattern routing algorithm based on the pin priority data and the minimum spanning tree to obtain preset routing data, and then perform a design rule check on the preset routing data to obtain a check result. Correspondingly, when it is determined that the check result is passed, the embodiments of the present invention generate a target routing file according to the preset routing data to complete the analog integrated circuit routing, which can effectively improve the efficiency and quality of analog integrated circuit routing, thereby improving the performance and reliability of analog circuits.

[0066] The analog integrated circuit routing method provided by the embodiments of the present application relates to the field of integrated circuit technology. The analog integrated circuit routing method provided by the embodiments of the present application can be applied to terminals, servers, or software running on terminals or servers. In some embodiments, the terminal can be a smart phone, a tablet computer, a laptop computer, a desktop computer, a smart speaker, a smart watch, a vehicle terminal, etc., but is not limited thereto; the server side can be configured as an independent physical server, or a server cluster or distributed system composed of multiple physical servers, or a cloud server providing basic cloud computing services such as cloud services, cloud databases, cloud computing, cloud functions, cloud storage, network services, cloud communications, middleware services, domain name services, security services, CDN, and big data and artificial intelligence platforms. The server can also be a node server in a blockchain network; the software can be an application implementing the analog integrated circuit routing method, etc., but is not limited to the above forms.

[0067] This application can be used in numerous general - purpose or special - purpose computer system environments or configurations. For example: personal computers, server computers, handheld or portable devices, tablet devices, multi - processor systems, micro - processor - based systems, set - top boxes, programmable consumer electronics, network PCs, minicomputers, mainframe computers, distributed computing environments including any of the above systems or devices, and so on. This application can be described in the general context of computer - executable instructions executed by a computer, such as program modules. Generally, program modules include routines, programs, objects, components, data structures, etc. that perform specific tasks or implement specific abstract data types. This application can also be practiced in a distributed computing environment where tasks are performed by remote processing devices connected through a communication network. In a distributed computing environment, program modules can be located in local and remote computer storage media including storage devices.

[0068] Figure 1 FIG. is an alternative flowchart of the analog integrated circuit wiring method provided by an embodiment of this application. Figure 1 The method in may include but is not limited to steps S110 to S150.

[0069] Step S110: Obtain a preset netlist to generate a minimum spanning tree according to the preset netlist. Among them, the minimum spanning tree includes several preset pin regions.

[0070] Step S120: Determine the pin priority data corresponding to the preset pin regions according to a preset sorting mechanism. Among them, the preset sorting mechanism is determined by the Manhattan distance algorithm.

[0071] Step S130: Perform a routing plan according to the pin priority data and the minimum spanning tree through a pattern routing algorithm to obtain preset routing data.

[0072] Step S140: Perform a design rule check on the preset routing data to obtain a check result.

[0073] Step S150: When it is determined that the check result is passed, generate a target routing file according to the preset routing data.

[0074] During the working process of this specific embodiment, the embodiment of the present invention first obtains a preset netlist to generate a minimum spanning tree according to the preset netlist. Specifically, the minimum spanning tree in the embodiment of the present invention includes several preset pin regions. Among them, in the embodiment of the present invention, a preset netlist is first input, and the preset netlist is split into the minimum spanning tree edges of multiple pairs of rectangular regions, and each pin region (such as a two - pin region) is routed to generate a minimum spanning tree. For example, before routing in the embodiment of the present invention, the routing edges of multiple pairs of pins are first generated according to the specific distribution of the pins, so as to construct the minimum spanning tree of the preset pin regions, such asFigure 2 As shown. Additionally, during the process of generating the minimum spanning tree, the embodiments of the present invention calculate the shortest Manhattan distance between the pin rectangular regions as the weight, thereby optimizing the connection path and reducing the total wiring length. Then, the embodiments of the present invention determine the pin priority data corresponding to the preset pin regions according to a preset sorting mechanism. Specifically, the preset sorting mechanism in the embodiments of the present invention refers to a mechanism for sorting the priorities of each preset pin region, which is determined by the Manhattan distance algorithm, that is, the preset sorting mechanism is constructed based on the Manhattan distance algorithm. Among them, the pin priority data in the embodiments of the present invention refers to the wiring priorities of the current preset pin regions. Correspondingly, before wiring, the embodiments of the present invention first sort each preset pin region to obtain the corresponding pin priorities, and then perform subsequent wiring according to the pin priorities. For example, the preset pin regions with higher priorities are wired first, thereby effectively improving the wiring efficiency.

[0075] Further, the embodiment of the present invention performs wiring planning through a pattern wiring algorithm according to the pin priority data and the minimum spanning tree to obtain preset wiring data. Specifically, after determining the pin priority data of each preset pin area, the embodiment of the present invention performs separate wiring for each preset pin area based on the wiring edge of the minimum spanning tree according to the pin priority. At the same time, in the wiring process, the wiring length, the number of through holes, the curvature of the path, etc. are comprehensively considered, and the optimal solution is selected for wiring. Correspondingly, when wiring the preset pin area (such as the double-pin area), in order to limit the wiring to a fixed shape as much as possible in the early stage of wiring, the embodiment of the present invention performs wiring through a pattern wiring algorithm to obtain preset wiring data. For example, in the embodiment of the present invention, the pattern wiring includes L-type, U-type, and Z-type pattern wiring, wherein the L-type and Z-type will only search within the rectangular search box surrounded by the double pins, while the U-type will exceed the rectangular box, thereby interfering with the wiring space of other wire nets and resulting in a high density of obstacles. Next, the embodiment of the present invention performs a design rule check (DRC) on the preset wiring data to obtain a check result. When it is determined that the check result is passed, a target wiring file is generated according to the preset wiring data. Specifically, the embodiment of the present invention performs a design rule check on the preset wiring data to determine whether the wiring result in the preset wiring data violates the relevant design rules, including line width, line spacing and through-hole size, etc. Correspondingly, when it is determined that the inspection result is passed, that is, the preset wiring data does not violate the relevant design rules, the wiring is completed, the preset wiring data is used as the final wiring data, and the corresponding target wiring file is generated. For example, the embodiment of the present invention generates a GDS file based on the preset wiring data. In the process of generating the GDS file, the key parameters of the wiring and through-hole are first read, the path coordinates are dynamically adjusted, and then the paths of different layers are stored as independent FlexPath objects, and finally all the data are written to the GDS file. In addition, when it is determined that the inspection result is failed, the step of returning to the mode wiring is used to rewire the wiring area that does not meet the design rules.

[0076] It should be noted that the wiring capacity (e capacity ), use (e demand ) and overflow value (e overflow ) information. capacity represents the maximum number of network lines that edge e can pass through, e demand Indicates the number of network lines that edge e actually passes through, e overflow =max{0,e demand -e capacity}, if e overflow > 0, the edge e is called an overflow edge. In order to avoid the occurrence of overflow edges as much as possible and optimize the length of the routing path, the pattern routing algorithm is superior to the traditional routing algorithms, such as the maze routing algorithm.

[0077] In some embodiments of the present invention, before generating a target routing file according to preset routing data, the analog integrated circuit routing method provided by the embodiments of the present invention further includes but is not limited to the following steps:

[0078] Optimize and trim the preset routing data through a preset trimming algorithm to obtain optimized routing data.

[0079] In this specific embodiment, after the routing is completed in the embodiments of the present invention, the preset routing data is optimized and trimmed through a preset trimming algorithm to obtain optimized routing data. Specifically, the preset trimming algorithm in the embodiments of the present invention refers to a line segment trimming algorithm, such as the Liang-Barsky trimming algorithm, the Cohen-Sutherland trimming algorithm, or the Cyrus-Beck trimming algorithm, etc. Correspondingly, in the embodiments of the present invention, after routing, an optimization algorithm based on line segment overlap detection is used to remove redundant paths using the preset trimming algorithm to ensure the global connectivity and shortest path characteristics of the paths. Exemplarily, in the embodiments of the present invention, the overlapping region of the starting path and the ending path is trimmed, and the Liang-Barsky trimming algorithm is used. Among them, this algorithm trims the line segments overlapping with obstacles, removes the overlapping parts, and splices the remaining line segments to generate an optimized path, that is, obtains the optimized routing data. For example, when the starting point of the line segment is p0=(x0,y0) and the ending point is p1=(x1,y1), it can be represented by parameterizing the line segment as shown in the following formula (1):

[0080] P(t)=(1 - t)×P0 + t×P1 (1)

[0081] Wherein, in the formula, t represents the parameterized scale factor, and t is between 0 and 1. The boundary of the trimming region can be defined by four parameters as shown in the following formula (2):

[0082]

[0083] Correspondingly, the coordinates of the trimmed line segment in the embodiments of the present invention are as shown in the following formula (3):

[0084]

[0085] It is easy to understand that in the embodiments of the present invention, by optimizing and trimming the preset routing data through a preset trimming algorithm after passing the design rule check, it is possible to effectively trim the overlapping line segments, optimize the routing path, and thus ensure the efficiency and reliability of the circuit design.

[0086] In some embodiments of the present invention, determining the pin priority data corresponding to the preset pin region according to the preset sorting mechanism includes but is not limited to the following steps:

[0087] Determine the boundary point distribution data according to the preset pin area.

[0088] Calculate the distance data between the device pins corresponding to the preset pin area and the target area position through the Manhattan distance algorithm according to the boundary point distribution data.

[0089] Determine the pin priority data according to the distance data and the preset signal threshold.

[0090] In this specific embodiment, the embodiment of the present invention first determines the boundary point distribution data according to the preset pin area, so as to calculate the distance data between the device pins corresponding to the preset pin area and the target area position through the Manhattan distance algorithm, and then determine the pin priority data according to the distance data and the preset signal threshold. Specifically, the embodiment of the present invention dynamically evaluates by comprehensively considering the pin geometric position, connection requirements and wiring environment, so as to preferentially select the optimal pins for wiring. Correspondingly, the embodiment of the present invention first performs geometric analysis on the device pin area to establish the boundary point distribution of the rectangular area where the pin is located, so as to ensure that the pins with better positional relationship with the target area are preferentially considered during the wiring process. Secondly, the embodiment of the present invention combines the Manhattan distance and signal requirements to sort the pins. By calculating the Manhattan distance between each pin and the target area, the pins are selected according to the corresponding distance data and the preset signal threshold, and then the pins are sorted by priority from the dimensions of distance and signal to obtain the priority data. For example, the embodiment of the present invention preferentially selects the pins with shorter distances to reduce the signal path length and reduce the delay and loss.

[0091] In addition, for the wiring requirements of the double-pin rectangular area, the embodiment of the present invention first detects whether the pin areas are on the same layer, and the algorithm will sort the rectangular pins according to the priority, and the pins with higher priority are wired first. Among them, the embodiment of the present invention will detect whether the X or Y coordinates of the rectangular area coincide. As Figure 3 shown, the left side indicates that there is an overlapping area between Pin a and Pin b. At this time, the algorithm preferentially extracts a series of point pairs in the format of [((x1,y1),(x2,y2)),((x3,y3),(x4,y4)),...], and these point pairs represent the boundary points of the two rectangular areas in the overlapping part. Correspondingly, the wiring algorithm in the embodiment of the present invention will preferentially wire in these overlapping areas because the wiring paths in these areas are shorter and the wiring complexity is lower. At the same time, if the wiring in the overlapping area cannot meet all the requirements, the algorithm will sort the remaining points by priority. The sorting basis includes the density of obstacle blocks and the total wire length, and the point pairs that pass through the areas with lower obstacle density and shorter total wire length are preferentially selected. Each pair of points ((x1,y1),(x2,y2)) represents the points that satisfy the shortest Manhattan distance, and (x1,y1) is located on the starting rectangle and (x2,y2) is located on the ending rectangle. If there is no overlap, asFigure 3 As shown by Pins a and c on the right side in

[0092] In some embodiments of the present invention, a wiring plan is performed through a pattern wiring algorithm based on pin priority data and a minimum spanning tree to obtain preset wiring data, including but not limited to the following steps:

[0093] Determine the preset characteristic values of the corresponding wiring edges according to the pin coordinate data of the minimum spanning tree.

[0094] Determine the area of the pins to be wired according to the pin priority data.

[0095] Determine the expected wiring pattern according to the preset characteristic values and the area of the pins to be wired, so as to perform a wiring plan through the expected wiring pattern to obtain the preset wiring data.

[0096] In this specific embodiment, the present invention example first determines the preset characteristic values of the corresponding wiring edges according to the pin coordinate data of the minimum spanning tree. Specifically, in the embodiments of the present invention, the pin coordinate data refers to the horizontal and vertical coordinates corresponding to the wiring edges generated by the minimum spanning tree. For example, as Figure 4 shown, the present invention embodiment inputs the wiring edges generated by the minimum spanning tree, first identifies the wiring edges where the horizontal and vertical coordinates of the two pin points are not equal, and randomly assigns 0 or 1 as the characteristic value. At the same time, for the wiring edges where the horizontal or vertical coordinates of the two pin points are equal, the characteristic value 2 or 3 is assigned. Then, the present invention embodiment determines the area of the pins to be wired according to the pin priority data. Specifically, to improve the wiring efficiency, the present invention embodiment manages the priority sorting of the pins through a priority queue. All candidate pins are dynamically sorted according to the comprehensive priority and added to the priority queue. The wiring process selects the pins in order from high to low priority to determine the area of the pins to be wired, and the priority queue is updated in real time to adapt to the changes in the wiring environment, so as to ensure that the high-priority pins are used first, reduce the complexity of the wiring path, and improve the wiring speed and quality.

[0097] Furthermore, in the embodiments of the present invention, the desired routing pattern is determined based on the preset eigenvalue and the area of the pins to be routed, so as to perform routing planning through the desired routing pattern and obtain the preset routing data. Specifically, in the embodiments of the present invention, the desired routing pattern refers to the routing pattern determined based on the corresponding eigenvalue, such as straight-line pattern routing, U-shaped pattern routing, single-L-shaped pattern routing, and double-L-shaped pattern routing, etc. Correspondingly, in the embodiments of the present invention, the corresponding routing edge is first determined according to the area of the pins to be routed, and then the corresponding eigenvalue of the routing edge is obtained. Among them, each routing edge in the embodiments of the present invention is matched with a corresponding routing pattern according to its corresponding eigenvalue. For example, for a routing edge with an eigenvalue of 2 or 3, the embodiments of the present invention give priority to straight-line pattern routing. If the straight-line pattern routing cannot meet the requirements (such as encountering obstacles), then the embodiments of the present invention adopt U-shaped pattern routing. Among them, the U-shaped pattern routing ensures the integrity of the connection and the stability of signal transmission by detouring around the obstacles. At the same time, for a routing edge with an eigenvalue of 0 or 1, the embodiments of the present invention adopt single-L-shaped pattern routing or double-L-shaped pattern routing. Among them, the single-L-shaped pattern routing is suitable for simple corner connections, while the double-L-shaped pattern routing is suitable for more complex path planning, especially when multiple obstacles or specific areas need to be bypassed. It is easy to understand that in the embodiments of the present invention, the corresponding eigenvalue of each routing edge is first calculated based on the geometric shape, connection requirements, and complexity of the surrounding environment of each routing edge, and then according to the classification of the eigenvalues, the corresponding routing pattern (desired routing pattern) is matched for each routing edge. Correspondingly, in the embodiments of the present invention, routing planning is performed according to the determined desired routing pattern, an initial routing scheme is generated, and the preset routing data is obtained.

[0098] In some embodiments of the present invention, determining the desired routing pattern according to the preset eigenvalue and the area of the pins to be routed, so as to perform routing planning through the desired routing pattern and obtain the preset routing data, includes but is not limited to the following steps:

[0099] When it is determined that the area of the pins to be routed is on the same routing layer, the corresponding first eigenvalue is determined according to the area of the pins to be routed and the preset eigenvalue, so as to perform the first routing planning process on the area of the pins to be routed according to the first eigenvalue and obtain the first planning result. When it is determined that the first planning result is that the routing is not completed, the second routing planning process is performed on the area of the pins to be routed according to the first planning result, and the preset routing data is obtained. Among them, the first routing planning process includes two-dimensional single-L-shaped routing pattern or straight-line routing pattern, and the second routing planning process includes two-dimensional double-L-shaped routing pattern or two-dimensional Z-shaped routing pattern.

[0100] Alternatively, when it is determined that the pin regions to be routed are on different routing layers, a corresponding second eigenvalue is determined according to the pin regions to be routed and a preset eigenvalue, so as to perform a third routing planning process on the pin regions to be routed according to the second eigenvalue, and a second planning result is obtained. When it is determined that the second planning result is that the routing is not completed, a fourth routing planning process is performed on the pin regions to be routed according to the second planning result, and preset routing data is obtained. Among them, the third routing planning process includes a three-dimensional single L-shaped routing mode, a three-dimensional double L-shaped routing mode or a three-dimensional Z-shaped routing mode, and the fourth routing planning process includes a multi-source multi-sink routing mode.

[0101] In this specific embodiment, during routing, the embodiment of the present invention determines whether the read pin rectangular region, that is, the pins to be routed, are on the same layer. Specifically, when it is determined that the pin regions to be routed are on the same routing layer, the embodiment of the present invention determines a first eigenvalue according to the pin regions to be routed and a preset eigenvalue, so as to perform a first routing rule process on the pin regions to be routed according to the first eigenvalue, and a first planning result is obtained. Among them, the first routing rule process in the embodiment of the present invention includes a two-dimensional single L-shaped routing mode or a linear routing mode. Correspondingly, the first eigenvalue refers to the eigenvalue of the routing edge corresponding to the pins in the pin region to be routed. In addition, after the first routing planning process is completed, the embodiment of the present invention determines whether the routing is completed according to the first planning result. When it is determined that the routing is not completed, the embodiment of the present invention performs a second routing planning process on the pin regions to be routed according to the first planning result, and preset routing data is obtained. Among them, the second routing planning process in the embodiment of the present invention includes a two-dimensional double L-shaped routing mode or a two-dimensional Z-shaped routing mode. Exemplarily, as Figure 5 shown, when the pin regions are read on the same layer, the embodiment of the present invention performs routing in a corresponding mode according to the eigenvalues of the routing. First, a two-dimensional single L-shaped routing mode is adopted, and the path is divided into two strategies: horizontal priority and vertical priority. Then, by detecting the obstacles between the starting point and the ending point, the algorithm dynamically adjusts the path, and determines whether it is necessary to punch vias in the pin region according to the obstacle density. If the obstacle density is too high, it may cause the L-shaped path to be unable to search for an effective path. At this time, the uncompleted routing will be split and converted into a linear double via mode for routing, as Figure 5As shown in the straight-line wiring part in []. During this process, the embodiments of the present invention will search according to the priority of point pairs in the overlapping area. The straight-line wiring pattern will find two points p and q in the point pair. If the Y coordinates of the point pair are equal, then p is (inter_x, y), where inter_x is between the X coordinate ranges of this pair of points, and q is (inter_x1, y), where the range of inter_x1 is between inter_x and the maximum X coordinate of the point pair, and vias are drilled at points p and q. The algorithm will pre-judge whether the expansion box overlaps with the previous wiring shape. Correspondingly, when the wiring cannot be completed after the first wiring planning process is completed, the embodiments of the present invention use a two-way Z-shaped wiring pattern (i.e., a two-dimensional Z-shaped wiring pattern) based on the points within the pin area. Among them, when there is no coincidence in the x coordinate or y coordinate of the points on the boundaries of the two pin rectangles, the same-layer L-shaped wiring pattern is also preferentially used, and then the point pair with the shortest Manhattan distance is extracted for double L-shaped double via type (i.e., two-dimensional double L-shaped wiring pattern) wiring, and finally the remaining double pins are wired in a two-dimensional Z-shaped wiring pattern to ensure the completion of the wiring.

[0102] Further, when it is determined that the pin area to be wired is on different wiring layers, the embodiments of the present invention determine a second characteristic value according to the pin area to be wired and a preset characteristic value, so as to perform a third wiring planning process on the pin area to be wired according to the second characteristic value to obtain a second planning result. Specifically, the third wiring planning process in the embodiments of the present invention includes a three-dimensional single L-shaped wiring pattern, a three-dimensional double L-shaped wiring pattern, or a three-dimensional Z-shaped wiring pattern. Exemplarily, as Figure 6 shown, when the pin areas are not on the same layer, the embodiments of the present invention also perform the first-stage pattern wiring, and determine the desired wiring pattern to be used according to the second characteristic value, such as 3D L-shaped, Z-shaped, and double L-shaped wiring patterns (i.e., three-dimensional single L-shaped wiring pattern, three-dimensional double L-shaped wiring pattern, or three-dimensional Z-shaped wiring pattern) to meet the cross-layer wiring requirements. Among them, the three-dimensional single L-shaped wiring pattern is used for simple interlayer connection. When there are fewer obstacles between the starting point and the ending point, a horizontal or vertical path is preferentially selected, and the interlayer connection is realized by adding vias. The vias adopt the operation of continuous vias, such as Figure 6As shown in the continuous via strategy section, it is required that the geometric center points of the continuous vias coincide. Secondly, the routing path is composed of multi-point line segments (such as the starting point, inflection point, and ending point) to ensure the shortest overall path length. Correspondingly, the three-dimensional double L-shaped routing mode or the three-dimensional Z-shaped routing mode is used for more complex routing scenarios, such as cases with multiple obstacles or interlayer barriers. In this mode, the path is adjusted through the path cost function and combined with via position optimization to reduce the number of vias. Secondly, when the routing in the first stage is not completed, the embodiment of the present invention will perform the routing in the second stage mode of different layers. First, the edge migration process is performed on the edges to be routed, and then the routing in the multi-source multi-sink mode is implemented. If the routing in the single pin region mode is adopted, it may lead to an overly long wire length, thus having an adverse impact on the routing of subsequent edges. For example, as Figure 7 shown, Pin a and Pin b are routed in the L-shaped mode. However, when connecting Pin c and Pin a, since they are not on the same layer, a cross-layer L-shaped connection needs to be adopted. Such a connection method obviously results in an unoptimized wire length. To solve this problem, the embodiment of the present invention regards the routing edge connected to Pin a and Pin a as a new pin region, denoted as Pina'. When routing, only Pin b needs to be connected to Pin a', as Figure 7 shown. In this way, the embodiment of the present invention introduces Steiner points on the routing edge, thereby effectively shortening the wire length, optimizing the signal transmission path, and significantly reducing signal loss.

[0103] In some embodiments of the present invention, after executing to determine the pin priority data corresponding to the preset pin region according to the preset sorting mechanism, the analog integrated circuit routing method provided by the embodiment of the present invention further includes but is not limited to the following steps:

[0104] Determine the first pin region according to the pin priority data. Among them, the first pin region includes the preset pin regions with the same priority.

[0105] Adjust the pin priority data through a preset activation function according to the obstacle distribution density data of the first pin region within the preset region range.

[0106] In this specific embodiment, there may be cases where the priorities corresponding to each preset pin area are the same. In this case, the embodiment of the present invention first determines the preset pin areas with the same priority according to the pin priority data, that is, the first pin area, and then adjusts the pin priority data through a preset activation function according to the obstacle distribution density data of the first pin area within the preset area range. Specifically, in the embodiment of the present invention, the preset pin areas with the same priority are first selected through the priority data. Then, the embodiment of the present invention introduces the influencing factors of obstacle density and dynamic environment interference, and adjusts the priority data of the device pins by statistically calculating the obstacle distribution density around each pin and combining with a preset activation function (such as the Sigmoid function). Among them, the Sigmoid function in the embodiment of the present invention is expressed as shown in the following formula (4):

[0107]

[0108] Among them, in the formula, h usually takes 2, k usually takes 5, demand represents the wiring capacity at the current pin point, and capacity represents the congestion degree of the netlist.

[0109] Correspondingly, the embodiment of the present invention adjusts the pin priority data by introducing the influencing factors of obstacle density and dynamic environment interference, so that the wiring process is more inclined to select the pins located in the low-density area, thereby reducing the risk of signal interference caused by obstacles during the wiring process.

[0110] In some embodiments of the present invention, before performing the wiring planning according to the pin priority data and the minimum spanning tree through the pattern wiring algorithm to obtain the preset wiring data, the analog integrated circuit wiring method provided by the embodiment of the present invention further includes but is not limited to the following steps:

[0111] Calculate the expected wiring step according to the obstacle density data, the path complexity data, and the target area distance data.

[0112] Perform dynamic step adjustment according to the expected wiring step.

[0113] In this specific embodiment, before performing pattern routing, the embodiment of the present invention first determines the routing compensation according to the layout size of the analog circuit. Correspondingly, the embodiment of the present invention calculates the expected routing step length based on the obstacle density data, path complexity data, and target area distance data, and then dynamically adjusts the step length according to the expected routing step length. Specifically, in the embodiment of the present invention, for a short distance or an area with dense obstacles, the embodiment of the present invention reduces the step length to improve the search accuracy. At the same time, for a long distance or an area with sparse obstacles, the embodiment of the present invention increases the step length to speed up the search. In addition, before performing pattern routing, the embodiment of the present invention also performs priority stratification on the obstacles, and establishes a priority stratification according to the size and distribution of the obstacles. Correspondingly, the embodiment of the present invention preferentially avoids large obstacles and tolerates slight path offsets.

[0114] In some embodiments of the present invention, a design rule check is performed on the preset routing data to obtain a check result, including but not limited to the following steps:

[0115] Generate a via extension rectangle according to the via data in the preset routing data.

[0116] Split the routing edges in the preset routing data to obtain preset disassembled edges. The preset disassembled edges include vertical edges and horizontal edges.

[0117] Expand the preset disassembled edges according to the preset expansion parameters to generate a disassembled edge expansion rectangle.

[0118] Perform an overlap judgment on the disassembled edge expansion rectangle and the via extension rectangle respectively according to the historical routing rectangle area to obtain a check result. The historical routing rectangle area includes the extended rectangle area where the routing has been completed.

[0119] In this specific embodiment, the embodiment of the present invention generates a via extension rectangle according to the via data in the preset routing data. Specifically, the embodiment of the present invention first processes the vias on the corresponding routing edges in the preset routing data. Among them, such as Figure 8As shown, if the pin point is not a Steiner point, the extended rectangular area is shown by the black dotted line in the figure, and the via point extends outwardly a rectangle with a length and width of 1 / 2*(via_length+spacing) respectively, generating a via extension rectangle. In addition, if the pin point is a Steiner point, the extended rectangular area will be larger to include possible multiple connection points. Then, the embodiment of the present invention splits the wiring edge in the preset wiring data to obtain a preset disassembly edge, and then expands the preset disassembly edge according to the preset expansion parameter to generate a disassembly edge expansion rectangle. Specifically, the preset disassembly edge in the embodiment of the present invention includes a vertical edge and a horizontal edge. Correspondingly, the preset expansion parameter in the embodiment of the present invention refers to the spacing parameter for the outward expansion of different disassembly edges. For example, for the processing of the wiring edge, from the wiring edge pin point b to the pin point a, the wiring edge is first disassembled into a horizontal edge and a vertical edge. Then, the embodiment of the present invention expands outwardly a spacing of 1 / 2*(minWidth+spacing) on each type of edge, and returns the expanded rectangle, that is, the disassembly edge expansion rectangle. Furthermore, the embodiment of the present invention performs overlap judgment on the disassembly edge extension rectangle and the through-hole extension rectangle respectively according to the historical wiring rectangular area to obtain the inspection result. Specifically, the historical rectangular area in the embodiment of the present invention includes the extended rectangular area corresponding to the wiring edge of the completed wiring. Accordingly, the embodiment of the present invention implements DRC discrimination through overlap judgment and processing, and judges whether all returned rectangular areas (disassembly edge extension rectangle and through-hole extension rectangle) overlap with the previously routed rectangular area class (historical wiring rectangular area). If there is overlap, the DRC constraint is violated, and the wiring edge is marked for removal and re-routing. On the contrary, if there is no overlap, it is added to the rectangular area class, and the pattern wiring of the next edge is continued. Through the above method, the algorithm of the embodiment of the present invention can quickly complete the pattern wiring while satisfying the DRC constraint.

[0120] It should be noted that, in order to improve real-time performance and efficiency, the embodiment of the present invention uses R-Tree indexing technology to perform spatial index storage on the completed wiring shapes, and quickly screens obstacle areas that may overlap with the expansion box through spatial queries, avoiding the performance overhead caused by global calculations. Accordingly, the generation of the expansion box in the embodiment of the present invention dynamically adjusts the protection distance based on the cross-layer wiring situation. For the cross-layer through-hole area, the protection range of the expansion boxes of the upper and lower layers is superimposed to ensure that the inter-layer isolation requirements are met. At the same time, the embodiment of the present invention performs conflict judgment on the overlapping areas of the upper and lower layers of the through-hole, and through-holes at different levels have different spacing constraints.

[0121] It should be noted that, in the embodiment of the present invention, when performing iterative routing, the objectives such as path length, number of inflection points and number of through holes are integrated into a single optimization objective through a cost function, as shown in the following formula (5):

[0122] C = α×L + β×N + γ×V (5)

[0123] Among them, in the formula, L represents the path length, N represents the number of corners, V represents the number of vias, and α, β, and γ represent weight coefficients.

[0124] In addition, according to the distribution of obstacles around the path and the position of the terminal device, the optimal routing mode is dynamically selected. The L-shaped, Z-shaped, or double-L-shaped routing modes are flexibly switched at different stages to meet diverse routing requirements. When approaching the end point, the path points with sparse obstacles are preferentially selected to reduce the number of final adjustments.

[0125] In addition, in some embodiments of the present invention, after the routing is completed, the three-dimensional visualization display of the routing path, vias, obstacles, start point, and end point is realized by using the Plotly library. Exemplarily, the embodiments of the present invention first define input parameters, including the rectangular frames of the start point and the end point, the path list of the start layer, the path list of the end layer, the cross-layer path list, and the via information of multiple layers. Then, the embodiments of the present invention create a three-dimensional graphic object for subsequent element addition. Then, the embodiments of the present invention define all relevant layer numbers to ensure that the layer numbers where the start point and the end point are located are correctly included and sorted. Correspondingly, during the visualization process, the system draws the rectangular frames of each pin, and by defining the coordinates of the four corners and using the Mesh3d method, renders them as red rectangular frames to intuitively represent the start point and the end point. Subsequently, the embodiments of the present invention generate different color rectangles to represent different paths. For example, the system traverses the path list of the start layer, generates blue rectangles to represent the paths, and adds them to the graphic. Similarly, the paths of the end layer are drawn by traversing the path list of the end layer, and green rectangles are used to represent them. In addition, the system can also perform the visualization of cross-layer paths, traverse the cross-layer path list and display them using purple rectangles. At the same time, for the drawing of vias, the system draws the lines of the vias according to the coordinates and layer information of the vias, and generates the rectangular frames of the vias by using the Mesh3d method, and differentiates them with different colors for easy identification. Finally, the embodiments of the present invention ensure the accuracy and aesthetics of the visualization effect by setting the scale, axis labels, and range of the graphic. The system can effectively display the layout of three-dimensional routing, provide an intuitive view, facilitate designers to analyze and optimize, and has significant application value and technical advantages.

[0126] Next, in combination with a specific analog integrated circuit routing scenario, the solutions of the embodiments of the present invention will be introduced and described in detail:

[0127] Exemplarily, as Figure 9As shown, in the embodiment of the present invention, a netlist and process files are first obtained to simulate a schematic diagram through the netlist, determine which pins should be connected, and obtain different line widths and design rule requirements through different process files. Then, after obtaining the pin connection relationship, the number of wiring layers, and wiring-related dimensions (such as via rectangles, line widths, and line pitches, etc.), the embodiment of the present invention splits the wiring edges based on the minimum spanning tree, thereby splitting the net into the minimum spanning tree edges of multiple pairs of rectangular regions, and then routes each two-pin rectangular region. Correspondingly, the embodiment of the present invention performs the minimum spanning tree splitting and point selection of the pin rectangular region through priority orientation. Correspondingly, the embodiment of the present invention determines the corresponding eigenvalue according to the abscissa and ordinate of the two pin points of the wiring edge, and then determines the corresponding expected wiring pattern according to the eigenvalue. Among them, during the wiring process, the embodiment of the present invention first detects whether the pin regions are on the same layer. When it is determined that the pin regions are on the same layer, the embodiment of the present invention sorts the rectangular pins according to the corresponding priority, and the pins with higher priority are wired first. Among them, during the wiring process on the same layer, the embodiment of the present invention performs pattern wiring according to the expected wiring pattern determined by the eigenvalue, such as the L-shaped and straight-line wiring patterns, and determines whether the DRC rule is violated through a virtual extension box. Correspondingly, when it is detected that the pin regions are not on the same layer, the embodiment of the present invention also performs pattern wiring according to the expected wiring pattern determined by the eigenvalue, such as the L-shaped, double-L-shaped, and Z-shaped wiring patterns, and determines whether the DRC rule is violated through a virtual extension box. When it is determined that the inspection result of the design rule check passes, the embodiment of the present invention uses the Liang-Barsky clipping algorithm to clip the overlapping part in the wiring data, thereby optimizing the wiring line segments, obtaining the final wiring data, and generating the corresponding wiring GDS file.

[0128] It should be noted that the embodiments of the present invention combine the particularity of the pins of the analog circuit, use a three-dimensional grid diagram model to represent the routing resources, and optimize the routing of the same layer and cross-layer by means of pattern routing strategies (such as L-shaped, Z-shaped, double L-shaped, etc.). During the routing process, the embodiments of the present invention can dynamically evaluate the priority of the pins and adjust the path by combining the obstacle density and dynamic environmental factors. This ability of dynamic adjustment makes the routing more efficient, especially in the case of a large number of signal lines or a complex distribution of pin areas, significantly reducing the number of vias, the path length, and the risk of signal interference. At the same time, for the requirement of the analog signal for path consistency during the routing process, the embodiments of the present invention manage the priority sorting of the pins through a priority queue mechanism, comprehensively considering the Manhattan distance, geometric position, and signal requirements, and preferentially select the pin with the shortest path and the least interference at each step. In addition, the embodiments of the present invention use the R-tree spatial index technology to quickly query the spatial relationship between the path and the obstacles, thereby significantly reducing the overhead of global calculation and improving the routing speed and resource utilization rate. In the cross-layer routing scenario, the embodiments of the present invention adopt a topological structure of continuous vias, and combine a path cost function and a dynamic step size adjustment strategy to preferentially select the layer with the lowest obstacle density for path planning, thereby effectively improving the efficiency and success rate of cross-layer routing, reducing the number of cross-layer vias, and optimizing the path length.

[0129] Please refer to Figure 10 , the embodiments of the present application also provide an analog integrated circuit routing system, which can implement the above-mentioned analog integrated circuit routing method. The system includes:

[0130] The first module 210 is used to obtain a preset netlist to generate a minimum spanning tree according to the preset netlist. Among them, the minimum spanning tree includes several preset pin areas.

[0131] The second module 220 is used to determine the pin priority data corresponding to the preset pin area according to a preset sorting mechanism. Among them, the preset sorting mechanism is determined by the Manhattan distance algorithm.

[0132] The third module 230 is used to perform routing planning through a pattern routing algorithm according to the pin priority data and the minimum spanning tree to obtain preset routing data.

[0133] The fourth module 240 is used to check the design rules for the preset routing data to obtain a check result.

[0134] The fifth module 250 is used to generate a target routing file according to the preset routing data when it is determined that the check result is passed.

[0135] It can be understood that the content in the above method embodiments is applicable to the system embodiments of the present application. The functions specifically implemented in the system embodiments of the present application are the same as those in the above method embodiments, and the beneficial effects achieved are also the same as those in the above method embodiments.

[0136] An embodiment of the present application also provides an electronic device, which includes a memory and a processor. The memory stores a computer program, and when the processor executes the computer program, the above-mentioned analog integrated circuit wiring method is implemented. The electronic device can be any intelligent terminal including a tablet computer, a vehicle-mounted computer, etc.

[0137] It can be understood that the content in the above method embodiments is applicable to the device embodiments of the present application. The functions specifically implemented in the device embodiments of the present application are the same as those in the above method embodiments, and the beneficial effects achieved are also the same as those in the above method embodiments.

[0138] Please refer to Figure 11 , Figure 11 which shows the hardware structure of an electronic device in another embodiment. The electronic device includes:

[0139] A processor 310, which can be implemented in ways such as a general-purpose CPU (Central Processing Unit), a microprocessor, an application-specific integrated circuit (ASIC), or one or more integrated circuits, and is used to execute relevant programs to implement the technical solutions provided in the embodiments of the present application;

[0140] A memory 320, which can be implemented in forms such as a read-only memory (ROM), a static storage device, a dynamic storage device, or a random access memory (RAM). The memory 320 can store an operating system and other application programs. When implementing the technical solutions provided in the embodiments of this specification through software or firmware, the relevant program codes are stored in the memory 320 and are called by the processor 310 to execute the analog integrated circuit wiring method in the embodiments of the present application;

[0141] An input / output interface 330, which is used to implement information input and output;

[0142] A communication interface 340, which is used to implement communication and interaction between the device and other devices. Communication can be achieved through wired means (such as USB, network cable, etc.) or wireless means (such as mobile network, WIFI, Bluetooth, etc.);

[0143] A bus 350 transmits information between various components of the device (such as a processor 310, a memory 320, an input / output interface 330, and a communication interface 340);

[0144] Among them, the processor 310, the memory 320, the input / output interface 330, and the communication interface 340 are communicatively connected to each other inside the device through the bus 350.

[0145] An embodiment of the present application also provides a computer-readable storage medium. The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the above-mentioned method for wiring an analog integrated circuit is implemented.

[0146] It can be understood that the content in the above method embodiments is applicable to the embodiments of this storage medium. The functions specifically implemented by the embodiments of this storage medium are the same as those of the above method embodiments, and the beneficial effects achieved are also the same as those of the above method embodiments.

[0147] As a non-transitory computer-readable storage medium, the memory can be used to store non-transitory software programs and non-transitory computer-executable programs. In addition, the memory may include high-speed random access memory, and may also include non-transitory memory, such as at least one magnetic disk storage device, a flash memory device, or other non-transitory solid-state storage devices. In some embodiments, the memory may optionally include a memory remotely disposed relative to the processor, and these remote memories can be connected to the processor through a network. Examples of the above network include but are not limited to the Internet, an enterprise intranet, a local area network, a mobile communication network, and combinations thereof.

[0148] The embodiments described in the embodiments of the present application are for more clearly illustrating the technical solutions of the embodiments of the present application, and do not constitute a limitation on the technical solutions provided by the embodiments of the present application. Those skilled in the art know that with the evolution of technology and the emergence of new application scenarios, the technical solutions provided by the embodiments of the present application are equally applicable to similar technical problems.

[0149] Those skilled in the art can understand that the technical solutions shown in the figures do not constitute a limitation on the embodiments of the present application, and may include more or fewer steps than those shown in the figures, or combine certain steps, or different steps.

[0150] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separated, that is, they may be located in one place, or may be distributed to multiple network units. Some or all of the modules can be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0151] Those of ordinary skill in the art will understand that all or some of the steps in the methods disclosed above, and the functional modules / units in systems and devices, can be implemented as software, firmware, hardware, and appropriate combinations thereof.

[0152] The terms "first", "second", "third", "fourth", etc. (if any) in the specification of this application and the above-mentioned drawings are used to distinguish similar objects, and do not necessarily describe a specific order or sequence. It should be understood that the data used in this way can be interchanged under appropriate circumstances, so that the embodiments of this application described here can be implemented in an order other than those illustrated or described here. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or units does not necessarily have to be limited to those steps or units clearly listed, but may include other steps or units not clearly listed or inherent to these processes, methods, products, or devices.

[0153] In the several embodiments provided by this application, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are merely illustrative. For example, the above-mentioned division of units is only a logical function division, and there may be other division methods in actual implementation. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the displayed or discussed coupling, direct coupling, or communication connection to each other can be through some interfaces, and the indirect coupling or communication connection of devices or units can be in electrical, mechanical, or other forms.

[0154] The units described above as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they can be located in one place, or distributed to multiple network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0155] In addition, the functional units in each embodiment of this application can be integrated in a processing unit, or each unit can exist physically alone, or two or more units can be integrated in one unit. The above-mentioned integrated units can be implemented in the form of hardware or in the form of software functional units.

[0156] When the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or all or part of this technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes multiple instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods of various embodiments of this application. The aforementioned storage medium includes: various media that can store programs, such as USB flash drives, mobile hard disks, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical discs.

[0157] The preferred embodiments of the embodiments of this application have been described above with reference to the accompanying drawings. This does not limit the scope of the rights of the embodiments of this application. Any modifications, equivalent replacements, and improvements made by those skilled in the art without departing from the scope and essence of the embodiments of this application shall be within the scope of the rights of the embodiments of this application.

Claims

1. A method for wiring an analog integrated circuit, characterized in that, The method includes the following steps: Obtain a preset wire network to generate a minimum spanning tree according to the preset wire network; wherein, the minimum spanning tree includes a plurality of preset pin regions; Determine the pin priority data corresponding to the preset pin regions according to a preset sorting mechanism; wherein, the preset sorting mechanism is determined by the Manhattan distance algorithm; Perform a wiring plan according to the pin priority data and the minimum spanning tree through a pattern wiring algorithm to obtain preset wiring data; Perform a design rule check on the preset wiring data to obtain a check result; When it is determined that the check result is passed, generate a target wiring file according to the preset wiring data.

2. The method according to claim 1, wherein Before performing the step of generating the target wiring file according to the preset wiring data, the method further includes: Optimize and trim the preset wiring data through a preset trimming algorithm to obtain optimized wiring data.

3. The method according to claim 1, wherein The step of determining the pin priority data corresponding to the preset pin regions according to the preset sorting mechanism includes: Determine boundary point distribution data according to the preset pin regions; Calculate the distance data between the device pins corresponding to the preset pin regions and the target region position through the Manhattan distance algorithm according to the boundary point distribution data; Determine the pin priority data according to the distance data and a preset signal threshold.

4. The method according to claim 1, wherein The step of performing a wiring plan according to the pin priority data and the minimum spanning tree through a pattern wiring algorithm to obtain preset wiring data includes: Determine the preset characteristic values of the corresponding wiring edges according to the pin coordinate data of the minimum spanning tree; Determine the pin regions to be wired according to the pin priority data; Determine an expected wiring pattern according to the preset characteristic values and the pin regions to be wired, and perform a wiring plan through the expected wiring pattern to obtain the preset wiring data.

5. The method according to claim 4, characterized in that, The step of determining an expected wiring pattern according to the preset characteristic values and the pin regions to be wired, and performing a wiring plan through the expected wiring pattern to obtain the preset wiring data includes: When it is determined that the pin regions to be wired are on the same wiring layer, determine corresponding first characteristic values according to the pin regions to be wired and the preset characteristic values, and perform a first wiring plan process on the pin regions to be wired according to the first characteristic values to obtain a first planning result; when it is determined that the first planning result is that the wiring is not completed, perform a second wiring plan process on the pin regions to be wired according to the first planning result to obtain the preset wiring data; wherein, the first wiring plan process includes a two-dimensional single L-shaped wiring pattern or a linear wiring pattern, and the second wiring plan process includes a two-dimensional double L-shaped wiring pattern or a two-dimensional Z-shaped wiring pattern; Alternatively, when it is determined that the pin regions to be routed are on different routing layers, a corresponding second eigenvalue is determined according to the pin regions to be routed and the preset eigenvalue, so as to perform a third routing planning process on the pin regions to be routed according to the second eigenvalue to obtain a second planning result; when it is determined that the second planning result is that the routing is not completed, a fourth routing planning process is performed on the pin regions to be routed according to the second planning result to obtain the preset routing data; wherein, the third routing planning process includes a three-dimensional single L-shaped routing mode, a three-dimensional double L-shaped routing mode or a three-dimensional Z-shaped routing mode, and the fourth routing planning process includes a multi-source multi-sink routing mode.

6. The method according to claim 1, characterized in that After performing the step of determining the pin priority data corresponding to the preset pin regions according to the preset sorting mechanism, the method further includes: determining a first pin region according to the pin priority data; wherein, the first pin region includes the preset pin regions with the same priority; adjusting the pin priority data according to the obstacle distribution density data of the first pin region within the preset region range through a preset activation function.

7. The method according to claim 1, wherein The step of performing a design rule check on the preset routing data to obtain a check result includes: generating a via extension rectangle according to the via data in the preset routing data; splitting the routing edges in the preset routing data to obtain preset disassembled edges; wherein, the preset disassembled edges include vertical edges and horizontal edges; extending the preset disassembled edges according to preset extension parameters to generate disassembled edge extension rectangles; performing an overlap determination on the disassembled edge extension rectangles and the via extension rectangles respectively according to the historical routing rectangle regions to obtain the check result; wherein, the historical routing rectangle regions include the extended rectangle regions where the routing has been completed.

8. An analog integrated circuit wiring system, characterized in that, The system includes: a first module, configured to obtain a preset netlist to generate a minimum spanning tree according to the preset netlist; wherein, the minimum spanning tree includes a plurality of preset pin regions; a second module, configured to determine the pin priority data corresponding to the preset pin regions according to a preset sorting mechanism; wherein, the preset sorting mechanism is determined by a Manhattan distance algorithm; a third module, configured to perform a routing planning according to the pin priority data and the minimum spanning tree through a pattern routing algorithm to obtain preset routing data; a fourth module, configured to perform a design rule check on the preset routing data to obtain a check result; a fifth module, configured to generate a target routing file according to the preset routing data when it is determined that the check result is passed.

9. An electronic device, characterized in that, including: at least one processor; at least one memory, configured to store at least one program; when the at least one program is executed by the at least one processor, the at least one processor implements the method according to any one of claims 1-7.

10. A computer-readable storage medium storing a computer program, characterized in that, The computer program, when executed by a processor, implements the method according to any one of claims 1 to 7.

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