Multi-port on-chip interconnection reliability analysis method

Abstract

The invention belongs to the technical field of integrated circuits, and particularly relates to a multi-port on-chip interconnection reliability analysis method. According to the method, a key path of on-chip interconnection is evaluated by establishing a multi-port on-chip interconnection physical model; the delay change of a gate on a critical path under the action of an NBTI effect is estimated by calculating the port utilization rate according to the working load condition, and the service life of the multi-port on-chip interconnection is predicted, namely, the time of failure caused by the fact that the delay exceeds an allowable range after long-term working of the multi-port on-chip interconnection is estimated. When the influence of a reverse bias temperature instability (NBTI) effect on the service life of the circuit is evaluated, a physical implementation method of a regular layout multi-port on-chip interconnection data path is considered, and the port utilization rate is calculated according to a port access conflict probability model. According to the method, accurate critical path estimation is obtained through a physical model, and efficient analysis of the reliability of the multi-port on-chip interconnection is realized in combination with an efficient port utilization rate calculation method.

Description

Technical Field

[0001] The present invention belongs to the technical field of integrated circuits, and particularly relates to a method for analyzing the reliability of multi-port on-chip interconnection. Background Art

[0002] With the rapid development of information technology, multi-core systems have been widely used in fields such as high-performance computing, artificial intelligence, and embedded systems. Compared with single-core processors, multi-core systems have significantly improved computing power and parallel processing efficiency by integrating multiple processor cores on the same chip, and have reduced the energy consumption per unit of performance. Therefore, multi-core systems have now become the mainstream architecture of electronic devices and data centers, capable of efficiently meeting the requirements of complex computing and massive data processing.

[0003] Driven by the continuous progress of integrated circuit technology, the multi-port on-chip interconnection architecture has become a key communication method in multi-core systems. This architecture integrates multiple processor cores, memory units, and other IP modules on the same chip, and realizes efficient data transmission between modules through on-chip interconnection. Compared with traditional bus structures, multi-port on-chip interconnection has higher parallel processing capabilities and stronger scalability, and can better meet the increasingly complex data transmission requirements of multi-core systems. However, with the shrinking of semiconductor process nodes, the reliability problems of multi-port on-chip interconnection have become increasingly prominent, and have gradually become the key factors affecting system performance and lifespan.

[0004] The reliability of multi-port on-chip interconnection is mainly affected by manufacturing process defects, device aging, and the working environment. Over time, these factors may cause an increase in node and link delays in on-chip interconnection, a decrease in performance, and even failure. Under the ultra-deep submicron (UDSM) process node, the NBTI (Negative Bias Temperature Instability) effect has a particularly significant impact on the gate delay of PMOS transistors. This effect will gradually increase the threshold voltage of the transistor, resulting in the continuous accumulation of gate delay, and thus affecting the lifespan and reliability of multi-port on-chip interconnection.

[0005] Currently, the focus of multi-port on-chip interconnection design mainly concentrates on performance and power consumption optimization, and the consideration of reliability is relatively limited. In the research on the reliability of multi-port on-chip interconnection, the difficulty lies in how to accurately estimate the critical path delay and obtain the switching activity information of the circuit. The critical path estimation depends on an accurate physical model, and requires detailed consideration of the physical implementation details of multi-port on-chip interconnection to ensure the predictability of layout and wiring. At the same time, the lifespan estimation of on-chip interconnection requires accurate switching activity information, usually obtained through performance simulation. However, in the face of a large number of evaluations for various applications, the simulation process is time-consuming and the computational cost is high. Therefore, evaluating the lifespan of multi-port on-chip interconnection through modeling in the early stage of design has become a key link in the reliability design of on-chip interconnection. Summary of the Invention

[0006] Aiming at the deficiencies of the prior art, the purpose of the present invention is to propose a multi-port on-chip interconnection reliability analysis method to support the rapid and accurate estimation of the lifespan of multi-port on-chip interconnections.

[0007] The multi-port on-chip interconnection reliability analysis method proposed by the present invention evaluates the critical path of the on-chip interconnection by establishing a physical model of the multi-port on-chip interconnection; calculates the port utilization rate according to the workload situation, estimates the delay change of the gates on the critical path under the effect of the NBTI effect, and predicts the lifespan of the multi-port on-chip interconnection, that is, estimates the time when the delay exceeds the allowable range after long-term operation and causes failure; when evaluating the impact of the reverse bias temperature instability (NBTI) effect on the circuit lifespan, the physical implementation of the regular layout multi-port on-chip interconnection data path and the port utilization rate are calculated according to the port access conflict probability model. The specific steps are as follows:

[0008] Step 1: Set the architecture parameters, micro-architecture parameters, physical implementation parameters, and process parameters of the multi-port on-chip interconnection; the architecture parameters include the number of master ports, the number of slave ports, and the data bit width; the micro-architecture parameters include the buffer depth and the multiplexer implementation form; the physical implementation parameters include the data path slice form and the slice stack number; the process parameters include the standard cell unit row height, the multiplexer size, and the register size;

[0009] Step 2: Based on the physical implementation method of the regular layout data path, establish a physical model of the multi-port on-chip interconnection;

[0010] Step 3: Estimate the critical path and the wire delay and gate delay on the path according to the physical model of the multi-port on-chip interconnection; calibrate the wire delay evaluation result by a machine learning method;

[0011] Step 4: Configure the memory access probability matrix according to the application program traffic pattern of the multi-port on-chip interconnection; calculate the port utilization rate according to the port access conflict probability model;

[0012] Step 5: Set the working environment and lifespan aging conditions. The working environment includes the working temperature and the port utilization rate, and the lifespan aging condition is the expected delay margin; update the gate delay on the critical path to the gate delay considering the NBTI effect;

[0013] Step 6: Evaluate the reliability (expected lifespan) of the overall circuit by combining the influence of the gate delay aging offset on the critical path delay.

[0014] In Step 2, the modeling method of the physical model of the multi-port on-chip interconnection is as follows:

[0015] Step 201: For simplicity of calculation, assume that the routing algorithm uses all metal layers as evenly as possible. This calculation can represent multiple physical metal layers with different line widths and line spacings as a single abstract metal layer. The line widths and line spacings of different metal layers are simplified to the average unit line width and average unit line spacing of all metal layers. The average unit line delay can be obtained through simulation (considering the automatic insertion of repeaters, the line delay is linearly related to the line length).

[0016] Step 202: The multiplexers in the multi-port on-chip interconnection data path are constructed using 2:1 sub-multiplexers, and the sub-multiplexers are stacked vertically.

[0017] Step 203: The multiplexers of the same output bit of all output ports are stacked horizontally to form a bit slice.

[0018] Step 204: The bit slices form a bit slice matrix according to the bit slice stacking parameters during physical implementation.

[0019] Step 205: The input register and output register are placed on both sides of the bit slice matrix and stacked according to the stacking method of the bit slice matrix.

[0020] Step 206: The control path includes an arbiter, an address decoder, and an address encoder, and is placed above the data path. Since the critical path is independent of the control path, the detailed control path modeling is omitted.

[0021] Step 207: The control signals output by the control path are input from above the data path, and a two-stage inverter is used to drive the control signal wires spanning the entire height of the data path.

[0022] In step 3, the method for estimating the critical path and the line delay and gate delay on the path according to the physical model of the multi-port on-chip interconnection, and the method for calibrating the line delay through machine learning are as follows:

[0023] Step 301: Compared with the delay of the multi-port on-chip interconnection data path, the delay of the control path of the multi-port on-chip interconnection can be ignored because usually the result of a single arbitration can support several data transmissions. On the other hand, at high bandwidth requirements, the data path accounts for the vast majority of the area in the high-radix and large data bit-width multi-port on-chip interconnection, resulting in a larger data path delay. Therefore, the present invention mainly considers the delay of the multi-port on-chip interconnection data path.

[0024] Step 302: According to the established physical model of the multi-port on-chip interconnection, the total bus length on the critical path is that the critical path of the data path is the sum of the control signal lines spanning the height of the bit slice matrix, the internal signal lines of the multiplexer tree, and the data signal output lines spanning the width of the bit slice matrix.

[0025] Step 303: The gate delay on the critical path is the sum of the gate delays of the control signal input register, the two-stage inverter, and the multiplexer tree.

[0026] Step 304: Calculate the wire delay of the critical path according to the average unit wire delay and the bus length of the critical path.

[0027] Step 305: Configure the regular layout physical implementation of a series of on-chip interconnection data paths with different scales, and fit the actual simulation results of the wire delay on the critical path through the linear regression algorithm.

[0028] In step 4, the access probability matrix is configured according to the application traffic pattern of the multi-port on-chip interconnection. This access probability matrix can be constructed manually or obtained by the application through simulation for a period of time, and it represents the traffic distribution of the multi-port on-chip interconnection within a period of time.

[0029] In step 4, the port utilization rate is calculated according to the port access conflict probability model. Its calculation method considers the arbitration mechanism of fairness, and the utilization rate of each port is the output traffic after the access traffic conflict at that port.

[0030] In step 5, the gate delay on the critical path is updated to the gate delay considering the NBTI effect. Specifically, it is an estimation of the critical path based on the physical model. By setting the working environment and lifetime aging conditions, the gate delay on the critical path is updated considering the NBTI effect.

[0031] In step 6, the overall circuit reliability is evaluated. Specifically, the impact of the NBTI effect on the critical path delay is estimated by calculating the ratio of the gate delay to the overall critical path delay, so as to estimate the reliability (expected lifetime) of the overall multi-port on-chip interconnection circuit.

[0032] The present invention has the following advantages:

[0033] (1) The multi-port on-chip interconnection physical model proposed by the present invention, based on the physical implementation method of the regular layout data path, effectively reduces the physical implementation complexity of the multi-port on-chip interconnection and ensures the optimized physical implementation result. By using the machine learning method to fit the modeling result of the physical model to the actual simulation result, the generalization of the model is improved, and both the estimated average error and the maximum error are less than 5%, verifying the accuracy of the model.

[0034] (2) The multi-port on-chip interconnection reliability analysis method proposed by the present invention accurately estimates the critical path according to the physical model, and can quickly obtain the switching activity information through the analysis model of access conflict calculation, and can quickly and efficiently evaluate the reliability of the multi-port on-chip interconnection.

[0035] (3) The multi-port on-chip interconnection reliability analysis method proposed by the present invention has parametric designs for both the physical model and the analysis model, which can support the evaluation of multi-port on-chip interconnection architectures of different scales and various application program workloads, and has wide applicability. Description of the Drawings

[0036] Figure 1 is a flowchart of the multi-port on-chip interconnection reliability analysis method of the present invention.

[0037] Figure 2 is a flowchart of the physical modeling described in the present invention.

[0038] Figure 3 and Figure 4 is a schematic diagram of the physical modeling described in the present invention. Detailed Embodiments

[0039] The present invention will be further introduced below through specific examples in combination with the drawings.

[0040] The main challenges in performing the reliability analysis of multi-port on-chip interconnections include evaluating the critical paths of multi-port on-chip interconnections and obtaining the switching activity information on the critical paths. The estimation of critical paths depends on accurate physical models. The present invention ensures the predictability of layout and wiring by carefully considering the physical implementation details of multi-port on-chip interconnections. In particular, for the data paths with regular circuit structures in multi-port on-chip interconnections, the physical model considers the physical implementation methods of regular layout data paths, ensuring optimized physical implementation results. To obtain the switching activity information on the critical paths, the present invention proposes an analysis model for calculating the switching activity information. Various workload traffic patterns are abstracted into a memory access probability matrix, and the port utilization rate of the multi-port on-chip interconnection is calculated based on the port access conflict probability. The switching activity information on the critical path can be represented by the output port utilization rate of this critical path. Both the physical model and the analysis model are parametric designs, which can support the evaluation of multi-port on-chip interconnection architectures of different scales and various application program workloads, and have wide applicability.

[0041] The flowchart of the multi-port on-chip interconnection reliability analysis method is as Figure 1 shown. It includes the following steps:

[0042] Step 1: Set the architecture parameters, micro-architecture parameters, physical implementation parameters, and process parameters of the multi-port on-chip interconnection;

[0043] Step 2: Establish a physical model of the multi-port on-chip interconnection based on the physical implementation method of the regular layout data path;

[0044] Step 3: Estimate the critical paths and the wire delay and gate delay on the paths according to the physical model of the multi-port on-chip interconnection; calibrate the wire delay evaluation results through machine learning methods;

[0045] Step 4: Configure the memory access probability matrix according to the application traffic pattern of the multi-port on-chip interconnection; calculate the port utilization rate according to the port access conflict probability model;

[0046] Step 5: Set the working environment and lifetime aging conditions. The working environment includes the working temperature and the port utilization rate, and the lifetime aging conditions include the expected lifetime and the expected delay margin; update the gate delay on the critical path to the gate delay considering the NBTI effect;

[0047] Step 6: Evaluate the reliability of the overall circuit by combining the impact of the gate delay aging offset on the critical path delay.

[0048] In Step 1, the setting of the multi-port on-chip interconnection parameters is as follows:

[0049] Set the architecture parameters of the multi-port on-chip interconnection: the number of master ports M, the number of slave ports N, and the data bit width DW, the micro-architecture parameters: the buffer depth depth and the size of the sub-multiplexer implementation form sub-mux, the physical implementation parameters: the data path slicing form (bit slicing or port slicing), the number of slice stacks W, the process parameters: the row height hi of the standard cell, the width w of the sub-multiplexer mx2 and the register width w reg .

[0050] Here, in order to elaborate on the multi-port on-chip interconnection reliability analysis method, the architecture parameters are configured as: M = 32, N = 32, DW = 32, depth = 1, sub-mux = 2, the data path slicing form is bit slicing, and the number of slice stacks W = 1; the process adopted in the implemented example is the SMIC 12nm process, and the process parameters are from the relevant process documents provided by the foundry: h i = 0.384um, w mx2 = 0.864um, w reg = 1.728um.

[0051] In Step 2, the modeling method of the physical model of the multi-port on-chip interconnection has the following process Figure 2 , as follows:

[0052] Step 201: For simplicity of calculation, assume that the routing algorithm uses all metal layers as evenly as possible. This assumption can represent multiple physical metal layers with different line widths and line spacings as a single abstract metal layer, and the line widths and line spacings of different metal layers are simplified to the average unit line width and average unit line spacing of all metal layers. The average unit wire delay can be obtained through simulation (considering the automatic insertion of repeaters, the wire delay is linearly related to the wire length).

[0053] Here, the SMIC 12nm process has 9 metal layers. Assuming the bottom - most metal layer is used for internal wiring of standard cells and the top - most two metal layers are used for global wires routing clock and power, there are 6 available metal layers, and the average unit wire delay d wire is obtained through linear regression by multiple simulations.

[0054] In this embodiment, the SMIC 12nm process library is used. Synopsys Design Compiler is used for RTL synthesis, Cadence Innovus is used for placement and routing, and Synopsys Primetime is used to report delay data.

[0055] Step 202: The multiplexers in the multi - port on - chip interconnection data path are constructed using 2:1 sub - multiplexers, and the sub - multiplexers are stacked vertically;

[0056] Step 203: The multiplexers of the same output bit of all output ports are stacked horizontally to form a bit - slice;

[0057] Step 204: The bit - slices form a bit - slice matrix according to the bit - slice stacking parameters during physical implementation;

[0058] The number of horizontally stacked bit - slices within the same row can be controlled by the bit - slice stacking parameter W, enabling the bit - slice matrix to have an adjustable aspect ratio.

[0059] Step 205: The input register and the output register are placed on both sides of the bit - slice matrix and are stacked according to the bit - slice matrix stacking method.

[0060] The input register and the output register of the data signal are respectively placed on both sides of the bit - slice matrix, and an adjustable aspect ratio is obtained through the bit - slice stacking parameter W.

[0061] Step 206: The control path includes an arbiter, an address decoder, and an address encoder, and is placed above the data path. Since the critical path is independent of the control path, detailed control path modeling is omitted.

[0062] Step 207: The control signals output from the control path are input from above the data path, and a two - stage inverter is used to drive the control signal wire spanning the entire height of the data path.

[0063] Figure 3 and Figure 4 are the schematic diagrams of the physical modeling.

[0064] In step 3, the methods for evaluating the critical path and the wire delay and gate delay on the path, and calibrating the wire delay through machine learning are as follows:

[0065] Step 301: Compared with the delay of the data path of the multi-port on-chip interconnection, the delay of the control path of the multi-port on-chip interconnection can be ignored because usually the result of a single arbitration can support several data transmissions. On the other hand, at high bandwidth requirements, the data path in the high-radix and large data-bitwidth multi-port on-chip interconnection occupies the vast majority of the area, resulting in a larger data path delay. Therefore, the present invention mainly considers the delay of the data path of the multi-port on-chip interconnection;

[0066] Step 302: According to the established physical model of the multi-port on-chip interconnection, the total wire length of the bus on the critical path totalwirelength is that the critical path of the data path is the wire length h of the control signal line spanning the height of the bit-slice matrix datapath , the wire length h of the internal signal line of the multiplexer tree mx and the wire length w of the data signal output line spanning the width of the bit-slice matrix datapath The sum is specifically calculated as:

[0067] h datapath =(M - 1)*DW*h i , (1)

[0068] h mx =(M - 2)*h i , (2)

[0069] w datapat h = N*w mx2 , (3)

[0070] totalwirelength = h datapath +h mx +w datapath , (4)

[0071] Among them, M is the number of master ports, N is the number of slave ports, DW is the data bit width, hi is the row height of the standard cell, and w mx2 is the width of the 2-to-1 multiplexer.

[0072] Step 303: The gate delay delay gate on the critical path is the input register delay delay reg , the two-stage inverter delay delay inv ×2 and the multiplexer tree delay delay mux The sum is specifically calculated as:

[0073] delay mux =(M - 1)*delay mx2 , (5)

[0074] delay gate =delay mux+delay reg +delay inv ×2, (6)

[0075] Here, delay reg 、delay inv and delay mx2 are from the process library related files;

[0076] Step 304: Calculate the wire delay delay wire of the critical path according to the average unit wire delay d wire and the total wire length totalwirelength of the critical path; Fit the results of multiple actual simulations through a linear regression algorithm.

[0077] delay wire = d wire *totalwirelength, (7)

[0078] The wire delay estimated by the model is fitted to the results of multiple actual simulations through a linear regression algorithm. After fitting, both the test average error and the maximum error are less than 5%, verifying the accuracy of the physical model.

[0079] In step 4, the application traffic pattern of the multi-port on-chip interconnection is represented by the memory access probability matrix A access which can be constructed manually or obtained by the application through simulation for a period of time, representing the traffic distribution of the multi-port on-chip interconnection over a period of time.

[0080] For example, a typical traffic pattern is a random uniform traffic pattern. The number of master ports is M and the number of slave ports is N. Then A access has M rows and N columns. The number pij in the i-th row and j-th column represents the probability that master port i accesses slave port j. Assuming that the injection rate of each input port is 1, then the sum of the access probabilities of each row in A access is 1, and the access probability of each master port to each slave port is 1 / N.

[0081] The calculation method of the utilization rate of the multi-port on-chip interconnection ports considers a fairness arbitration mechanism, and the utilization rate of each port is the output traffic after access traffic conflict at that port.

[0082] Using the method proposed by Andreas Tretter et al. in their paper "Interleaved multi-bank scratchpad memories: A probabilistic description of access conflicts" published in the 2015 52nd ACM / EDAC / IEEE Design Automation Conference (DAC), the calculation formula for the output traffic from port a considering traffic conflicts is:

[0083]

[0084] where p mi_a is the probability that the master port mi accesses the slave port a.

[0085] The lifetime estimation method for the multi-port on-chip interconnection considers the critical path estimation based on a physical model. By setting the working environment and lifetime aging conditions, the gate delay model is updated considering the NBTI effect, and the ratio of the gate delay to the overall critical path delay is calculated to estimate the impact of the NBTI effect on the critical path delay, thereby estimating the lifetime of the multi-port on-chip interconnection.

[0086] Among them, a prediction model based on NBTI aging is used, and this model is based on the related work of Henkel et al. in their paper "Thermal management for dependable on-chip systems" published in the 2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC). This model gives the long-term NBTI-induced ΔV t as a function of the supply voltage (V dd ), temperature (T), time (t), and duty cycle (equivalent to the utilization rate u of the port).

[0087]

[0088] t Then, the increase in delay can be approximated as a first-order relative increase in V

[0089] Therefore, the corresponding correction of the gate delay delay-gate-modify considering the NBTI effect is:

[0090]

[0091] Then, calculate the ratio of the gate delay to the overall critical path delay to estimate the impact of the NBTI effect on the critical path delay, and thus estimate the lifetime of the multi-port on-chip interconnect.

[0092] Here, the sum of the gate delays on the critical path needs to be updated to the gate delay delay after considering the NBTI effect. gate-modify , when the NBTI effect is not considered, the total delay on the critical path:

[0093] delay criticalpath = delay gate + delay wire , (11)

[0094] Assume that the expected delay margin is 10% of the total delay. Then, the expected lifetime t of the multi-port on-chip interconnect satisfies the following condition:

[0095] delay criticalpath ×1.1 > delay gate-modify + delay wire , (12)

[0096] In this embodiment, the configuration of the on-chip interconnect is M = 32 = N, DW = 32, the process library is a 12nm process library, the operating voltage V dd is about 0.8V, the threshold voltage V t is about 0.3V, the operating temperature T is about 300K, and the workload is a random uniform traffic pattern with an injection rate of 1. According to the reliability analysis method proposed by the present invention, the expected lifetime of this on-chip interconnect is about 2.7 years.

Claims

1. A method for analyzing the reliability of multi-port on-chip interconnection, characterized in that Evaluate the critical path of on-chip interconnection by establishing a physical model of multi-port on-chip interconnection; calculate the port utilization based on the workload to estimate the delay change of the gates on the critical path under the effect of NBTI, and predict the lifetime of the multi-port on-chip interconnection, that is, estimate the time when the delay exceeds the allowable range after long-term operation and causes failure; when evaluating the impact of reverse bias temperature instability (NBTI) effect on the circuit lifetime, consider the physical implementation of the regular layout multi-port on-chip interconnection data path and calculate the port utilization according to the port access conflict probability model. The specific steps are as follows: Step 1: Set the architecture parameters, micro-architecture parameters, physical implementation parameters, and process parameters of the multi-port on-chip interconnection; the architecture parameters include the number of master ports, the number of slave ports, and the data bit width; the micro-architecture parameters include the buffer depth and the multiplexer implementation form; the physical implementation parameters include the data path slicing form and the number of slice stacks; the process parameters include the row height of the standard cell, the size of the multiplexer, and the size of the register. Step 2: Based on the physical implementation method of the regular layout data path, establish a physical model of the multi-port on-chip interconnection. Step 3: Estimate the critical path and the wire delay and gate delay on the path according to the physical model of the multi-port on-chip interconnection; calibrate the wire delay evaluation result by machine learning method. Step 4: Configure the memory access probability matrix according to the application traffic pattern of the multi-port on-chip interconnection; calculate the port utilization according to the port access conflict probability model. Step 5: Set the working environment and lifetime aging conditions. The working environment includes the working temperature and the port utilization, and the lifetime aging condition is the expected delay margin; update the gate delay on the critical path to the gate delay considering the NBTI effect. Step 6: Evaluate the reliability of the overall circuit by combining the impact of the gate delay aging offset on the critical path delay.

2. The multi-port on-chip interconnection reliability analysis method according to claim 1, wherein The specific steps for establishing the physical model of the multi-port on-chip interconnection described in Step 2 are as follows: Step 201: Assume that the routing algorithm uses all metal layers as evenly as possible. This calculation can represent multiple physical metal layers with different line widths and line spacings as a single abstract metal layer. The line width and line spacing of different metal layers are simplified to the average unit line width and average unit line spacing of all metal layers, and the average unit wire delay is obtained through simulation. Step 202: The multiplexers in the multi-port on-chip interconnection data path are constructed using 2:1 sub-multiplexers, and the sub-multiplexers are stacked vertically. Step 203: The multiplexers of the same output bit of all output ports are stacked horizontally to form a bit slice. Step 204: The bit slices form a bit slice matrix according to the bit slice stacking parameters during physical implementation. Step 205: The input register and output register are placed on both sides of the bit slice matrix and stacked according to the bit slice matrix stacking method. Step 206: The control path includes an arbiter, an address decoder, and an address encoder, and is placed above the data path. Step 207: The control signals output by the control path are input from above the data path, and a two-stage inverter is used to drive the control signal wire spanning the entire height of the data path.

3. The multi-port on-chip interconnection reliability analysis method according to claim 2, wherein In step 3, estimating the critical path and the wire delay, gate delay on the path, and calibrating the wire delay through machine learning according to the physical model of the multi-port on-chip interconnect are specifically as follows: Step 301: Compared with the delay of the data path of the multi-port on-chip interconnect, the delay of the control path of the multi-port on-chip interconnect is ignored, and mainly the delay of the data path of the multi-port on-chip interconnect is considered; Step 302: According to the established physical model of the multi-port on-chip interconnect, the total length of the bus on the critical path is the sum of the control signal lines, internal signal lines of the multiplexer tree, and data signal output lines that cross the height of the bit-slice matrix for the critical path of the data path; Step 303: The gate delay on the critical path is the sum of the gate delays of the control signal input register, the second-stage inverter, and the multiplexer tree; Step 304: Calculate the wire delay of the critical path according to the average unit wire delay and the total length of the bus on the critical path; Step 305: Configure the regular layout physical implementations of the on-chip interconnect data paths with a series of different scales, and fit the actual simulation results of the wire delay on the critical path through the linear regression algorithm.

4. The multi-port on-chip interconnection reliability analysis method according to claim 3, characterized in that In step 4, configuring the memory access probability matrix according to the application traffic pattern of the multi-port on-chip interconnect, which is constructed manually or obtained by the application through simulation for a period of time, and represents the traffic distribution of the multi-port on-chip interconnect within a period of time; Calculating the port utilization rate according to the port access conflict probability model, and its calculation method considers the arbitration mechanism of fairness, and the utilization rate of each port is the output traffic after the access traffic conflict at that port.

5. The multi-port on-chip interconnection reliability analysis method according to claim 4, characterized in that In step 5, updating the gate delay on the critical path to the gate delay considering the NBTI effect, specifically based on the critical path estimation of the physical model, and considering the NBTI effect to update the gate delay on the critical path by setting the working environment and lifetime aging conditions.

6. The multi-port on-chip interconnection reliability analysis method according to claim 5, characterized in that In step 6, evaluating the reliability of the overall circuit, specifically estimating the impact of the NBTI effect on the critical path delay by calculating the ratio of the gate delay to the overall critical path delay, so as to estimate the reliability of the overall circuit of the multi-port on-chip interconnect.

7. The multi-port on-chip interconnect reliability analysis method according to claim 6, characterized in that: In step 302, the total wire length on the critical path is the critical path of the data path, and the control signal line length h spanning the height of the bit slice matrix is datapath 、The length of the signal line inside the multiplexer tree h mx and the data signal output line length w across the width of the bit slice matrix datapath The specific formula is: h datapath =(M - 1)*DW*h i , (1) h mx =(M - 2)*h i , (2) w datapath = N * w mx2 , (3) totalwirelength = h datapath + h mx + w datapath , (4) Where M is the number of master ports, N is the number of slave ports, DW is the data bit width, hi is the row height of the standard cell, and w mx2 is the width of the 2-to-1 multiplexer; In step 303, the gate delay delay on the critical path gate is the input register delay delay reg , the two-stage inverter delay delay inv ×2, and the multiplexer tree delay delay mux The sum is specifically calculated as follows: delay mux =(M - 1) * delay mx2 , (5) delay gate = delay mux + delay reg + delay inv ×2, (6) Here, delay reg , delay inv and delay mx2 are from the process library related files; In step 304: according to the average unit wire delay d wire and the total wire length of the critical path, calculate the wire delay delay of the critical path wire ; Fit the results of multiple actual simulations through the linear regression algorithm: delay wire = d wire * total wire length, (7) The wire delay estimated by the model is fitted to the results of multiple actual simulations through the linear regression algorithm, and both the test average error and the maximum error after fitting are less than 5%, verifying the accuracy of the physical model.

8. The multi-port on-chip interconnection reliability analysis method according to claim 7, characterized in that, The calculation method of the multi-port on-chip interconnect port utilization rate described in step 4 considers the arbitration mechanism of fairness, and the utilization rate of each port is the output traffic after the access traffic conflict at port a of that port, and the calculation formula is: Among them, p mi_a is the probability that the master port mi accesses the slave port a.

9. The multi-port on-chip interconnection reliability analysis method according to claim 8, wherein In step 6, the impact of NBTI effect on the critical path delay is estimated by calculating the ratio of the gate delay to the overall critical path delay, so as to estimate the reliability of the overall circuit of the multi-port on-chip interconnect; specifically, the long-term NBTI-induced ΔV is given t As the operating voltage (V dd ), temperature (T), time (t), and duty cycle, which is equivalent to the utilization rate u of the port, are expressed as a function of: Then, the increase in the delay is approximated as the relative increase in the first-order threshold voltage V t ; Therefore, the corresponding correction of the gate delay delay-gate-modify considering the NBTI effect is: Then, calculate the ratio of the gate delay to the overall critical path delay to estimate the impact of the NBTI effect on the critical path delay, so as to estimate the lifetime of the multi-port on-chip interconnect.

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