A signal demodulation circuit and digital isolator

Abstract

The present invention discloses a signal demodulation circuit and a digital isolator. The signal demodulation circuit includes an amplification module and a clock detection module; the amplification module receives a first modulation signal, is used to amplify the first modulation signal, and outputs a second modulation signal; the clock detection module is connected to the amplification module, and is used to output a valid level signal according to the transition edge of the clock signal when the second modulation signal has a clock signal, and output an invalid level signal when the second modulation signal does not have the clock signal, thereby forming a demodulation signal, wherein the frequency of the clock signal is the same as the frequency of the carrier signal of the second modulation signal. The structure of the signal demodulation circuit provided by the present invention is relatively simple.

Description

Technical Field

[0001] The present invention relates to the field of communication technology, and in particular to a signal demodulation circuit and a digital isolator. Background Art

[0002] Digital isolators are devices used to transmit digital signals between different electrical domains. They can isolate high voltages, suppress noise interference, and achieve reliable signal transmission.

[0003] On-off keying (OOK) is a common modulation method in digital isolators. It represents binary data by controlling the presence or absence of a carrier signal. The presence of a carrier signal represents a "1," while the absence of a carrier signal represents a "0." On the transmitting end, the binary data sequence controls a switch. When the data is a "1," the switch closes, allowing the carrier signal to pass; when the data is a "0," the switch opens, eliminating the carrier signal. On the receiving end, the presence of a carrier signal is detected to determine whether the received data is a "1" or a "0." Figure 1 This is a digital isolator circuit diagram in related technology, such as Figure 1 As shown, the low-voltage side is the transmitting end, the high-voltage side is the receiving end, and the capacitor serves as an isolation layer. The demodulation method of the existing receiving end signal demodulation circuit is generally to amplify the signal through an amplifier and then detect the logic level through an envelope detection module. The demodulation module has many stages and a relatively complex structure. Summary of the Invention

[0004] The present invention provides a signal demodulation circuit and a digital isolator to solve the problem of complex structure of the signal demodulation circuit in the prior art.

[0005] According to one aspect of the present invention, there is provided a signal demodulation circuit, comprising an amplification module and a clock detection module;

[0006] The amplifying module receives a first modulated signal, and is used to amplify the first modulated signal and output a second modulated signal;

[0007] The clock detection module is connected to the amplification module. The clock detection module is used to output a valid level signal according to the transition edge of the clock signal when the second modulation signal has a clock signal, and output an invalid level signal when the second modulation signal does not have the clock signal to form a demodulated signal, wherein the frequency of the clock signal is the same as the frequency of the carrier signal of the second modulation signal.

[0008] Optionally, the clock detection module includes a first delay unit, a second delay unit and a logic AND operation unit; the first end of the first delay unit and the first end of the second delay unit are connected to the output end of the amplification module, the second end of the first delay unit is connected to the first input end of the logic AND operation unit, and the second end of the second delay unit is connected to the second input end of the logic AND operation unit; the first delay unit is used to delay the falling edge of the second modulated signal for a first preset time length, the second delay unit is used to delay the rising edge of the second modulated signal for a second preset time length, and the logic AND operation unit is used to perform a logic AND operation on the signal output by the first delay unit and the signal output by the second delay unit, and output a demodulated signal; wherein, the first preset time length is equal to the second preset time length, and the first preset time length is greater than the period of the carrier signal in the second modulated signal and less than the period of the baseband signal.

[0009] Optionally, the second delay unit includes a first delay sub-unit and a first logic NOT operation sub-unit, the input end of the first logic NOT operation sub-unit is connected to the amplification module, the output end of the first logic NOT operation sub-unit is connected to the first end of the first delay sub-unit, the second end of the first delay sub-unit is connected to the second input end of the logic AND operation unit, the first logic NOT operation sub-unit is used to invert the second modulation signal, and the first delay sub-unit is used to delay the falling edge of the inverted second modulation signal by the second preset time length.

[0010] Optionally, the amplification module includes a comparator, the first modulation signal includes a single-channel modulation signal, the first input end of the comparator is used to access the first modulation signal, the second input end of the comparator is used to access the reference signal, the output end of the comparator is connected to the input end of the clock detection module, and the comparator is used to compare the first modulation signal and the reference signal and then output the second modulation signal; or, the first modulation signal includes a differential modulation signal, the first input end of the comparator is used to access the positive differential modulation signal, the second input end of the comparator is used to access the negative differential modulation signal, the output end of the comparator is connected to the input end of the clock detection module, and the comparator is used to compare the positive differential modulation signal and the negative differential modulation signal, and output the second modulation signal when the difference between the positive differential modulation signal and the negative differential signal meets a preset threshold.

[0011] Optionally, the signal demodulation circuit further includes a de-jitter module, which is connected to the output end of the clock detection module and is used to filter out interference signals in the demodulated signal output by the clock detection module.

[0012] Optionally, the de-jitter module includes a third delay unit, a fourth delay unit and a latch unit, the first end of the third delay unit is connected to the output end of the clock detection module, the second end of the third delay unit is connected to the first input end of the latch unit, the first end of the fourth delay unit is connected to the output end of the clock detection module, and the second end of the fourth delay unit is connected to the second input end of the latch unit; the third delay unit is used to delay the rising edge of the demodulated signal for a third preset time length, the fourth delay unit is used to delay the falling edge of the demodulated signal for a fourth preset time length, and the latch unit is used to latch and output according to the signal output by the third delay unit and the signal output by the fourth delay unit; wherein, the delay length of the third delay unit is equal to the delay length of the fourth delay unit, and the delay length of the third delay unit is greater than the length of the interference signal.

[0013] Optionally, the fourth delay unit includes a second delay sub-unit and a second logic NOT operation sub-unit, the input end of the second logic NOT operation sub-unit is connected to the output end of the clock detection module, the output end of the second logic NOT operation sub-unit is connected to the first end of the second delay sub-unit, and the second end of the second delay sub-unit is connected to the second input end of the latch unit.

[0014] According to another aspect of the present invention, a digital isolator is provided, comprising a signal modulation circuit, an isolation layer and the signal demodulation circuit, wherein the isolation layer is connected between the signal modulation circuit and the signal demodulation circuit, the signal modulation circuit is used to modulate the input baseband signal to form a modulated signal, the isolation layer is used to isolate and transmit the modulated signal to the signal demodulation circuit to form a first modulated signal, and the signal demodulation circuit is used to demodulate the first modulated signal and output a demodulated signal.

[0015] Optionally, the isolation layer includes a first capacitor and a second capacitor, the first end of the first capacitor is connected to the first input end of the amplifying module in the signal demodulation circuit, the second end of the first capacitor is connected to the first output end of the signal modulation circuit, the first end of the second capacitor is connected to the second input end of the amplifying module, and the second end of the second capacitor is connected to the second output end of the signal modulation circuit; or, the isolation layer includes a third capacitor, the first end of the third capacitor is connected to the first input end of the amplifying module in the signal demodulation circuit, the second end of the third capacitor is connected to the output end of the signal modulation circuit, and the second input end of the amplifying module is connected to the reference signal.

[0016] The technical solution of the embodiment of the present invention is to connect a clock detection module with an amplification module. The clock detection module outputs a valid level signal according to the transition edge of the clock signal when the second modulation signal has a clock signal, and outputs an invalid level signal when the second modulation signal has no clock signal, thereby forming a demodulated signal. The frequency of the clock signal is the same as the frequency of the carrier signal of the second modulation signal. Since the clock detection module outputs a valid level signal according to the transition edge of the clock signal and outputs an invalid level signal when there is no clock signal, the demodulation of the second modulation signal is achieved. The present invention directly demodulates the modulation signal through the clock detection module, reduces the number of stages of the demodulation module, and simplifies the structure of the signal demodulation circuit. This solves the problem of the relatively complex structure of the signal demodulation circuit in the prior art.

[0017] It should be understood that the content described in this section is not intended to identify the key or important features of the embodiments of the present invention, nor is it intended to limit the scope of the present invention. Other features of the present invention will become readily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0019] Figure 1 This is a circuit diagram of a digital isolator in the related art;

[0020] Figure 2 1 is a schematic structural diagram of a signal demodulation circuit provided by an embodiment of the present invention;

[0021] Figure 3 is a circuit diagram of a signal demodulation circuit provided by an embodiment of the present invention;

[0022] Figure 4 is a circuit diagram of another signal demodulation circuit provided by an embodiment of the present invention;

[0023] Figure 5 is a circuit diagram of another signal demodulation circuit provided by an embodiment of the present invention;

[0024] Figure 6 is a circuit diagram of another signal demodulation circuit provided by an embodiment of the present invention;

[0025] Figure 7 is a timing diagram of signal demodulation provided by an embodiment of the present invention;

[0026] Figure 8is a circuit diagram of a de-jitter module provided in an embodiment of the present invention;

[0027] Figure 9 is a timing diagram of a demodulated signal under common mode interference provided by an embodiment of the present invention;

[0028] Figure 10 is a de-jitter timing diagram of the de-jitter module provided in an embodiment of the present invention;

[0029] Figure 11 1 is a structural diagram of a digital isolator provided by an embodiment of the present invention;

[0030] Figure 12 is a circuit diagram of a digital isolator provided by an embodiment of the present invention;

[0031] Figure 13 is a circuit diagram of another digital isolator provided by an embodiment of the present invention;

[0032] Figure 14 This is a timing diagram of differential modulation signal transmission provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0033] In order to enable those skilled in the art to better understand the solutions of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the embodiments described are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts should fall within the scope of protection of the present invention.

[0034] It should be noted that the terms "first", "second", etc. in the description and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that the numbers used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0035] An embodiment of the present invention provides a signal demodulation circuit. Figure 2 FIG. 1 is a schematic diagram of a signal demodulation circuit provided by an embodiment of the present invention. Figure 2As shown, the signal demodulation circuit 100 includes an amplifying module 110 and a clock detection module 120; the amplifying module 110 is connected to the first modulation signal CLK, and the amplifying module 110 is used to amplify the first modulation signal and output the second modulation signal VCOMP; the clock detection module 120 is connected to the amplifying module 110, and the clock detection module 120 is used to output a valid level signal according to the transition edge of the clock signal when the second modulation signal has a clock signal, and output an invalid level signal when the second modulation signal has no clock signal, so as to form a demodulated signal, wherein the frequency of the clock signal is the same as the frequency of the carrier signal of the second modulation signal.

[0036] In this embodiment of the present invention, the signal demodulation circuit 100 is a circuit that restores the modulated signal to the original baseband signal and is provided at the receiving end of a digital isolator. The amplification module 110 amplifies the modulated signal output by the isolation layer of the digital isolator. The clock detection module 120 is a functional module that detects and analyzes clock signals. For example, the clock detection module 120 can detect the clock signal in the second modulated signal.

[0037] In an embodiment of the present invention, the amplification module 110 amplifies the input first modulated signal and outputs a second modulated signal. The clock detection module 120 outputs a valid level signal based on the transition edge of the clock signal when the second modulated signal has a clock signal, and outputs an invalid level signal when the second modulated signal does not have a clock signal. For example, when the second modulated signal has a clock signal, the clock detection module 120 outputs a high level signal based on the rising edge of the clock signal. When the second modulated signal does not have a clock signal, the clock detection module 120 outputs a low level signal, thereby forming a demodulated signal and demodulating the second modulated signal. The demodulated signal is output through the output terminal OUT of the signal demodulation circuit.

[0038] The technical solution of this embodiment is to connect a clock detection module with an amplification module. The clock detection module outputs a valid level signal according to the transition edge of the clock signal when the second modulation signal has a clock signal, and outputs an invalid level signal when the second modulation signal has no clock signal, thereby forming a demodulated signal. The frequency of the clock signal is the same as the frequency of the carrier signal of the second modulation signal. Since the clock detection module outputs a valid level signal according to the transition edge of the clock signal and outputs an invalid level signal when there is no clock signal, the demodulation of the second modulation signal is achieved. This embodiment directly demodulates the modulation signal through the clock detection module, reduces the number of stages of the demodulation module, and simplifies the structure of the signal demodulation circuit. This solves the problem of the relatively complex structure of the signal demodulation circuit in the prior art.

[0039] Figure 3 is a circuit diagram of a signal demodulation circuit provided by an embodiment of the present invention, such as Figure 3As shown, the clock detection module 120 includes a first delay unit 121, a second delay unit 122, and a logic AND operation unit 123. The first end of the first delay unit 121 is connected to the amplification module 110, the second end of the first delay unit 121 is connected to the first input end of the logic AND operation unit 123, the first end of the second delay unit 122 is connected to the amplification module 110, and the second end of the second delay unit 122 is connected to the second input end of the logic AND operation unit 123; the first delay unit 121 is used to delay the falling edge of the second modulated signal for a first preset time length, the second delay unit 122 is used to delay the rising edge of the second modulated signal for a second preset time length, and the logic AND operation unit 123 is used to perform a logic AND operation on the signal output by the first delay unit 121 and the signal output by the second delay unit 122, and output a demodulated signal. The first preset time length is equal to the second preset time length, and the first preset time length is greater than the period of the carrier signal in the second modulated signal and less than the period of the baseband signal.

[0040] In this embodiment of the present invention, the first delay unit 121 and the second delay unit 122 are units that delay the input signal for a certain period of time. The first delay unit 121 delays the falling edge of the second modulated signal, and the second delay unit 122 delays the rising and falling edges of the second modulated signal. The logic AND operation unit 123 operates on the input logic signal according to the "AND logic" rule and outputs the corresponding result. The logic AND operation unit 123 may include a logic AND gate circuit.

[0041] In an embodiment of the present invention, the first delay unit 121 delays the falling edge of the carrier signal in the second modulated signal by a first preset duration, and the second delay unit 122 delays the rising edge of the carrier signal in the second modulated signal by a second preset duration. For example, when the second modulated signal does not contain a clock signal, the digital signals output by the first delay unit 121 and the second delay unit 122 are opposite, and the logic AND operation unit 123 performs a logic AND operation on the signal output by the first delay unit 121 and the signal output by the second delay unit 122, and outputs a logic "0". When the second modulated signal contains a clock signal, because the first preset duration is equal to the second preset duration, and the first preset duration is greater than the period of the carrier signal in the second modulated signal and less than the period of the baseband signal, the first delay unit 121 outputs a high-level signal, and the second delay unit 122 outputs a high-level signal. The logic AND operation unit 123 performs a logic AND operation on the signal output by the first delay unit 121 and the signal output by the second delay unit 122, and outputs a logic "1". That is, when there is a clock signal in the second modulated signal, the signal demodulation circuit outputs a high-level signal; when there is no clock signal in the second modulated signal, the signal demodulation circuit outputs a low-level signal, thereby achieving demodulation of the second modulated signal.

[0042] Figure 4 is a circuit diagram of another signal demodulation circuit provided by an embodiment of the present invention, such as Figure 4 As shown, the second delay unit 122 includes a first delay sub-unit 1221 and a first logic NOT operation sub-unit 1222, the input end of the first logic NOT operation sub-unit 1222 is connected to the amplification module 110, the output end of the first logic NOT operation sub-unit 1222 is connected to the first end of the first delay sub-unit 1221, and the second end of the first delay sub-unit 1221 is connected to the second input end of the logic AND operation unit 123.

[0043] In an embodiment of the present invention, the first delay subunit 1221 is a unit that delays the falling edge of the input signal, and the first logical negation subunit 1222 is a logic unit that implements a logical negation operation and is used to invert the input signal. For example, the first logical negation subunit 1222 includes a logical negation gate circuit. Based on the above embodiment, the first logical negation subunit 1222 performs a logical negation operation on the input second modulation signal VCOMP and outputs a signal that is the inversion of the second modulation signal. The first delay subunit 1221 delays the falling edge of the signal output by the first logical negation subunit 1222 for a second preset duration. When the second modulation signal has a clock signal, the first logical negation subunit 1222 inverts the second modulation signal, and the signal output by the first delay subunit maintains a logic "1," i.e., the second delay unit outputs a logic "1." When the second modulated signal lacks a clock signal, the first logical negation subunit 1222 inverts the second modulated signal. The signal output by the first delay subunit is the logical opposite of the signal output by the first delay unit. That is, the signal output by the second delay unit is the logical opposite of the signal output by the first delay unit. Based on the above embodiment, the logical AND operation unit 123 performs a logical AND operation on the signal output by the first delay unit 121 and the signal output by the second delay unit 122, and then outputs a demodulated signal.

[0044] Figure 5 is a circuit diagram of another signal demodulation circuit provided by an embodiment of the present invention, such as Figure 5 As shown, the amplification module 110 includes a comparator U1, the first modulation signal includes a single modulation signal, the first input end of the comparator U1 is connected to the first modulation signal CLK, the second input end of the comparator U1 is connected to the reference signal Vref, the output end of the comparator U1 is connected to the input end of the clock detection module, and the comparator U1 is used to compare the first modulation signal and the reference signal and then output the second modulation signal VCOMP.

[0045] In an embodiment of the present invention, comparator U1 is a circuit element that compares two input signals, is capable of determining the magnitude relationship between the two input voltages, and outputs a corresponding logic level representing the comparison result. For example, when the first modulated signal is a single-channel modulated signal, comparator U1 compares the first modulated signal with a reference signal. When the first modulated signal is greater than the reference signal, comparator U1 outputs a high-level signal; when the first modulated signal is less than the reference signal, comparator U1 outputs a low-level signal. Because the comparator can output a digital signal by comparing the magnitudes of two analog signals, the first modulated signal can reach its full swing after being amplified by the comparator.

[0046] Figure 6 is a circuit diagram of another signal demodulation circuit provided by an embodiment of the present invention, such as Figure 6 As shown, the first modulation signal includes a differential modulation signal, the first input end of the comparator U1 is connected to the positive differential modulation signal CLK+, the second input end of the comparator U1 is connected to the negative differential modulation signal CLK-, the output end of the comparator U1 is connected to the input end of the clock detection module, and the comparator U1 is used to compare the positive differential modulation signal and the negative differential modulation signal, and output the second modulation signal VCOMP when the difference between the positive differential modulation signal and the negative differential signal meets the preset threshold.

[0047] In an embodiment of the present invention, when the first modulated signal is a differential modulated signal, comparator U1 compares the positive differential modulated signal with the negative differential modulated signal. When the difference between the positive differential modulated signal and the negative differential modulated signal meets a first preset threshold, comparator U1 outputs a high-level signal. When the difference between the positive differential modulated signal and the negative differential modulated signal meets a second preset threshold, comparator U1 outputs a low-level signal. Because differential signals have strong anti-interference properties, using differential signal modulation can improve the circuit's anti-interference capabilities. Figure 7 This is a timing diagram of signal demodulation provided by an embodiment of the present invention, such as Figure 7 As shown, td1 is the first preset duration of the first delay unit and the second delay duration of the second delay unit, VCOMP is the second modulation signal, VCOMPb is the signal after inverting the second modulation signal, a1 is the signal output by the first delay unit, a2 is the signal output by the second delay unit, and OUT is the demodulated signal output by the output end.

[0048] Based on the above embodiment, the signal demodulation circuit further includes a de-jitter module. Figure 8 is a circuit diagram of a de-jitter module provided by an embodiment of the present invention, such as Figure 8 As shown, the de-jitter module 210 is connected to the output end of the clock detection module, and the de-jitter module 210 is used to filter out interference signals in the demodulated signal output by the clock detection module.

[0049] In embodiments of the present invention, during signal transmission, common-mode interference may be superimposed on the useful signal, resulting in signal distortion, reduced transmission quality, and other issues. De-jitter module 210 is a module that can suppress or filter out common-mode interference signals, thereby improving the accuracy of signal transmission. Based on the above embodiments, de-jitter module 210 is connected to the clock detection module to de-jitter the demodulated signal output by the clock detection module, thereby improving the accuracy of the demodulated signal.

[0050] Specifically, the de-jitter module 210 includes a third delay unit 211, a fourth delay unit 212, and a latch unit 213. The first end of the third delay unit 211 is connected to the clock detection module, the second end of the third delay unit 211 is connected to the first input end of the latch unit 213, the first end of the fourth delay unit 212 is connected to the clock detection module, and the second end of the fourth delay unit 212 is connected to the second input end of the latch unit 213. The third delay unit 211 is configured to delay the rising edge of the demodulated signal by a third preset duration, the fourth delay unit 212 is configured to delay the falling edge of the demodulated signal by a fourth preset duration, and the latch unit 213 is configured to latch and output a latch signal based on the signal output by the third delay unit 211 and the signal output by the fourth delay unit 212. The delay duration of the third delay unit 211 is equal to the delay duration of the fourth delay unit 212, and the delay duration of the third delay unit 211 is greater than the duration of the interference signal.

[0051] In the embodiment of the present invention, the third delay unit 211 and the fourth delay unit 212 are units that delay the input signal for a certain period of time. The third delay unit 211 is a unit that delays the rising edge of the demodulated signal, and the fourth delay unit 212 is a unit that delays the falling edge of the demodulated signal. The latch unit 213 latches and outputs a latch signal based on the signal output by the third delay unit 211 and the signal output by the fourth delay unit 212. For example, the latch unit 213 includes a latch, etc.

[0052] Based on the above embodiment, the third delay unit 211 delays the rising edge of the demodulated signal by a third preset time length, the fourth delay unit 212 delays the falling edge of the demodulated signal by a fourth preset time length, and the latch unit 213 latches and outputs the latch signal based on the signal output by the third delay unit 211 and the signal output by the fourth delay unit 212. Transient interference has the characteristics of fast speed and limited time, and the common-mode voltage suddenly changes within a certain period of time. For example, the third preset time length of the third delay unit 211 and the fourth preset time length of the fourth delay unit 212 are both td2. When the demodulated signal is input to the de-jitter module, the de-jitter module can de-jitter the rising and falling edges of the demodulated signal for a duration of td2. Since the interference signal duration is less than td2, the de-jitter module can shield the erroneous signal within the td2 time, that is, filter out the glitches in the high and low levels of the demodulated signal. By providing the de-jitter module 210 , interference signals in the demodulated signal are filtered out, and the output terminal OUT1 of the de-jitter module outputs the de-jittered demodulated signal, thereby improving the accuracy of the demodulated signal. Figure 9 This is a timing diagram of the demodulated signal under common mode interference provided by an embodiment of the present invention, such as Figure 9 As shown, at the rising edge and falling edge of the common-mode interference signal G, the modulated signal CLK_TX sent by the transmitting end of the digital isolator and the modulated signal CLK_RX received by the signal demodulation circuit will be erroneous, causing the demodulated signal outputted from the output end OUT of the signal demodulation circuit to be erroneous within the corresponding time period.

[0053] Continue to refer Figure 8 The fourth delay unit 212 includes a second delay sub-unit 2121 and a second logic NOT operation sub-unit 2122, the input end of the second logic NOT operation sub-unit 2122 is connected to the clock detection module, the output end of the second logic NOT operation sub-unit 2122 is connected to the first end of the second delay sub-unit 2121, and the second end of the second delay sub-unit 2121 is connected to the second input end of the latch unit 213.

[0054] In this embodiment of the present invention, the second delay sub-unit 2121 delays the rising edge of the input signal, and the second logical negation sub-unit 2122 performs a negation operation. Based on the above embodiment, the second logical negation sub-unit 2122 performs a negation operation on the input demodulated signal and outputs a signal that is the inverted version of the demodulated signal. The second delay sub-unit 2121 delays the rising edge of the signal output by the second logical negation sub-unit 2122 by a fourth preset duration.

[0055] In the embodiment of the present invention, the latch unit 213 can temporarily store input data or signals and maintain their state until a new control signal is received to change it. The latch unit is generally composed of two cross-coupled logic gates. For example, the latch unit is an SR latch composed of two NOR gates. Figure 10 This is a de-jitter timing diagram of the de-jitter module provided in an embodiment of the present invention, such as Figure 10 As shown, td2 represents the third preset duration of the third delay unit and the fourth preset duration of the fourth delay unit. A represents the signal output by the third delay unit, i.e., the R terminal of the SR latch; B represents the signal output by the fourth delay unit, i.e., the S terminal of the SR latch. C represents the signal output by the NOR gate connected to the third delay unit in the latch unit, i.e., the positive output terminal of the SR latch; D represents the signal output by the NOR gate connected to the fourth delay unit in the latch unit, i.e., the negative output terminal of the SR latch. When the demodulated signal includes an interference signal, the third delay unit delays the rising edge of the interference signal. Because td2 exceeds the common-mode interference duration, the common-mode interference signal is filtered out, and the third delay unit outputs a low-level signal. The fourth delay unit delays the falling edge of the interference signal, outputting a low-level signal on the rising edge of the interference signal and, after a delay of the fourth preset duration, outputting a high-level signal. Based on the operating characteristics of the SR latch, the logical values ​​of the positive and negative output terminals of the SR latch are obtained. The negative output terminal of the SR latch serves as the output terminal OUT1 of the de-jitter module to obtain the demodulated signal after de-jittering. Among them, the interference signal is not limited to common mode interference, and surge, electrostatic discharge, etc. are also applicable.

[0056] In an embodiment of the present invention, the amplification module 110 amplifies the input first modulated signal and outputs a second modulated signal. The first delay unit 121 delays the falling edge of the carrier signal in the second modulated signal by a first preset time length, and the second delay unit 122 delays the rising edge of the carrier signal in the second modulated signal by a second preset time length. For example, when the second modulated signal does not contain a clock signal, the digital signals output by the first delay unit 121 and the second delay unit 122 are opposite, and the logic AND operation unit 123 performs a logic AND operation on the signal output by the first delay unit 121 and the signal output by the second delay unit 122, and outputs a logic "0". When a clock signal appears in the second modulated signal, since the first preset duration is equal to the second preset duration, and the first preset duration is greater than the period of the carrier signal in the second modulated signal and less than the period of the baseband signal, the first delay unit 121 outputs a high-level signal, and the second delay unit 122 outputs a high-level signal. The logic AND operation unit 123 performs a logic AND operation on the signal output by the first delay unit 121 and the signal output by the second delay unit 122, and outputs a logic "1", thereby achieving demodulation of the second modulated signal. At the same time, a de-jitter module 210 is provided at the output end of the logic AND operation unit 123 to eliminate interference signals in the demodulated signal and enhance the system's anti-interference capability.

[0057] The embodiment of the present invention further provides a digital isolator, Figure 11 FIG. 1 is a structural diagram of a digital isolator provided by an embodiment of the present invention. Figure 11 As shown, the digital isolator 10 includes a signal modulation circuit 11, an isolation layer 12, and a signal demodulation circuit 100 according to any of the above embodiments. The isolation layer 12 is connected between the signal modulation circuit 11 and the signal demodulation circuit 100. The signal modulation circuit 11 is used to modulate the input baseband signal. The isolation layer 12 is used to isolate the modulated signal and transmit it to the signal demodulation circuit 100 to form a first modulated signal. The signal demodulation circuit 100 is used to demodulate the first modulated signal and output a demodulated signal.

[0058] In an embodiment of the present invention, a digital isolator 10 is a device for transmitting digital signals between different electrical domains. Different modules may be at different potentials, with high voltage differences or noise interference. The use of a digital isolator can effectively avoid the impact of these interference factors on signal transmission, ensuring the stability and security of the system. The signal modulation circuit 11 is a circuit that superimposes the original baseband signal on a high-frequency carrier signal according to certain rules. The signal modulation circuit 11 achieves information transmission by changing the amplitude, frequency and other characteristics of the carrier. For example, the signal modulation circuit includes an oscillator. The isolation layer 12 can achieve electrical isolation and block the electrical isolation between different circuit parts. The isolation layer generally uses technologies such as transformer isolation, capacitor isolation or optical coupling isolation. Taking capacitor isolation as an example, the characteristics of capacitors are used to achieve signal transmission. The transmitting end of the digital isolator converts the electrical signal into a charge change on the capacitor, which is coupled to the receiving end of the digital isolator through the capacitor. The receiving end then converts the charge change into an electrical signal. This method can effectively isolate DC signals and only allow AC signals to pass, thereby achieving electrical isolation.

[0059] For example, Figure 12 is a circuit diagram of a digital isolator provided by an embodiment of the present invention, such as Figure 12 As shown, the isolation layer 12 includes a first capacitor C1 and a second capacitor C2, combined with Figure 6 The first end of the first capacitor C1 is connected to the first input end of the comparator U1, the second end of the first capacitor C1 is connected to the signal modulation circuit 11, the first end of the second capacitor C2 is connected to the second input end of the comparator U1, and the second end of the second capacitor C2 is connected to the signal modulation circuit 11. Figure 13 is a circuit diagram of another digital isolator provided by an embodiment of the present invention, such as Figure 13 As shown, the isolation layer 12 includes a third capacitor C3, combined with Figure 5 The first end of the third capacitor C3 is connected to the first input terminal of the comparator U1, the second end of the third capacitor C3 is connected to the signal modulation circuit 11, and the second input terminal of the comparator U1 is connected to the reference signal Vref. The isolation layer can use a single capacitor to transmit the modulated signal, or a pair of differential capacitors to transmit the modulated signal. In addition, because the amplification module 110 uses a comparator, there is no strict limit on the capacitance of the isolation capacitor. The larger the capacitance of the isolation capacitor and the smaller the parasitic capacitance at the receiving end, the greater the signal amplitude at the receiving end, and the stronger the noise and interference resistance.

[0060] In the embodiment of the present invention, the first capacitor C1 and the second capacitor C2 are a pair of differential capacitors, and the modulation signal output by the signal modulation circuit 11 is a differential modulation signal. Figure 14This is a timing diagram for differential modulation signal transmission provided by an embodiment of the present invention. Based on the above embodiment, when the original baseband signal IN is high, the oscillator in the signal modulation circuit operates and outputs a pair of differential modulation signals, with the oscillator's clock period set to t_clk. The differential modulation signals output by the oscillator are represented by CLK+_TX and CLK-_TX, respectively, and their amplitudes are the same as the oscillator's power supply voltage. Due to voltage division caused by parasitic capacitance at the receiving end of the digital isolator, the amplitude of the received signal is reduced. The differential signals of the first modulation signal received by the comparator are represented by CLK+_RX and CLK-_RX, respectively. The first modulation signal is compared and amplified by the comparator to a full-swing square wave signal VCOMP, i.e., the second modulation signal. Referring to the above embodiment, under the condition td1 > t_clk, the second modulation signal passes through the first delay unit, the second delay unit, and the logical AND operation unit, and then outputs a demodulated signal. This embodiment uses differential capacitance to transmit the modulation signal, which has better noise and interference suppression capabilities. At the same time, the structures of the signal modulation circuit 11 and the signal demodulation circuit 100 are relatively simple. Applying the signal demodulation circuit and the signal modulation circuit to the digital isolator is conducive to reducing costs.

[0061] It should be understood that the various forms of the processes shown above can be used to reorder, add, or delete steps. For example, the steps described in the present invention can be performed in parallel, sequentially, or in a different order, as long as the desired results of the technical solution of the present invention can be achieved. This is not limited herein.

[0062] The above specific embodiments do not limit the scope of protection of the present invention. Those skilled in the art will appreciate that various modifications, combinations, sub-combinations, and substitutions may be made based on design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention are intended to be included within the scope of protection of the present invention.

Claims

1. A signal demodulation circuit, characterized in that: include: Amplification module and clock detection module; The amplifying module receives a first modulated signal, and is used to amplify the first modulated signal and output a second modulated signal; The clock detection module is connected to the amplification module, and is configured to output a valid level signal according to a transition edge of the clock signal when the second modulation signal has a clock signal, and output an invalid level signal when the second modulation signal does not have the clock signal, to form a demodulated signal, wherein the frequency of the clock signal is the same as the frequency of the carrier signal of the second modulation signal; The clock detection module includes a first delay unit, a second delay unit and a logic and operation unit; The first end of the first delay unit and the first end of the second delay unit are connected to the output end of the amplification module, the second end of the first delay unit is connected to the first input end of the logic and operation unit, and the second end of the second delay unit is connected to the second input end of the logic and operation unit; the first delay unit is used to delay the falling edge of the second modulated signal for a first preset time length, the second delay unit is used to delay the rising edge of the second modulated signal for a second preset time length, and the logic and operation unit is used to perform a logic and operation on the signal output by the first delay unit and the signal output by the second delay unit, and output a demodulated signal; wherein, the first preset time length is equal to the second preset time length, and the first preset time length is greater than the period of the carrier signal in the second modulated signal and less than the period of the baseband signal.

2. The signal demodulation circuit according to claim 1, wherein: The second delay unit includes a first delay sub-unit and a first logic NOT operation sub-unit, the input end of the first logic NOT operation sub-unit is connected to the amplification module, the output end of the first logic NOT operation sub-unit is connected to the first end of the first delay sub-unit, and the second end of the first delay sub-unit is connected to the second input end of the logic AND operation unit. The first logic NOT operation sub-unit is used to invert the second modulated signal, and the first delay sub-unit is used to delay the falling edge of the inverted second modulated signal by the second preset time length.

3. The signal demodulation circuit according to claim 1, wherein: The amplification module includes a comparator, the first modulation signal includes a single modulation signal, the first input end of the comparator is used to receive the first modulation signal, the second input end of the comparator is used to receive a reference signal, the output end of the comparator is connected to the input end of the clock detection module, and the comparator is used to compare the first modulation signal with the reference signal and output the second modulation signal; Alternatively, the first modulation signal includes a differential modulation signal, the first input end of the comparator is used to access the positive differential modulation signal, the second input end of the comparator is used to access the negative differential modulation signal, the output end of the comparator is connected to the input end of the clock detection module, and the comparator is used to compare the positive differential modulation signal and the negative differential modulation signal, and output the second modulation signal when the difference between the positive differential modulation signal and the negative differential modulation signal meets a preset threshold.

4. The signal demodulation circuit according to claim 1, wherein: The signal demodulation circuit further includes a de-jitter module, which is connected to the output end of the clock detection module and is used to filter out interference signals in the demodulated signal output by the clock detection module.

5. The signal demodulation circuit according to claim 4, wherein: The de-jitter module includes a third delay unit, a fourth delay unit and an operation unit, wherein the first end of the third delay unit is connected to the output end of the clock detection module, the second end of the third delay unit is connected to the first input end of the operation unit, the first end of the fourth delay unit is connected to the output end of the clock detection module, and the second end of the fourth delay unit is connected to the second input end of the operation unit; the third delay unit is used to delay the rising edge of the demodulated signal for a third preset time length, the fourth delay unit is used to delay the falling edge of the demodulated signal for a fourth preset time length, and the operation unit is used to latch and output according to the signal output by the third delay unit and the signal output by the fourth delay unit; wherein the delay length of the third delay unit is equal to the delay length of the fourth delay unit, and the delay length of the third delay unit is greater than the length of the interference signal.

6. The signal demodulation circuit according to claim 5, wherein: The fourth delay unit includes a second delay sub-unit and a second logical NOT operation sub-unit, the input end of the second logical NOT operation sub-unit is connected to the output end of the clock detection module, the output end of the second logical NOT operation sub-unit is connected to the first end of the second delay sub-unit, and the second end of the second delay sub-unit is connected to the second input end of the operation unit.

7. The signal demodulation circuit according to claim 5, wherein: The operation unit includes a latch subunit, the first input end of the latch subunit is connected to the second end of the third delay unit, the second input end of the latch subunit is connected to the second end of the fourth delay unit, and the output end of the latch subunit serves as the output end of the operation unit.

8. A digital isolator, characterized in that: It includes a signal modulation circuit, an isolation layer and the signal demodulation circuit described in claims 1 to 7, the isolation layer is connected between the signal modulation circuit and the signal demodulation circuit, the signal modulation circuit is used to modulate the input baseband signal to form a modulation signal, the isolation layer is used to isolate the modulation signal and transmit it to the signal demodulation circuit to form a first modulation signal, and the signal demodulation circuit is used to demodulate the first modulation signal and output a demodulation signal.

9. The digital isolator according to claim 8, wherein: The isolation layer includes a first capacitor and a second capacitor, wherein the first end of the first capacitor is connected to the first input end of the amplifier module in the signal demodulation circuit, the second end of the first capacitor is connected to the first output end of the signal modulation circuit, the first end of the second capacitor is connected to the second input end of the amplifier module, and the second end of the second capacitor is connected to the second output end of the signal modulation circuit; Alternatively, the isolation layer includes a third capacitor, the first end of the third capacitor is connected to the first input end of the amplification module in the signal demodulation circuit, the second end of the third capacitor is connected to the output end of the signal modulation circuit, and the second input end of the amplification module is connected to the reference signal.

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