Design method of three-level active drive circuit for inhibiting bridge arm crosstalk of GaN device

Abstract

The invention belongs to the field of driving circuits of gallium nitride (GaN) power devices in motor driving or power electronic conversion, and discloses a design method of a three-level active driving circuit for restraining bridge arm crosstalk of a GaN device, and the method comprises the steps that a circuit is connected in a bridge type topological structure, and the bridge type topological structure comprises an upper bridge arm and a lower bridge arm which are the same in structure; the upper bridge arm and the lower bridge arm are both divided into two parts, namely a traditional driving circuit and an auxiliary circuit, and the auxiliary circuit is divided into a negative voltage self-recovery circuit and a crosstalk suppression circuit. According to the invention, a negative voltage self-recovery circuit and a crosstalk suppression circuit are formed by using the output and reverse conduction characteristics of the charge pump and the auxiliary GaN device. The advantages of the two methods are combined, the defects of a traditional method are effectively overcome, the turn-off speed is increased, the turn-off loss is reduced, and the positive and negative crosstalk is reduced while the turn-on speed is hardly influenced and the reverse turn-on loss is not additionally increased. The overall design is flexible, efficient and reliable.

Description

Technical Field

[0001] The present invention belongs to the technical field of drive circuits for gallium nitride (GaN) power devices in motor drive or power electronic conversion, and particularly relates to a three-level active drive circuit design method for suppressing crosstalk in the bridge arms of GaN devices. Background Art

[0002] With the development of electric vehicles, servo drive systems, and high-performance charging technologies, as well as the demand for green and low-carbon, high-performance, high-power-density, and low-power-consumption power conversion technologies have become the core in these fields. Among the third-generation wide-bandgap semiconductor devices, GaN power devices have characteristics such as small parasitic capacitance, high switching speed, low on-resistance, low switching losses, and no reverse recovery losses. In the application of GaN power devices, the switching frequency of the power converter can reach hundreds of kilohertz or even dozens of megahertz, enabling smaller filter components to be used in the topology, thereby increasing the power density and reducing the weight. Therefore, GaN power devices are increasingly used in industry.

[0003] However, its excellent characteristics also bring more serious electromagnetic interference (EMI) problems, especially the crosstalk phenomenon in the bridge arm circuit. Crosstalk in the bridge arm circuit occurs when the power device rapidly switches between the on and off states. Especially in medium- and high-voltage applications, a large dv / dt will generate a large current on the parasitic capacitance. This current flows through the internal gate resistance and the drive resistance, thereby generating a transient voltage spike at the gate-source of the power device. Compared with other power devices in the medium- and high-power application range, the on-voltage of GaN and the maximum positive and negative voltages that can be tolerated between the gate and source are very small. The positive voltage spike may exceed the on-threshold voltage, causing the device to be mis-triggered, resulting in bridge arm shoot-through and damaging the power device; serious positive or negative voltage spikes may directly exceed the maximum voltage that the device can withstand, thereby directly damaging the device.

[0004] Existing methods for suppressing crosstalk include: 1) Reducing the switching speed of power devices to decrease the dv / dt generated by the circuit. Usually, methods such as increasing the resistance of the drive circuit or connecting a capacitor in parallel at the gate-source terminal of the power device are used. However, this method will increase the switching loss, which is contrary to the purpose of using GaN power devices. 2) Using negative voltage to reduce the positive crosstalk voltage spike. Usually, an additional negative voltage source, an RCD circuit, or a charge pump is used to generate negative voltage. However, when the current reverse conducts during the dead time, the constant negative voltage used in this method will generate higher reverse conduction loss, and it may cause reverse breakdown due to the superposition of negative crosstalk exceeding the maximum negative voltage that the device's gate-source can withstand. 3) Providing an additional low-impedance path for crosstalk current. Using an active device, an auxiliary branch in which a controllable MOSFET (metal-oxide-semiconductor field-effect transistor) is connected in series with a capacitor is connected in parallel at the gate-source. When positive crosstalk occurs, the MOSFET is turned on to provide a path for the crosstalk current, but it may cause turn-off delay; or a resistor and a triode auxiliary branch are connected in the drive circuit, and the crosstalk current flows through the resistor to generate a voltage drop that turns on the triode, thereby providing a path for the crosstalk current. However, it requires the device to reach the conduction condition, with a slow response speed, and the design of the low-impedance path is difficult. Summary of the Invention

[0005] To solve the problems existing in the prior art, the present invention provides a three-level active drive circuit design method for suppressing crosstalk in GaN device bridge arms. This method utilizes the output and reverse conduction characteristics of a charge pump and an auxiliary GaN device to form a negative voltage self-recovery circuit and a crosstalk suppression circuit. Combining the advantages of both effectively overcomes the defects of traditional methods. This method can accelerate the turn-off speed, reduce the turn-off loss, and reduce positive and negative crosstalk while hardly affecting the turn-on speed and not additionally increasing the reverse conduction loss. The overall design is flexible, efficient, and reliable.

[0006] To achieve the above object, the present invention provides the following solutions:

[0007] A three-level active drive circuit design method for suppressing crosstalk in GaN device bridge arms, the method comprising:

[0008] The circuit is connected in a bridge topology structure, and the bridge topology structure includes an upper bridge arm and a lower bridge arm with the same structure;

[0009] Both the upper bridge arm and the lower bridge arm are divided into two parts, namely a traditional drive circuit and an auxiliary circuit, and the auxiliary circuit is further divided into a negative voltage self-recovery circuit and a crosstalk suppression circuit.

[0010] Preferably, the traditional drive circuit is composed of IC1, VCC, Ron, Roff, Lg, Rin, Q1, Cgd, Cgs, Cds, and Ls;

[0011] Among them, IC1 includes M1 and M2. IC1 is the direct drive chip of the GaN device. M1 and M2 are the equivalent P-MOSFET and N-MOSFET in the drive chip. VCC is the forward drive voltage, Ron is the on-resistance, Roff is the off-resistance, Lg is the gate inductance, Rin is the gate resistance, Q1 is the GaN power device to be controlled in the upper bridge arm, Cgd is the gate-drain capacitance of the power device, Cgs is the gate-source capacitance of the power device, Cds is the drain-source capacitance of the power device, and Ls is the source inductance;

[0012] Use the dual-port drive chip IC1. Connect Ron to the on-port of the drive chip, connect Roff to the off-port of the drive chip, connect the other ends of the two resistors, and then connect them in series with Lg, Rin and the gate of Q1. Connect the drain of Q1 to the load voltage Vdc, and connect the source of Q1 to Ls and then connect it to the upper bridge arm reference ground plane;

[0013] PWM_H is the input control signal of the drive chip Q1, which controls the on and off of Q1.

[0014] Preferably, the negative voltage self-recovery circuit consists of IC2, VCC, C1, D1 and R1;

[0015] Among them, IC2 includes M3 and M4. IC2 is the charge and discharge drive chip of the capacitor C1. M3 and M4 are the equivalent P-MOSFET and N-MOSFET in the drive chip. VCC is the charging voltage, C1 is the energy storage capacitor, D1 is the Schottky diode, and R1 is the discharge resistor;

[0016] Use the single-port drive chip IC2. Connect C1 to the control output terminal of the drive chip, then connect it in series with the anode of the Schottky diode D1, connect the cathode of the Schottky diode to the reference ground plane, connect the discharge resistor R1 in parallel with both ends of the Schottky diode D1. At the same time, connect the ground terminal of IC1 to the anode of D1, and connect the ground terminal of IC2 to the reference ground plane of the upper bridge arm;

[0017] PWM_H is also the control signal of the negative voltage self-recovery circuit, which controls the charging or discharging of C1.

[0018] Preferably, the crosstalk suppression circuit consists of IC3, VCC, VEE, Ron, Q2 and C2;

[0019] Among them, IC3 includes M5 and M6. IC3 includes M5 and M6. IC3 is the drive chip for the auxiliary low-voltage GaN device. M5 and M6 are the equivalent P-MOSFET and N-MOSFET in the drive chip. VCC is the forward drive voltage, VEE is the reverse off voltage, Ron is the on or off resistance, Q2 is the low-voltage GaN power device, and C2 is the auxiliary capacitor for absorbing crosstalk;

[0020] Use a single - port drive chip IC3. The output control terminal of the drive chip is connected to Ron, and then connected to the gate of the auxiliary GaN device Q2. The source of Q2 is connected to the reference ground plane, and the drain is connected to C2 and then to the gate of Q1. At the same time, the ground terminal of IC3 is connected to VEE;

[0021] PWM_HA serves as the input control signal of IC3 to control the on - off of Q2.

[0022] Preferably, the input control signals PWM_H and PWM_L of the main devices on the upper and lower bridge arms are complementary. The two bridge arms conduct alternately. At the same time, a dead - time is added;

[0023] The input control signals PWM_HA and PWM_LA of the crosstalk suppression circuit are complementary, and the two auxiliary GaN devices on the upper and lower bridge arms also conduct alternately;

[0024] The load Load is an inductor, one end is connected to the load voltage, and the other end is connected to the mid - point of the upper and lower bridge arms.

[0025] Preferably, using the charge pump and the output and reverse - conduction characteristics of the auxiliary GaN device, a negative - voltage self - recovery circuit and a crosstalk suppression circuit are formed.

[0026] Preferably, IC1 and IC4 are selected as drive chips with separate drive and turn - off ports, and IC2 and IC3 are selected as single - port drive chips;

[0027] Both the main control drive device and the auxiliary device are GaN devices.

[0028] Compared with the prior art, the beneficial effects of the present invention are:

[0029] The present invention has a negative - voltage self - recovery function. When the current reversely free - wheels during the dead - time, the negative voltage becomes zero, preventing the additional reverse - conduction loss caused by using a constant negative voltage. Before conduction, the negative voltage drops to zero, also preventing the additional conduction time starting from the negative voltage.

[0030] The crosstalk suppression circuit does not work at the turn - on and turn - off moments of the present invention, and hardly affects the switching speed of the original traditional drive circuit. When the device is turned off, the negative voltage generated by the negative - voltage self - recovery circuit speeds up the turn - off speed of the power device and reduces the energy loss generated during the device turn - off period.

[0031] The present invention effectively suppresses the forward crosstalk. When forward crosstalk occurs, the crosstalk current flows through the low - impedance path generated by the crosstalk suppression circuit, and the forward crosstalk is superimposed on the negative voltage generated by the negative - voltage self - recovery circuit, further suppressing the positive crosstalk voltage from exceeding the gate - source conduction threshold voltage of the device, effectively and reliably preventing the occurrence of mis - conduction events during operation.

[0032] The present invention effectively suppresses negative crosstalk. When negative crosstalk occurs, the crosstalk current flows through the low-impedance path generated by the crosstalk suppression circuit, and at this time, the negative voltage source has dropped to zero, and only a very small negative pulse voltage is generated at the gate-source of the device, effectively and reliably preventing the device breakdown event caused by exceeding the maximum negative pressure of the gate-source during operation. Description of the Drawings

[0033] In order to more clearly illustrate the technical solutions of the present invention, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0034] Figure 1 Schematic diagram of the three-level active drive circuit according to Embodiment 3 of the present invention;

[0035] Figure 2 Schematic diagram of the output characteristics and reverse conduction characteristics curves of the GaN device according to Embodiment of the present invention;

[0036] Figure 3 Schematic diagram of the circuit operation timing according to Embodiment of the present invention;

[0037] Figure 4 Circuit operation diagram of Mode Ⅰ according to Embodiment of the present invention;

[0038] Figure 5 Circuit operation diagram of Mode Ⅱ according to Embodiment of the present invention;

[0039] Figure 6 Circuit operation diagram of Mode Ⅲ according to Embodiment of the present invention;

[0040] Figure 7 Circuit operation diagram of Mode Ⅳ according to Embodiment of the present invention;

[0041] Figure 8 Circuit operation diagram of Mode Ⅴ according to Embodiment of the present invention;

[0042] Figure 9 Circuit operation diagram of Mode Ⅵ according to Embodiment of the present invention;

[0043] Figure 10 Comparison diagram of the drain-source voltage waveforms of the device during the turn-on and turn-off stages according to Embodiment of the present invention, where (a) is the comparison diagram of the drain-source voltage waveforms of the device during the turn-on stage; (b) is the comparison diagram of the drain-source voltage waveforms of the device during the turn-off stage;

[0044] Figure 11 Comparison diagram of the positive and negative crosstalk voltage waveforms of the gate-source of the device according to Embodiment of the present invention, where (a) is the comparison diagram of the positive crosstalk voltage waveforms of the gate-source of the device; (b) is the comparison diagram of the negative crosstalk voltage waveforms of the gate-source of the device. Detailed implementation manners

[0045] The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0046] In order to make the above objects, features and advantages of the present invention more obvious and understandable, the present invention will be further described in detail below with reference to the accompanying drawings and specific implementation manners.

[0047] Embodiment 1

[0048] This embodiment proposes a three-level active drive circuit design method for suppressing crosstalk in the bridge arm of a GaN device. The three-level means that when a conduction signal arrives, the gate-source voltage of the GaN device is a positive voltage, and when it is turned off, it is a negative voltage. Before the next conduction signal arrives, the voltage between the gate and the source drops to zero; the active means that a controllable device and a capacitor are connected in series to form a low-impedance path to suppress positive and negative crosstalk. The circuit is connected in a bridge topology structure, which includes an upper bridge arm and a lower bridge arm. The upper bridge arm is divided into two parts, namely a traditional drive circuit and an auxiliary circuit. The auxiliary circuit is further divided into a negative voltage self-recovery circuit and a crosstalk suppression circuit.

[0049] The traditional drive circuit consists of IC1 (including M1 and M2), VCC, Ron, Roff, Lg, Rin, Q1, Cgd, Cgs, Cds, and Ls. Among them, IC1 is a direct drive chip for the GaN device, M1 and M2 are equivalent P-MOSFET and N-MOSFET in the drive chip, VCC is the forward drive voltage, Ron is the turn-on resistance, Roff is the turn-off resistance, Lg is the gate inductance, Rin is the gate resistance, Q1 is the GaN power device that is the control object of the upper bridge arm, Cgd is the gate-drain capacitance of the power device, Cgs is the gate-source capacitance of the power device, Cds is the drain-source capacitance of the power device, and Ls is the source inductance. The dual-port drive chip IC1 is used. Ron is connected to the turn-on port of the drive chip, Roff is connected to the turn-off port of the drive chip, and the other ends of the two resistors are connected and then connected in series with Lg, Rin, and the gate of Q1. The drain of Q1 is connected to the load voltage Vdc, and the source of Q1 is connected to Ls and then connected to the upper bridge arm reference ground plane. PWM_H is the input control signal of the drive chip Q1, which controls the turn-on and turn-off of Q1.

[0050] The negative voltage self - recovery circuit consists of IC2 (including M3 and M4), VCC, C1, D1, and R1. Among them, IC2 is the charge - discharge driving chip for capacitor C1, M3 and M4 are the equivalent P - MOSFET and N - MOSFET in the driving chip, VCC is the charging voltage, C1 is the energy - storage capacitor, D1 is the Schottky diode, and R1 is the discharge resistor. Using a single - port driving chip IC2, C1 is connected to the control output terminal of the driving chip, then the anode of the Schottky diode D1 is connected in series, the cathode of the Schottky diode is connected to the reference ground plane, the discharge resistor R1 is connected in parallel across the two ends of the Schottky diode D1. At the same time, the grounding terminal of IC1 is connected to the anode of D1, and the grounding terminal of IC2 is connected to the reference ground plane of the upper bridge arm. PWM_H is also the control signal for the negative voltage self - recovery circuit, controlling the charging or discharging of C1. s

[0051] The crosstalk suppression circuit consists of IC3 (including M5 and M6), VCC, VEE, Ron, Q2, and C2. Among them, IC3 is the driving chip for the auxiliary low - voltage GaN device, M5 and M6 are the equivalent P - MOSFET and N - MOSFET in the driving chip, VCC is the forward driving voltage, VEE is the reverse turn - off voltage, Ron is the on - or - off resistance, Q2 is the low - voltage GaN power device, and C2 is the auxiliary capacitor for absorbing crosstalk. Using a single - port driving chip IC3, the control output terminal of the driving chip is connected to Ron, then connected to the gate of the auxiliary GaN device Q2, the source of Q2 is connected to the reference ground plane, the drain is connected to C2 which is connected to the gate of Q1. At the same time, the grounding terminal of IC3 is connected to VEE. PWM_HA is used as the input control signal of IC3 to control the on - off of Q2.

[0052] The composition structure of the lower bridge arm is the same as that of the upper bridge arm. The main device input control signals PWM_H and PWM_L of the upper and lower bridge arms are complementary, and the two bridge arms conduct alternately. To avoid shoot - through of the bridge arms, a dead - time is added. The input control signals PWM_HA and PWM_LA of the crosstalk suppression circuit are complementary, and the two auxiliary GaN devices of the upper and lower bridge arms also conduct alternately. There is no shoot - through problem in the auxiliary circuit, so there is no need to add a dead - time. The load Load is an inductor, one end is connected to the load voltage, and the other end is connected to the mid - point of the upper and lower bridge arms.

[0053] The circuit operating principles of the upper and lower bridge arms are the same. Taking the upper bridge arm as an example, the operating principle of the traditional driving circuit: When the high - voltage pulse of PWM_H arrives, it is the forward - conduction signal, M1 conducts, M2 turns off, Ron works, and VCC charges the gate - source capacitor of Q1, making Q1 conduct; when the low - voltage pulse of PWM_H arrives, it is the turn - off signal, M1 turns off, M2 conducts, Roff works, and the gate - source capacitor of Q1 discharges, making Q1 turn off.

[0054] Working principle of the negative voltage self - recovery circuit: When the high - voltage pulse of PWM_H arrives, it is a forward - conduction signal. M3 conducts, M4 turns off, and VCC charges C1. At this time, D1 conducts and R1 does not participate in the charging process. When the low - voltage pulse of PWM_H arrives, it is a turn - off signal. M3 turns off, M4 conducts, the original positive - voltage terminal of C1 is connected to the reference ground plane, which is equivalent to the other end of C1 becoming a negative voltage, providing a negative voltage to form a negative - voltage turn - off. At this time, D1 does not function and R1 functions to discharge. After a period of time, the voltage across C1 drops to 0V.

[0055] Working principle of the crosstalk suppression circuit: When the high - voltage pulse of PWM_HA arrives, it is a forward - conduction signal. M5 conducts, M6 turns off, and VCC charges the gate - source capacitance of Q2. At this time, Q2 conducts, and the crosstalk suppression circuit composed of Q2 and C2 functions to provide a low - impedance path for the crosstalk current to flow through. When the low - voltage pulse of PWM_HA arrives, it is a turn - off signal. M5 turns off, M6 conducts, the gate - source capacitance of Q2 discharges rapidly, and its gate - source voltage is set to VEE. At this time, Q2 turns off, and the crosstalk suppression circuit composed of Q2 and C2 does not function, and the positive and negative - direction currents cannot flow through it.

[0056] The present invention requires the four control signals of PWM_H, PWM_HA, PWM_L, and PWM_LA of the upper and lower bridge arms to cooperate with each other, that is, the traditional drive circuit, the negative - voltage self - recovery circuit, and the crosstalk suppression circuit cooperate with each other to achieve the purpose of efficiently and reliably accelerating the turn - off speed and suppressing the positive and negative crosstalk. When the high - voltage pulse of the main drive signal of the lower bridge arm arrives, in order not to affect the turn - on speed, its crosstalk suppression auxiliary power device is in the off state, and the capacitor of the negative - voltage self - recovery circuit starts to charge to prepare for generating a negative voltage. At the same time, the main drive signal of the upper bridge arm is a low - voltage pulse, and the negative voltage of the capacitor is discharging through the resistor. The crosstalk suppression circuit of the upper bridge arm is turned on to prepare in advance for the arrival of crosstalk. When the main power device of the lower bridge arm is turned on, the voltage across the power device of the upper bridge arm changes instantaneously, generating a positive crosstalk current. The crosstalk current flows through the low - impedance path generated by the crosstalk suppression circuit to avoid generating a large voltage, and the positive crosstalk is superimposed on the negative voltage to further suppress the positive crosstalk voltage from exceeding the gate - source conduction threshold voltage of the device. Then, the voltage across the capacitor in the negative - voltage self - recovery circuit of the upper bridge arm drops to zero. When the low - voltage pulse of the main drive signal of the lower bridge arm arrives, the power device of the lower bridge arm turns off. Therefore, the voltage across the power device of the upper bridge arm changes instantaneously again, generating a negative crosstalk current. The crosstalk current flows through the low - impedance path generated by the crosstalk suppression circuit to avoid generating a large negative voltage between the gate and source of the device, and at this time, the negative - voltage source has dropped to zero, only generating a very small negative crosstalk voltage.

[0057] Embodiment Two

[0058] The following further describes Embodiment One of the present invention in combination with the accompanying drawings and specific implementation cases.

[0059] The present invention proposes a three-level active drive circuit for suppressing crosstalk in the bridge arms of GaN devices. Figure 1 The circuit diagram of the embodiment of the present invention is shown, and the circuit is connected in the upper and lower bridge arms of the bridge topology. Each bridge arm is divided into two parts, namely the traditional drive circuit and the auxiliary circuit, and the auxiliary circuit is further divided into a negative voltage self-recovery circuit and a crosstalk suppression circuit. The GaN device in this embodiment is selected as INN650D080BS.

[0060] Taking the upper bridge arm as an example, the traditional drive circuit consists of IC1 (including M1 and M2), VCC, Ron, Roff, Lg, Rin, Q1, Cgd, Cgs, Cds, and Ls. Among them, IC1 is the direct drive chip of the GaN device, M1 and M2 are the equivalent P-MOSFET and N-MOSFET in the drive chip, VCC is the forward drive voltage, Ron is the on-resistance, Roff is the off-resistance, Lg is the gate inductor, Rin is the gate resistance, Q1 is the GaN power device to be controlled in the upper bridge arm, Cgd is the gate-drain capacitance of the power device, Cgs is the gate-source capacitance of the power device, Cds is the drain-source capacitance of the power device, and Ls is the source inductor. The dual-port drive chip IC1 is used. Ron is connected to the on-port of the drive chip, Roff is connected to the off-port of the drive chip, and the other ends of the two resistors are connected together and then connected in series with Lg, Rin, and the gate of Q1. The drain of Q1 is connected to the load voltage Vdc, and the source of Q1 is connected to Ls and then connected to the reference ground plane of the upper bridge arm. PWM_H is the input control signal of the drive chip Q1, which controls the on and off of Q1.

[0061] The negative voltage self-recovery circuit consists of IC2 (including M3 and M4), VCC, C1, D1, and R1. Among them, IC2 is the charge and discharge drive chip of the capacitor C1, M3 and M4 are the equivalent P-MOSFET and N-MOSFET in the drive chip, VCC is the charging voltage, C1 is the energy storage capacitor, D1 is the Schottky diode, and R1 is the discharge resistor. The single-port drive chip IC2 is used. C1 is connected to the control output terminal of the drive chip, and then connected in series with the anode of the Schottky diode D1. The cathode of the Schottky diode is connected to the reference ground plane, and the discharge resistor R1 is connected in parallel across the Schottky diode D1. At the same time, the ground terminal of IC1 is connected to the anode of D1, and the ground terminal of IC2 is connected to the reference ground plane of the upper bridge arm. PWM_H is also the control signal of the negative voltage self-recovery circuit, which controls the charging or discharging of C1.

[0062] The crosstalk suppression circuit consists of IC3 (including M5 and M6), VCC, VEE, Ron, Q2, and C2. Among them, IC3 is a driving chip for assisting low-voltage GaN devices, M5 and M6 are equivalent P-MOSFET and N-MOSFET in the driving chip, VCC is the forward driving voltage, VEE is the reverse turn-off voltage, Ron is the on or off resistance, Q2 is a low-voltage GaN power device, and C2 is an auxiliary capacitor for absorbing crosstalk. A single-port driving chip IC3 is used. The output control terminal of the driving chip is connected to Ron, and then connected to the gate of the auxiliary GaN device Q2. The source of Q2 is connected to the reference ground plane, the drain is connected to C2 and then connected to the gate of Q1. At the same time, the ground terminal of IC3 is connected to VEE. PWM_HA serves as the input control signal of IC3 to control the on and off of Q2.

[0063] The composition structure of the lower bridge arm is the same as that of the upper bridge arm. The input control signals PWM_H and PWM_L of the main devices of the upper and lower bridge arms are complementary, and the two bridge arms conduct alternately. To avoid shoot-through of the bridge arms, a dead time is added. The input control signals PWM_HA and PWM_LA of the crosstalk suppression circuit are complementary, and the two auxiliary GaN devices of the upper and lower bridge arms also conduct alternately. There is no shoot-through problem in the auxiliary circuit, so there is no need to add a dead time. The load Load is an inductor, one end is connected to the load voltage, and the other end is connected to the midpoint of the upper and lower bridge arms. Take VCC = +5V, VEE = -3V, and Load = 100μH.

[0064] The negative voltage self-recovery circuit mainly uses the principle of charge pump. When the input control signal is at a high level, +5V charges the capacitor C1, and positive charges accumulate on the left side of the capacitor. The Schottky diode D1 conducts, and the parallel R1 at both ends does not participate in the charging process. When the input control signal becomes low, due to the voltage across the capacitor not changing suddenly, the left side of the capacitor is equivalent to being connected to the reference ground plane, and the voltage on the right side of the capacitor will become negative, thus generating a negative voltage at the output. At this time, D1 does not work, and R1 works for discharging. After a period of time, the voltage across C1 drops to zero.

[0065] The crosstalk suppression circuit mainly utilizes the output and reverse conduction characteristics of the auxiliary GaN device, as Figure 2 shown. When the gate-source voltage is -3V, it cannot conduct forward, and when the drain-source voltage is less than -4V, it can conduct reversely; when the gate-source voltage is +5V, the GaN device can conduct freely in both positive and negative directions. When the input control signal is at a high level, +5V charges the gate-source of the Q2 auxiliary GaN device. At this time, Q2 conducts, and the crosstalk suppression path composed of Q2 and C2 functions to provide a low-impedance path for the crosstalk current to flow through; when the input control signal is at a low level, the gate-source capacitor of Q2 discharges quickly and sets its gate-source voltage to -3V. At this time, Q2 turns off, and current in both positive and negative directions cannot flow through the crosstalk suppression circuit, that is, the crosstalk suppression circuit composed of Q2 and C2 does not work.

[0066] This implementation case mainly illustrates the operation circuits of six modes corresponding to the upper-bridge-arm driving GaN device before and after turn-off, as Figure 3 shown. The switching frequency is 100KHZ, the dead time is 100ns, and the duty cycle is 0.5, that is, the conduction time is 5μs.

[0067] Mode Ⅰ [t0 - t1]: At this time, the circuit is as Figure 4 shown. The lower driving tube is in the off state, the upper driving tube is in the on state, the gate-source voltage of Q1 is +5V, and the voltage across capacitor C1 is (5 - VD)V, where VD is the conduction voltage drop of the Schottky diode. The lower auxiliary tube is in the on state, and the gate-source voltage of Q4 is +5V. The upper auxiliary tube is in the off state, and the gate-source voltage of Q2 is -3V.

[0068] Mode Ⅱ [t1 - t2]: At this time, the circuit is as Figure 5 shown. At time t1, entering the dead time, the lower driving tube is still in the off state, the upper driving tube starts to turn off, M1 turns off, M2 turns on, M3 turns off, M4 turns on, and Roff = 3Ω acts. The original positive voltage terminal of C1 is connected to the reference ground plane, which is equivalent to the other end of C1 becoming a negative voltage. The turn-off negative voltage is U_off:

[0069]

[0070] Among them, Qg = 5.4nC is the charge required to turn on the gate of the GaN device, and Cgs = 224.5pF is the gate-source capacitance of the GaN device. To make U_off = -2V, then C1 = C3 = 2.2nF, forming a negative voltage turn-off, which makes Q1 turn off. At this time, D1 does not act, and R1 acts to discharge. By selecting an appropriate time constant, it is ensured that the voltage is still negative when discharging until the auxiliary tube turns on and positive crosstalk occurs, and it drops to zero before negative crosstalk occurs. R1 = R2 = 51Ω. The switching states of the upper and lower bridge-arm auxiliary tubes are the same as those in Mode Ⅰ. The crosstalk suppression circuit of the upper bridge arm does not work due to the negative voltage of the gate-source of Q2 and hardly affects the turn-off time of the device.

[0071] Mode Ⅲ [t2 - t3]: At this time, the circuit is as Figure 6As shown in Figure 2, the PWM_A on / off timings of the upper and lower bridge auxiliary driver transistors are set to half the corresponding dead-time. At time t2, the lower driver transistor remains off, and the upper driver transistor is also off, allowing capacitor C1 to continue discharging. The lower-arm auxiliary GaN device begins to shut down, with M11 off and M12 on. This rapidly discharges the gate-source capacitance of Q4, setting its gate-source voltage to -3V, and Q4 turns off. The upper-arm auxiliary GaN device begins to turn on, with M5 on and M6 off. +5V charges the gate-source capacitance of Q2, turning Q2 on. The crosstalk suppression circuit formed by Q2 and C2 provides a low-impedance path, preparing for the onset of crosstalk current. Due to the connection of the upper-arm auxiliary capacitor C2 at time t2, the charge across C1 is redistributed, causing the gate-source voltage of the upper-arm driver transistor to increase instantaneously at time t2, increasing the discharge time constant.

[0072] Mode IV [t3-t4]: At this time, the circuit is as follows Figure 7 As shown. At this stage, the upper and lower bridge arm auxiliary transistors are the same as in Mode III. The lower auxiliary transistor Q4 is in negative voltage shutdown, barely affecting the conduction of the lower main driver transistor Q3. The upper driver transistor remains off, and the negative voltage continues to discharge through R1. The lower bridge arm driver transistor begins to conduct, with M7 on and M8 off. Ron acts, and the +5V voltage charges the gate-source capacitance of Q3, turning Q3 on. The conduction circuit consists of a power supply, resistors, inductors, and capacitors, so its second-order differential equation is:

[0073]

[0074] Its damping ratio is:

[0075]

[0076] Where, Ciss = Cgs + Cgd = 225pF, Lg = 5nF, Rin = 3Ω. To prevent the gate-source voltage of the GaN device from overshooting and damaging the device, there is no overshoot when the damping ratio is greater than or equal to 1, and Ron = 7Ω.

[0077] In the negative voltage reset circuit, M9 is turned on, M10 is turned off, and +5V charges C3. At this point, D2 is turned on, and R3 does not participate in the charging process. Due to the rapid switching of the lower-side driver Q3 from off to on, the voltage across Q1 instantly changes from 0V to 400V. The dv / dt transient generates a large current in Q1's parasitic capacitance. This current flows through the internal gate resistor and the driver resistor, generating a positive transient voltage spike at the gate-source of the power device. However, before the lower-side driver Q3 turns on, the crosstalk suppression circuit has already been activated.

[0078] To ensure safe operation of the circuit, the positive and negative crosstalk voltage spikes at the gate-source of the GaN driver device should be limited to a reasonable range. Therefore, the sizes of the auxiliary capacitors C2 and C4 need to be reasonably selected. The positive and negative crosstalk voltages need to be limited to the following ranges:

[0079]

[0080] Among them, ΔV P is the positive crosstalk voltage, and ΔV N is the negative crosstalk voltage. V gs_off is the gate-source voltage when crosstalk occurs. V gs_min =-6V is the maximum negative voltage that the gate-source of the GaN device can withstand. V th =1.2V is the gate-source turn-on threshold voltage.

[0081] The positive crosstalk voltage is:

[0082]

[0083] The negative crosstalk voltage is:

[0084]

[0085] Among them, T f is the device fall time, and T r is the device rise time. Under the above conditions, when C1 = 10nF is taken, the positive crosstalk can be effectively suppressed. Then, before t4, the negative voltage of the gate-source of Q1 drops to 0V.

[0086] Mode Ⅴ [t4 - t5]: At this time, the circuit is as Figure 8 shown. At time t4, the gate-source voltage of the upper-bridge-arm GaN device Q1 has dropped to 0V. The lower-bridge-arm drive transistor Q3 starts to turn off, M7 turns off, M8 turns on, the Roff acts, and the gate-source capacitance of Q1 discharges, causing Q1 to turn off. M9 of the negative voltage self-recovery circuit turns off, M10 turns on, C3 provides negative voltage turn-off, and at this time D1 does not act, and R1 acts to discharge. Since the lower-bridge-arm drive transistor Q3 switches from on to off quickly, the voltage across Q1 changes from 400V to 0V instantaneously, and a large current is generated on the parasitic capacitance due to dv / dt. This current flows through the internal gate resistance and the drive resistance, thereby generating a transient voltage spike at the gate-source of the power device. However, before the lower-bridge-arm drive transistor Q3 turns off, the crosstalk suppression circuit has already turned on. The same as described in Mode Ⅳ, the two crosstalk current flow paths are the same and the directions are opposite. The low-impedance path composed of C2 and Q2 can effectively suppress the negative crosstalk.

[0087] Mode Ⅵ [t5 - t6]: At this time, the circuit is as Figure 9As shown in the figure. At time t5, the lower driving transistor is still in the off state, and the upper driving transistor is also in the off state. The lower-bridge auxiliary GaN device starts to turn on, M11 turns on, M12 turns off, the gate-source capacitance of Q4 is quickly charged to +5V, Q4 turns on, and the crosstalk suppression circuit composed of Q4 and C4 provides a low-impedance path to prepare in advance for the arrival of the crosstalk current of the lower transistor. The upper-bridge auxiliary GaN device starts to turn off, M5 turns off, M6 conducts, the gate-source capacitance of Q2 quickly discharges, and its gate-source voltage is set to -3V. At this time, Q2 turns off to prepare for not affecting the turn-on of the upper-bridge driving transistor.

[0088] The operation of Mode VI ends, the dead time ends, and then it returns to Mode I. The specific implementation case of this invention ends. Through the above-mentioned component values and parameter values, the following technical effects can be achieved:

[0089] It has the function of negative voltage self-recovery. When the current reversely freewheels during the dead time, the negative voltage becomes zero, preventing the additional reverse conduction loss caused by using a constant negative voltage. The negative voltage drops to zero before conduction, also preventing the additional conduction time caused by starting conduction from the negative voltage.

[0090] The crosstalk suppression circuit does not work at the turn-on moment and the turn-off moment, and hardly affects the switching speed of the original traditional drive circuit. As Figure 10 (a) shows, compared with the traditional drive, the turn-on delay of the drive circuit of the present invention is only 1.5ns, and it reaches 0V almost at the same time; when the device turns off, the negative voltage generated by the negative voltage self-recovery circuit speeds up the turn-off speed of the power device. As Figure 10 (b) shows, compared with the traditional drive, the drive circuit of the present invention turns off 8ns in advance, reducing the energy loss generated during the turn-off of the device.

[0091] Effectively suppresses the positive crosstalk. As Figure 11 (a) shows, the positive crosstalk value generated by the traditional drive circuit reaches 1.7V, exceeding the gate-source threshold voltage of the GaN device by 1.2V. The drive circuit proposed in this invention reduces the positive crosstalk value to -0.16V, effectively preventing the occurrence of mis-conduction events during operation.

[0092] Effectively suppresses the negative crosstalk. As Figure 11 (b) shows, the negative crosstalk value generated by the traditional drive circuit reaches -12V, exceeding the maximum negative voltage that the GaN device can withstand at the gate-source by -6V. The drive circuit proposed in this invention reduces the negative crosstalk value to -0.4V, effectively preventing the occurrence of negative device breakdown events during operation.

[0093] The embodiments described above are only descriptions of the preferred embodiments of the present invention, and do not limit the scope of the present invention. Without departing from the design spirit of the present invention, various deformations and improvements made by those of ordinary skill in the art to the technical solutions of the present invention shall fall within the protection scope determined by the claims of the present invention.

Claims

1. A design method for a three-level active driving circuit to suppress crosstalk in the bridge arm of a GaN device, characterized in that, The method includes: The circuit is connected in a bridge topology, and the bridge topology includes an upper arm and a lower arm with the same structure; Both the upper arm and the lower arm are divided into two parts, namely a traditional drive circuit and an auxiliary circuit, and the auxiliary circuit is further divided into a negative voltage self - recovery circuit and a crosstalk suppression circuit.

2. The method according to claim 1, wherein The traditional drive circuit consists of IC1, VCC, Ron, Roff, Lg, Rin, Q1, Cgd, Cgs, Cds, and Ls; Among them, IC1 includes M1 and M2. IC1 is a direct drive chip for GaN devices. M1 and M2 are equivalent P - MOSFET and N - MOSFET in the drive chip. VCC is the forward drive voltage, Ron is the on - resistance, Roff is the off - resistance, Lg is the gate inductor, Rin is the gate resistor, Q1 is the GaN power device controlled by the upper arm, Cgd is the gate - drain capacitance of the power device, Cgs is the gate - source capacitance of the power device, Cds is the drain - source capacitance of the power device, and Ls is the source inductor; Use a dual - port drive chip IC1. Ron is connected to the on - port of the drive chip, Roff is connected to the off - port of the drive chip. The other ends of the two resistors are connected, and then are connected in series with Lg, Rin, and the gate of Q1. The drain of Q1 is connected to the load voltage Vdc, and the source of Q1 is connected to Ls and then connected to the reference ground plane of the upper arm; PWM_H is the input control signal for the drive chip Q1, controlling the on and off of Q1.

3. The method according to claim 1, characterized in that The negative voltage self - recovery circuit consists of IC2, VCC, C1, D1, and R1; Among them, IC2 includes M3 and M4. IC2 is a charge - discharge drive chip for the capacitor C1. M3 and M4 are equivalent P - MOSFET and N - MOSFET in the drive chip. VCC is the charging voltage, C1 is the energy - storage capacitor, D1 is the Schottky diode, and R1 is the discharge resistor; Use a single - port drive chip IC2. C1 is connected to the control output terminal of the drive chip, and then is connected in series with the anode of the Schottky diode D1. The cathode of the Schottky diode is connected to the reference ground plane. The discharge resistor R1 is connected in parallel across the Schottky diode D1. At the same time, the ground terminal of IC1 is connected to the anode of D1, and the ground terminal of IC2 is connected to the reference ground plane of the upper arm; PWM_H is also the control signal for the negative voltage self - recovery circuit, controlling the charging or discharging of C1.

4. The method according to claim 1, characterized in that, The crosstalk suppression circuit consists of IC3, VCC, VEE, Ron, Q2, and C2; Among them, IC3 includes M5 and M6. IC3 is a drive chip for auxiliary low - voltage GaN devices. M5 and M6 are equivalent P - MOSFET and N - MOSFET in the drive chip. VCC is the forward drive voltage, VEE is the reverse off - voltage, Ron is the on - or off - resistance, Q2 is the low - voltage GaN power device, and C2 is the auxiliary capacitor for absorbing crosstalk; Use a single - port drive chip IC3. The output control terminal of the drive chip is connected to Ron, and then is connected to the gate of the auxiliary GaN device Q2. The source of Q2 is connected to the reference ground plane, and the drain is connected to C2 and then connected to the gate of Q1. At the same time, the ground terminal of IC3 is connected to VEE; PWM_HA serves as the input control signal for IC3 to control the on / off of Q2.

5. The method according to claim 1, characterized in that The input control signals PWM_H and PWM_L of the main devices in the upper and lower bridge arms are complementary. The two bridge arms conduct alternately, and at the same time, a dead time is added. The input control signals PWM_HA and PWM_LA of the crosstalk suppression circuit are complementary, and the two auxiliary GaN devices in the upper and lower bridge arms also conduct alternately. The load Load is an inductor, with one end connected to the load voltage and the other end connected to the midpoint of the upper and lower bridge arms.

6. The method according to claim 1, characterized in that By utilizing the output and reverse conduction characteristics of the charge pump and the auxiliary GaN device, a negative voltage self-recovery circuit and a crosstalk suppression circuit are formed.

7. The method according to claim 1, characterized in that, IC1 and IC4 are selected as driver chips with separate driving and turning-off ports, and IC2 and IC3 are selected as single-port driver chips. Both the main control driving device and the auxiliary device are GaN devices.

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