High-speed linear phase discriminator

Abstract

The invention discloses a high-speed linear phase discriminator which comprises a channel transistor logic module 1, a channel transistor logic module 2, an AND gate AND1 and a reset path. The channel transistor logic module 1, the channel transistor logic module 2, the AND gate AND1 and the reset path are electrically connected. The channel transistor logic module is used for pre-charging, the logic complexity is reduced, the phase discriminator of the structure has higher maximum frequency, the zero phase difference dead zone of the phase discriminator is eliminated by feeding back and accelerating the circuit reset process when the same level is output, and the charge and discharge linearity of a follow-up charge pump is optimized by conducting pulse compensation.

Description

Technical Field

[0001] The present invention belongs to the field of hybrid integrated circuits, and particularly relates to a high-speed linear phase detector. Background Art

[0002] Phase detectors are used in radio frequency (RF) systems and modems to extract and compare the phases of carrier signals. In the development of phase-locked loops (PLLs), phase detectors serve as a key component for achieving frequency and phase synchronization. In mobile wireless communications, portable wireless terminals, and highly integrated multi-channel optical fiber receivers, high-speed, low-power PLLs operating in the range of several hundred megahertz or even higher frequencies are particularly important. Phase detectors are one of the important components of PLL systems and play an important role in determining the locking time of PLL systems.

[0003] With the development of communication technologies such as optical communication, satellite communication, and 5G, the demand for high-frequency, high-precision, and low-noise phase detectors is increasing continuously, driving the design of phase detectors with higher bandwidths and lower latencies. Conventional phase detectors all use D-type flip-flops. However, D-type flip-flops and other logic gates will limit the maximum operating frequency of the phase detector and cannot eliminate the zero-phase phase detection dead zone. Although adding a delay unit in the feedback path of conventional phase detectors can eliminate the zero-phase phase detection dead zone, the excessively long hold time will also limit the phase detection range of the phase detector; while non-linear phase detectors with higher operating frequencies have shorter hold pulse widths, which will lead to deterioration of the charge pump charging and discharging linearity of the subsequent stage. Summary of the Invention

[0004] Object of the Invention: In order to solve the problems existing in the above-mentioned prior art, the present invention discloses a high-speed linear phase detector.

[0005] Technical Solution: The present invention discloses a high-speed linear phase detector, which includes a first-channel transistor logic module, a second-channel transistor logic module, a reset path, and an AND gate; both the first and second-channel transistor logic modules include a pre-charge module and a signal transmission module connected to each other, and the node connecting the pre-charge module and the signal transmission module is denoted as the pre-charge node.

[0006] The external clock signal is input to the input terminal of the first-channel transistor logic module, and the external reference clock signal is input to the input terminal of the second-channel transistor logic module; when the external clock signal or the external reference clock signal is at a low level, the pre-charge module of the corresponding channel transistor logic module charges; when the external clock signal or the external reference clock signal is at a high level, the clock signal is output through the signal transmission module of the corresponding channel transistor logic module. The first transistor logic module outputs the signal DOWN to the first input terminal of the AND gate, and the first transistor logic module outputs the signal UP to the second input terminal of the AND gate; the output terminal of the AND gate is connected to the reset path, and the reset path outputs the signal Q1 to the pre-charge node of the first-channel transistor logic module to reset the signal DOWN, and the reset path outputs the signal Q2 to the pre-charge node of the second-channel transistor logic module to reset the signal UP.

[0007] Further, the pre-charge module includes a first MOS transistor. The gate of the first MOS transistor serves as the input terminal of the corresponding channel transistor logic module, the source is connected to the power supply voltage, and the drain serves as the pre-charge node.

[0008] Further, the first MOS transistor is a PMOS transistor.

[0009] Further, the signal transmission module includes a first inverter, a second inverter, and a second MOS transistor. The input terminal of the first inverter is connected to the pre-charge node, the output terminal is connected to the drain of the second MOS transistor, the gate of the second MOS transistor is connected to the input terminal of the corresponding channel transistor logic module, the source is connected to the input terminal of the second inverter, and the output terminal of the second inverter serves as the output terminal of the corresponding channel transistor logic module.

[0010] Further, the second MOS transistor is an NMOS transistor.

[0011] Further, the reset path includes the third to tenth MOS transistors. The gate of the third MOS transistor is connected to the input end of the first channel transistor logic module, the drain is connected to the pre-charge node of the first channel transistor logic module and the gate of the eighth MOS transistor, and the third source is connected to the drain of the fourth MOS transistor and the source of the sixth MOS transistor. The source of the fourth MOS transistor is connected to the pre-charge node of the second channel transistor logic module and the gate of the seventh MOS transistor. The gate of the fourth MOS transistor is connected to the input end of the second channel transistor logic module. The gate of the sixth MOS transistor is connected to the gate of the fifth MOS transistor and the output end of the AND gate. The drain of the sixth MOS transistor is connected to the source of the fifth MOS transistor, and the drain of the fifth MOS transistor is grounded. The drain of the seventh MOS transistor is connected to the output end of the first inverter in the first channel transistor logic module and the gate of the tenth MOS transistor. The source of the seventh MOS transistor is connected to the source of the eighth MOS transistor and the power supply voltage. The drain of the eighth MOS transistor is connected to the output end of the first inverter in the second channel transistor logic module and the gate of the ninth MOS transistor. The sources of the ninth MOS transistor and the tenth MOS transistor are connected to each other and then grounded. The drain of the ninth MOS transistor is connected to the output end of the first channel transistor logic module, and the drain of the tenth MOS transistor is connected to the output end of the second channel transistor logic module.

[0012] Further, the third to sixth MOS transistors, the ninth and tenth MOS transistors are all NMOS transistors, and the seventh and eighth MOS transistors are all PMOS transistors.

[0013] Further, the reset path further includes the eleventh and twelfth MOS transistors and the first and second NOR gates. The first input end of the first NOR gate is connected to the input end of the first channel transistor logic module and the first input end of the second NOR gate. The second input end of the first NOR gate is connected to the second input end of the second NOR gate and the input end of the second channel transistor logic module. The output end of the first NOR gate is connected to the gate of the eleventh MOS transistor. The source of the eleventh MOS transistor is grounded, and the drain is connected to the output end of the first channel transistor logic module. The output end of the second NOR gate is connected to the gate of the twelfth MOS transistor. The source of the twelfth MOS transistor is grounded, and the drain of the twelfth MOS transistor is connected to the output end of the second channel transistor logic module.

[0014] Further, the eleventh and twelfth MOS transistors are MOS transistors.

[0015] Beneficial effects: The present invention uses a pre-charge module for pre-charging, reducing the logic complexity. The phase detector with this structure has a higher maximum frequency (the highest operating frequency is 9.1Ghz when the power supply voltage AVDD is 1.3V). Through feedback, the circuit reset process when the output is high is accelerated, the zero-phase difference dead zone of the phase detector is eliminated, and through pulse compensation, the charge and discharge linearity of the subsequent charge pump is optimized. Description of the Drawings

[0016] Figure 1 This is the overall structural diagram of the present invention.

[0017] Figure 2 This is the overall circuit diagram of the present invention.

[0018] Figure 3 This is the working timing simulation diagram of the high-speed linear phase detector designed by the present invention.

[0019] Figure 4 This is the transmission characteristic simulation diagram of the high-speed linear phase detector designed by the present invention. Detailed implementation manners

[0020] The accompanying drawings that form a part of the present invention are used to provide a further understanding of the present invention. The schematic embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation to the present invention.

[0021] As Figure 1 shown, a high-speed linear phase detector designed by the present invention includes a pass transistor logic module 1, a pass transistor logic module 2, an AND gate AND1, and a reset path. Among them, the input terminal of the pass transistor logic module 1 is denoted as VIN, and the output terminal of the pass transistor logic module 1 is denoted as DOWN; the input terminal of the pass transistor logic module 2 is denoted as CLKREF, and the output terminal of the pass transistor logic module 2 is denoted as UP; the two input terminals of the AND gate AND1 are respectively connected to the output terminal DOWN of the pass transistor logic module 1 and the output terminal UP of the pass transistor logic module 2, and the output terminal of the AND gate AND1 is denoted as Q7; the input terminal of the reset path is connected to the output terminal Q7 of the AND gate AND1, the two output terminals of the reset path are respectively denoted as Q1 and Q2, the output terminal Q1 of the reset path is connected to the pass transistor logic module 1, and the output terminal Q2 of the reset path is connected to the pass transistor logic module 2. When the high level of the clock arrives at the input terminal VIN of the pass transistor logic module 1, the output terminal DOWN of the pass transistor logic module 1 outputs a high level; when the high level of the clock arrives at the input terminal CLKREF of the pass transistor logic module 2, the output terminal UP of the pass transistor logic module 2 also outputs a high level; when the two input terminals UP and DOWN of the AND gate AND1 are both high levels, the output terminal Q7 of the AND gate AND1 outputs a high level, and the high level of Q7 will activate the reset path module, making the output terminals Q1 and Q2 of the reset path module become low levels, thereby respectively making the output terminal DOWN of the pass transistor logic module 1 and the output terminal UP of the pass transistor logic module 2 become low levels.

[0022] As Figure 2As shown, the sub-circuit structure adopted by the present invention, the sub-circuit structure includes a channel transistor logic module 1, a channel transistor logic module 2, an AND gate AND1 and a reset path: The channel transistor logic module 1 includes a PMOS transistor P1, an NMOS transistor N1, an inverter INV1 and an inverter INV3. Among them: the source of the PMOS transistor P1 is connected to the power supply line AVDD, the drain of P1 is connected to the input terminal of the inverter INV1, the output terminal of the inverter INV1 is connected to the drain of the NMOS transistor N1, the source of N1 is connected to the input terminal of the inverter INV3, and the gates of P1 and N1 are simultaneously connected to the input clock signal VIN. The channel transistor logic module 2 includes a PMOS transistor P2, an NMOS transistor N2, an inverter INV2 and an inverter INV4. Among them: the source of the PMOS transistor P2 is connected to AVDD, the drain of P2 is connected to the input terminal of the inverter INV2, the output terminal of the inverter INV2 is connected to the source of the NMOS transistor N2, the drain of N2 is connected to the input terminal of the inverter INV4, and the gates of P2 and N2 are simultaneously connected to the reference clock signal CLKREF. The reset path includes PMOS transistors P3, P8 and NMOS transistors N3, N4, N5, N6, N7, N8, N13, N14 and NOR gates NOR1 and NOR2. Among them: the source of the PMOS transistor P3 is connected to AVDD, the drain of P3 and the gate of the NMOS transistor N4 are simultaneously connected to the output terminal Q3 of the inverter INV1, the gate of P3 and the source of N6 are simultaneously connected to the input terminal Q2 of the inverter INV2, the source of N8 is connected to the source of N5, the gate of N5 is connected to the input clock signal VIN, the drain of N5 and the gate of P8 are simultaneously connected to the input terminal Q1 of the inverter INV1, the source of N5 is connected to the drain of N6, the gate of N6 is connected to the reference clock signal CLKREF, the sources of N3, N4, N7, N13, N14 are simultaneously connected to the ground wire AVSS, the drains of N3, N13 are simultaneously connected to the output terminal DOWN of the inverter INV3, the drains of N4, N14 are simultaneously connected to the output terminal UP of the inverter INV4, the gate of N3 and the drain of P8 are simultaneously connected to the output terminal Q4 of the inverter INV2, the drain of N7 is connected to the source of N8, the gates of N7 and N8 are simultaneously connected to the output terminal Q7 of the AND gate AND1, the two input terminals of the NOR gate NOR1 are respectively connected to VIN and CLKREF, the two input terminals of the NOR gate NOR2 are respectively connected to VIN and CLKREF, the output terminal of NOR1 is connected to the gate of N13, and the output terminal of NOR2 is connected to the gate of N14.

[0023] When the input clock signals VIN and CLKREF are at low levels, the channel transistor logic module 1 and the channel transistor logic module 2 pre-charge nodes Q1 and Q2 through PMOS transistors P1 and P2 respectively, making Q1 and Q2 go high. When the input signals VIN and CLKREF become high, the output terminal DOWN of the channel transistor logic module 1 and the output terminal UP of the channel transistor logic module 2 become high respectively, which reduces the logic complexity. When the input terminals DOWN and UP of the AND gate AND1 are both high, the output terminal Q7 of AND1 becomes high, activating the reset path to ground Q1 and Q2 to make them low. During the process of Q1 and Q2 changing from high to low, PMOS transistors P3 and P8, and NMOS transistors N3 and N4 start to work, accelerating the level conversion speed of nodes Q3 and Q4 in the channel transistor logic module 1 and the channel transistor logic module 2 through positive feedback, and finally resetting the output terminal DOWN of the channel transistor logic module 1 and the output terminal UP of the channel transistor logic module 2 to low level. This makes the signal edge steeper through feedback, accelerating the circuit reset process of the DOWN and UP outputs changing from high to low level, enabling the phase detector to have a higher maximum operating frequency. Since this circuit can work when the high levels of the input clock signals VIN and CLKREF arrive simultaneously, the zero-phase-difference dead zone of the phase detector is eliminated. Since there is a delay in the process of the high levels DOWN and UP making Q7 of the AND gate AND1 go high and performing the level reset process, there is also a delay in the DOWN and UP signals resetting from high to low level. This performs pulse compensation, making the DOWN and UP signals have a certain minimum pulse width and optimizing the charge and discharge linearity of the subsequent charge pump. NOR gates NOR1, NOR2, N13, and N14 ensure that the outputs UP and DOWN are also low when the input signals VIN and CLKREF are at low levels, and also ensure that the signals change within one clock cycle without affecting the next clock cycle.

[0024] As Figure 3 [[ID=⑤]]shown, it is a working timing simulation diagram of a high-speed linear phase detector designed by the present invention. At a working frequency of 1.25G, when the phase difference between the input clock signal VIN and the reference clock signal CLKREF is 0.65π and the input clock signal VIN lags behind the reference clock signal CLKREF, the high-speed linear phase detector correctly discriminates the phase and outputs the correct timing, and the high-level duration of the output signals UP and DOWN in the same cycle is 50.4ps.

[0025] As Figure 4 [[ID=⑩]]shown, it is a transmission characteristic simulation diagram of a high-speed linear phase detector designed by the present invention. The phase detector shows a very approximately linear response state within its input range, and the reduction of the dead zone range is also very significant. It should be noted that there seems to be an error in the numbering in the original text. The "⑤" and "⑩" in the translation are just for indicating the corresponding content in the original text where the numbering might be incorrect. You may need to check and correct it in the original source.

[0026] In summary, the channel transistor logic module adopted by the present invention performs pre-charging to reduce the logic complexity. The phase detector with this structure has a higher maximum frequency (the highest operating frequency is 9.1 GHz when the power supply voltage AVDD is 1.3 V). Through feedback, the circuit reset process when the output is at the same high level is accelerated, the zero-phase difference dead zone of the phase detector is eliminated, and through pulse compensation, the charge and discharge linearity of the subsequent charge pump is optimized.

[0027] In addition, it should be noted that the various specific technical features described in the above specific embodiments can be combined in any suitable manner without contradiction. To avoid unnecessary repetition, the present invention will not separately describe various possible combination methods.

Claims

1. A high-speed linear phase discriminator, characterized in that It includes a first-channel transistor logic module, a second-channel transistor logic module, a reset path, and an AND gate; both the first and second-channel transistor logic modules include a pre-charge module and a signal transmission module connected to each other, and the node connecting the pre-charge module and the signal transmission module is denoted as the pre-charge node. An external clock signal is input to the input terminal of the first-channel transistor logic module, and an external reference clock signal is input to the input terminal of the second-channel transistor logic module; when the external clock signal or the external reference clock signal is at a low level, the pre-charge module of the corresponding channel transistor logic module is charged; when the external clock signal or the external reference clock signal is at a high level, the clock signal is output through the signal transmission module of the corresponding channel transistor logic module. The first transistor logic module outputs a signal DOWN to the first input terminal of the AND gate, and the first transistor logic module outputs a signal UP to the second input terminal of the AND gate; the output terminal of the AND gate is connected to the reset path, and the reset path outputs a signal Q1 to the pre-charge node of the first-channel transistor logic module to reset the signal DOWN, and the reset path outputs a signal Q2 to the pre-charge node of the second-channel transistor logic module to reset the signal UP.

2. The high-speed linear phase discriminator according to claim 1, wherein The pre-charge module includes a first MOS transistor, the gate of the first MOS transistor serves as the input terminal of the corresponding channel transistor logic module, the source is connected to the power supply voltage, and the drain serves as the pre-charge node.

3. The high-speed linear phase detector according to claim 2, characterized in that, The first MOS transistor is a PMOS transistor.

4. A high-speed linear phase discriminator according to claim 1, characterized in that, The signal transmission module includes a first inverter, a second inverter, and a second MOS transistor. The input terminal of the first inverter is connected to the pre-charge node, the output terminal is connected to the drain of the second MOS transistor, the gate of the second MOS transistor is connected to the input terminal of the corresponding channel transistor logic module, the source is connected to the input terminal of the second inverter, and the output terminal of the second inverter serves as the output terminal of the corresponding channel transistor logic module.

5. The high-speed linear phase discriminator according to claim 4, wherein The second MOS transistor is an NMOS transistor.

6. The high-speed linear phase discriminator according to claim 1, characterized in that The reset path includes the third to tenth MOS transistors. The gate of the third MOS transistor is connected to the input end of the first-channel transistor logic module, the drain is connected to the pre-charge node of the first-channel transistor logic module and the gate of the eighth MOS transistor, and the third source is connected to the drain of the fourth MOS transistor and the source of the sixth MOS transistor. The source of the fourth MOS transistor is connected to the pre-charge node of the second-channel transistor logic module and the gate of the seventh MOS transistor. The gate of the fourth MOS transistor is connected to the input end of the second-channel transistor logic module. The gate of the sixth MOS transistor is connected to the gate of the fifth MOS transistor and the output end of the AND gate. The drain of the sixth MOS transistor is connected to the source of the fifth MOS transistor, and the drain of the fifth MOS transistor is grounded. The drain of the seventh MOS transistor is connected to the output end of the first inverter in the first-channel transistor logic module and the gate of the tenth MOS transistor. The source of the seventh MOS transistor is connected to the source of the eighth MOS transistor and the power supply voltage. The drain of the eighth MOS transistor is connected to the output end of the first inverter in the second-channel transistor logic module and the gate of the ninth MOS transistor. The sources of the ninth MOS transistor and the tenth MOS transistor are connected to each other and then grounded. The drain of the ninth MOS transistor is connected to the output end of the first-channel transistor logic module, and the drain of the tenth MOS transistor is connected to the output end of the second-channel transistor logic module.

7. The high-speed linear phase discriminator according to claim 6, characterized in that, The third to sixth MOS transistors, the ninth and tenth MOS transistors are all NMOS transistors, and the seventh and eighth MOS transistors are all PMOS transistors.

8. The high-speed linear phase detector according to claim 1, wherein, The reset path further includes the eleventh and twelfth MOS transistors, and the first and second NOR gates. The first input end of the first NOR gate is connected to the input end of the first-channel transistor logic module and the first input end of the second NOR gate. The second input end of the first NOR gate is connected to the second input end of the second NOR gate and the input end of the second-channel transistor logic module. The output end of the first NOR gate is connected to the gate of the eleventh MOS transistor. The source of the eleventh MOS transistor is grounded, and the drain is connected to the output end of the first-channel transistor logic module. The output end of the second NOR gate is connected to the gate of the twelfth MOS transistor. The source of the twelfth MOS transistor is grounded, and the drain of the twelfth MOS transistor is connected to the output end of the second-channel transistor logic module.

9. The high-speed linear phase detector according to claim 8, wherein The eleventh and twelfth MOS transistors are MOS transistors.

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