Silicon carbide device simulation model and simulation method thereof

Abstract

The invention discloses a silicon carbide device simulation model and a simulation method thereof. The simulation model is composed of a device gate parasitic inductor, a device gate internal resistor, a device gate collector parasitic capacitor, a device gate emitter parasitic capacitor, an electron current voltage-controlled current source, a hole current source, a device collector parasitic resistor, a device emitter parasitic inductor, a device collector parasitic inductor, a device collector emitter parasitic capacitor and a device ideal diode. During application, parameter data of the device are tested through the static analysis device and the 18kV high-voltage dynamic characteristic test platform, the measured data are input into fitting software, parameter values of the device are determined according to fitting results, and the fitting voltage range is widened, so that the model can be used for simulating the high-voltage silicon carbide device with the voltage class of 18kV and below. The technical problems that an existing silicon carbide device simulation model cannot simulate a silicon carbide device with the voltage of 6.5 kV or above and cannot meet the simulation requirement of a 18kV high-voltage silicon carbide device are solved.

Description

Technical Field

[0001] The present invention relates to the technical field of silicon carbide device simulation, and in particular to a silicon carbide device simulation model and a simulation method thereof. Background Art

[0002] Compared to traditional silicon-based materials, silicon carbide (SiC) boasts a higher dielectric breakdown field strength and simultaneously combines high blocking voltage, low on-resistance, and high switching speed and frequency. These characteristics effectively reduce the power density and losses of power devices. Currently, SiC devices include 27kV SiC IGBTs, 21kV SiC BJTs, and 15kV SiC MOSFETs. The development of SiC devices is expected to gradually replace silicon-based devices in power grid applications, simplifying the series structure of high-voltage converter valves, reducing cost and complexity, and improving device efficiency. However, due to the current immaturity of SiC chip design, chip processing, and device packaging, overall R&D is difficult, resulting in low yields and a single SiC device costing tens of times more than a silicon device. In particular, SiC devices rated above 10kV are even more expensive. 18kV SiC devices are limited to laboratory research, with a single device costing nearly one million yuan. Therefore, it's impractical to directly conduct physical experiments and circuit construction on 18kV-rated SiC devices. Damage could result in incalculable economic losses. Therefore, it's essential to establish accurate circuit models through safe dynamic and static testing. By using these models for circuit construction and simulation, we can accurately assess the device's switching transient characteristics and safe operating area, saving experimental time, protecting device assets, and shortening device development cycles.

[0003] Currently, Saber simulation software can be used to simulate silicon carbide devices below 6.5kV, but there is no simulation model above 6.5kV, which cannot meet the simulation requirements of 18kV high-voltage silicon carbide devices. Summary of the Invention

[0004] The present invention provides a silicon carbide device simulation model and a simulation method thereof, which are used to solve the technical problem that the existing silicon carbide device simulation model cannot simulate silicon carbide devices above 6.5kV and cannot meet the simulation requirements of 18kV high-voltage silicon carbide devices.

[0005] In view of this, the first aspect of the present invention provides a silicon carbide device simulation model, including device gate parasitic inductance, device gate internal resistance, device gate collector parasitic capacitance, device gate emitter parasitic capacitance, electron current voltage-controlled current source, hole current source, device collector parasitic resistance, device emitter parasitic inductance, device collector parasitic inductance, device collector emitter parasitic capacitance and device ideal body diode;

[0006] One end of the device gate parasitic inductance is the device gate connection end, the other end of the device gate parasitic inductance is connected to one end of the device gate internal resistance, the other end of the device gate internal resistance is respectively connected to one end of the device gate collector parasitic capacitance and one end of the device gate emitter parasitic capacitance, the other end of the device gate collector parasitic capacitance is respectively connected to the positive electrode of the electron current voltage-controlled current source, the positive electrode of the hole current source and one end of the device collector-emitter parasitic capacitance, the other end of the device gate-emitter parasitic capacitance is respectively connected to the negative electrode of the electron current voltage-controlled current source, the negative electrode of the hole current source, the other end of the device collector-emitter parasitic capacitance and the anode of the device ideal body diode;

[0007] One end of the device collector parasitic inductance is the device drain connection end, the other end of the device collector parasitic inductance is connected to one end of the device collector parasitic resistance, and the other end of the device collector parasitic resistance is connected to a common end of the positive electrode of the hole current source, the positive electrode of the electron current voltage-controlled current source, and one end of the device collector-emitter parasitic capacitance;

[0008] One end of the device emitter parasitic inductance is the device source connection end, the other end of the device emitter parasitic inductance is connected to the negative electrode of the hole current source, the negative electrode of the electron current voltage-controlled current source, the other end of the device collector-emitter parasitic capacitance and the common end of the anode of the device ideal body diode, and the cathode of the device ideal body diode is connected to the other end of the device collector parasitic inductance.

[0009] A second aspect of the present invention provides a simulation method applied to the silicon carbide device simulation model described in the first aspect, comprising:

[0010] Model the device gate parasitic inductance, device gate internal resistance, device gate-collector parasitic capacitance, device gate-emitter parasitic capacitance, electron current voltage-controlled current source, hole current source, device collector parasitic resistance, device emitter parasitic inductance, device collector parasitic inductance, device collector-emitter parasitic capacitance and device ideal body diode respectively;

[0011] The modeled device gate parasitic inductance, device gate internal resistance, device gate collector parasitic capacitance, device gate emitter parasitic capacitance, electron current voltage-controlled current source, hole current source, device collector parasitic resistance, device emitter parasitic inductance, device collector parasitic inductance, device collector emitter parasitic capacitance and device ideal body diode are electrically connected to obtain the silicon carbide device simulation model described in claim 1.

[0012] Optionally, the parasitic inductance of the device gate is modeled by performing electromagnetic simulation on a 3D model of the device package in electromagnetic simulation analysis software to determine the value.

[0013] Optionally, a method for modeling the device gate internal resistance is to determine a value by measuring a gate charging current peak value when the device is turned on.

[0014] Optionally, the modeling method of the device gate-collector parasitic capacitance is: measuring the capacitance value of the device gate-collector parasitic capacitance through a static analysis device, plotting the capacitance value of the device gate-collector parasitic capacitance as the voltage changes from 0 to 18 kV into a first curve, putting the first curve into a multi-physics field simulation software for fitting, and determining the capacitance value of the device gate-collector parasitic capacitance based on the fitting result.

[0015] Optionally, the modeling method of the device gate-emitter parasitic capacitance is: measuring the capacitance value of the device gate-emitter parasitic capacitance through a static analysis device, plotting the capacitance value of the device gate-emitter parasitic capacitance as the voltage changes from 0 to 18 kV into a second curve, putting the second curve into a multi-physics field simulation software for fitting, and determining the capacitance value of the device gate-collector parasitic capacitance based on the fitting results.

[0016] Optionally, the device collector parasitic resistance is modeled by measuring the steady-state resistance of the device in a double-pulse experiment using an 18kV high-voltage dynamic characteristics test platform, subtracting the steady-state resistance from the device internal resistance, and obtaining the resistance value of the device collector parasitic resistance.

[0017] Optionally, the modeling method of the device emitter parasitic inductance is: performing electromagnetic simulation in electromagnetic simulation analysis software using a 3D model of the device package to determine the value.

[0018] Optionally, the device collector parasitic inductance is modeled by performing electromagnetic simulation on a 3D model of the device package in electromagnetic simulation analysis software to determine the value.

[0019] Optionally, the modeling method of the device collector-emitter parasitic capacitance is: measuring the device collector-emitter parasitic capacitance through a static analysis device, plotting the change of the device collector-emitter parasitic capacitance value with the voltage of 0~18kV into a third curve, putting the third curve into the multi-physics field simulation software for fitting, and determining the capacitance value of the device collector-emitter parasitic capacitance based on the fitting result.

[0020] From the above technical solutions, it can be seen that the silicon carbide device simulation model provided by the present invention has the following advantages:

[0021] The silicon carbide device simulation model provided by the present invention consists of device gate parasitic inductance, device gate internal resistance, device gate collector parasitic capacitance, device gate emitter parasitic capacitance, electron current voltage-controlled current source, hole current source, device collector parasitic resistance, device emitter parasitic inductance, device collector parasitic inductance, device collector emitter parasitic capacitance and device ideal body diode. When used, the parameter data of the device are tested by a static analysis device and an 18kV high-voltage dynamic characteristics test platform, the measured data are input into the fitting software, and the values of the device parameters are determined according to the fitting results, so as to broaden the fitting voltage range, so that the model can simulate high-voltage silicon carbide devices with voltage levels of 18kV and below, thereby solving the technical problem that the existing silicon carbide device simulation model cannot simulate silicon carbide devices above 6.5kV and cannot meet the simulation requirements of 18kV high-voltage silicon carbide devices.

[0022] At the same time, the silicon carbide device simulation model provided in the present invention can achieve more accurate simulation results for parameters such as the switching transient waveform and switching loss of the silicon carbide device, which are closer to actual tests, by adjusting the parasitic capacitance model, the current source transfer characteristic curve and the output characteristic curve. This solves the technical problem that the existing silicon device model cannot accurately describe the characteristics of the silicon carbide device and has large errors. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying any creative work.

[0024] Figure 1 A current model diagram of a silicon carbide device simulation model provided in an embodiment of the present invention;

[0025] Figure 2 An output characteristic fitting curve diagram of a current source provided in an embodiment of the present invention;

[0026] Figure 3 A transfer characteristic fitting curve diagram of a current source provided in an embodiment of the present invention;

[0027] Figure 4 A parasitic capacitance characteristic fitting curve diagram provided in an embodiment of the present invention;

[0028] Figure 5 Schematic diagram of the flow of a simulation method for a silicon carbide device simulation model provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0029] In order to enable those skilled in the art to better understand the solutions of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts shall fall within the scope of protection of the present invention.

[0030] For easier understanding, see Figure 1 The present invention provides an embodiment of a silicon carbide device simulation model, including a device gate parasitic inductance 1, a device gate internal resistance 2, a device gate-collector parasitic capacitance 3, a device gate-emitter parasitic capacitance 4, an electron current voltage-controlled current source 5, a hole current source 6, a device collector parasitic resistance 7, a device emitter parasitic inductance 8, a device collector parasitic inductance 9, a device collector-emitter parasitic capacitance 10 and a device ideal body diode 11.

[0031] One end of the device gate parasitic inductance 1 is the device gate connection terminal Gate, the other end of the device gate parasitic inductance 1 is connected to one end of the device gate internal resistance 2, the other end of the device gate internal resistance 2 is respectively connected to one end of the device gate collector parasitic capacitance 3 and one end of the device gate emitter parasitic capacitance 4, the other end of the device gate collector parasitic capacitance 3 is respectively connected to the positive electrode of the electron current voltage-controlled current source 5, the positive electrode of the hole current source 6 and one end of the device collector-emitter parasitic capacitance 10, the other end of the device gate-emitter parasitic capacitance 4 is respectively connected to the negative electrode of the electron current voltage-controlled current source 5, the negative electrode of the hole current source 6, the other end of the device collector-emitter parasitic capacitance 10 and the anode of the device ideal body diode 11, and one end of the device collector parasitic inductance 9 is respectively connected to the positive electrode of the electron current voltage-controlled current source 5, the negative electrode of the hole current source 6, the other end of the device collector-emitter parasitic capacitance 10 and the anode of the device ideal body diode 11. The end is the device drain connection terminal Drain, the other end of the device collector parasitic inductance 9 is connected to one end of the device collector parasitic resistance 7, the other end of the device collector parasitic resistance 7 is connected to the common end of the positive electrode of the hole current source 6, the positive electrode of the electron current voltage-controlled current source 5 and one end of the device collector-emitter parasitic capacitance 10, one end of the device emitter parasitic inductance 8 is the device source connection terminal Source, the other end of the device emitter parasitic inductance 8 is connected to the common end of the negative electrode of the hole current source 6, the negative electrode of the electron current voltage-controlled current source 5, the other end of the device collector-emitter parasitic capacitance 10 and the anode of the device ideal body diode 11, and the cathode of the device ideal body diode 11 is connected to the other end of the device collector parasitic inductance 9.

[0032] It should be noted that the "device" mentioned in the present invention refers to a silicon carbide device. The working principle of the silicon carbide device simulation model provided in the embodiment of the present invention is:

[0033] According to the simulation model in the embodiment of the present invention, electromagnetic simulation, static power analyzer measurement, high-voltage dynamic characteristics testing, and gate charging current testing are performed on the silicon carbide device. The obtained results are subjected to data processing and curve fitting to obtain the values of each component in the simulation model and the corresponding curves. The values of each component and the corresponding curves are connected according to the proposed circuit connection method to obtain the final simulation model. This simulation model can be used in circuit simulation software to accurately simulate and calculate the various electrical parameters of high-voltage silicon carbide devices.

[0034] The silicon carbide device simulation model provided by the present invention consists of device gate parasitic inductance, device gate internal resistance, device gate collector parasitic capacitance, device gate emitter parasitic capacitance, electron current voltage-controlled current source, hole current source, device collector parasitic resistance, device emitter parasitic inductance, device collector parasitic inductance, device collector emitter parasitic capacitance and device ideal body diode. When used, the parameter data of the device are tested by a static analysis device and an 18kV high-voltage dynamic characteristics test platform, the measured data are input into the fitting software, and the values of the device parameters are determined according to the fitting results, so as to broaden the fitting voltage range, so that the model can simulate high-voltage silicon carbide devices with voltage levels of 18kV and below, thereby solving the technical problem that the existing silicon carbide device simulation model cannot simulate silicon carbide devices above 6.5kV and cannot meet the simulation requirements of 18kV high-voltage silicon carbide devices.

[0035] The silicon carbide device simulation model provided in the present invention can achieve more accurate simulation results for parameters such as the switching transient waveform and switching loss of the silicon carbide device, which are closer to actual tests, by adjusting the parasitic capacitance model, the current source transfer characteristic curve and the output characteristic curve. This solves the technical problem that the existing silicon device model cannot accurately describe the characteristics of the silicon carbide device and has large errors.

[0036] In one embodiment, the device gate parasitic inductance 1 is modeled by performing electromagnetic simulation in electromagnetic simulation analysis software using a 3D model of the device package to determine its value. Specifically, electromagnetic simulation can be performed in the Q3D module within the MAXWELL software to determine its value. The device gate parasitic inductance 1 is the line inductance introduced by connection processes such as package bonding wires in the simulation of an actual device. The establishment of the model of the device gate parasitic inductance 1 can more accurately calculate the gate switching transient voltage and the gate charge and discharge current.

[0037] In one embodiment, the device gate internal resistance 2 is modeled by measuring the peak gate charging current when the device is turned on to determine its value. The device gate internal resistance 2 represents the resistance introduced into the gate channel by semiconductor processing in simulating an actual device. Modeling the device gate internal resistance 2 allows for more accurate calculation of gate switching transient voltages and gate charge and discharge currents. This also ensures that the gate voltage and current waveforms are closer to actual measured values.

[0038] In one embodiment, the modeling method of the device gate-collector parasitic capacitance 3 is as follows: the capacitance value of the device gate-collector parasitic capacitance is measured by a static analysis device, the capacitance value of the device gate-collector parasitic capacitance is plotted as a first curve along with the change of the voltage from 0 to 18 kV, and the first curve is put into the multi-physics field simulation software for fitting. The fitting result is as follows: Figure 4 As shown, Figure 4 The Cres curve in the figure represents the device gate-collector parasitic capacitance 3, and the capacitance value of the device gate-collector parasitic capacitance is determined based on the fitting result. Specifically, the multi-physics field simulation software is Saber software. The static analysis device is a power analyzer. The device gate-collector parasitic capacitance 3 is the capacitance formed by the series connection of the oxide layer capacitance and the depletion layer capacitance in the equivalent actual device. The establishment of the device gate-collector parasitic capacitance 3 in the simulation model can more accurately reflect the voltage and current changes in the Miller platform part during the device switching transient process, making the simulation of switching loss and switching time more accurate and consistent with actual measurements.

[0039] In one embodiment, the modeling method of the device gate-emitter parasitic capacitance 4 is as follows: the capacitance value of the device gate-emitter parasitic capacitance 4 is measured by a static analysis device, the capacitance value of the device gate-emitter parasitic capacitance 4 is plotted as a second curve with the change of the voltage of 0~18kV, and the second curve is put into the multi-physics field simulation software for fitting. The fitting result is as follows: Figure 4 As shown, Figure 4 Cies in the equation represents the sum of the device gate-collector parasitic capacitance 3 and the device gate-emitter parasitic capacitance 4. The capacitance value of the device gate-collector parasitic capacitance is determined based on the fitting result. Specifically, the multi-physics simulation software is Saber software. The static analysis device is a power analyzer. The device gate-emitter parasitic capacitance 4 is the capacitance effect between the gate oxide layer and the emitter electrode in the equivalent actual device. The establishment of the device gate-emitter parasitic capacitance 4 in the simulation model can more accurately reflect the changes in the gate voltage and gate current before the gate voltage reaches the Miller platform during the device switching transient process, making the simulation of switching loss and switching time more accurate and consistent with actual measurements, while more accurately reflecting the high-frequency characteristics of the device switching process.

[0040] In one embodiment, the modeling method of the electron current voltage-controlled current source 5 and the hole current source 6 is as follows: the dynamic characteristic parameters of the electron current voltage-controlled current source 5 and the hole current source 6 are measured by a static analysis device and an 18kV high-voltage dynamic characteristic test platform, and the dynamic characteristic parameters are put into the multi-physics field simulation software for fitting, so that the dynamic characteristic parameters of the electron current voltage-controlled current source 5 and the hole current source 6 meet the preset output characteristic curve and the preset transfer characteristic curve. Specifically, the multi-physics field simulation software is Saber software. The preset output characteristic curve is as follows Figure 2 As shown, the preset transfer characteristic curve is as follows Figure 3 shown. Figure 2 and Figure 3 The result is the combined effect of electron current voltage-controlled current source 5 and hole current source 6. These two sources are mathematically coupled and cannot be measured independently. The present invention incorporates two current sources rather than a single one to better align with the device's physical principles. The static analysis device is a power analyzer. The electron current voltage-controlled current source 5 and hole current source 6 are used to jointly simulate the device's output and transfer characteristics, accurately reflecting the relationship between the current between the device's collector and emitter and the voltage between the device's gate and emitter.

[0041] In one embodiment, the device collector parasitic resistance 7 is modeled by measuring the steady-state resistance of the device in a double-pulse experiment using an 18kV high-voltage dynamic characteristics test platform, subtracting the steady-state resistance from the device internal resistance, and obtaining the resistance value of the device collector parasitic resistance 7. The device collector parasitic resistance 7 is the sum of all resistances on one side of the power loop introduced by connection processes such as package bonding wires in an equivalent actual device. Establishing a model for the device collector parasitic resistance 7 can more accurately reflect the relationship between the voltage and current flowing through the device during steady-state current flow.

[0042] In one embodiment, the modeling method of the device emitter parasitic inductance 8 is: to determine the value by performing electromagnetic simulation in the electromagnetic simulation analysis software through the 3D model of the device package. Specifically, the electromagnetic simulation can be performed in the Q3D module in the MAXWELL software to determine the value. The device emitter parasitic inductance 8 is the line inductance on the emitter side introduced by the connection process such as the package bonding wire in the simulation of the actual device. The establishment of the model of the device emitter parasitic inductance 8 can more accurately simulate the transient current waveform of the current loop where the collector and emitter are located, as well as the transient voltage oscillation and overshoot value between the gate and the emitter.

[0043] In one embodiment, the modeling method of the device collector parasitic inductance 9 is: to determine the value size by performing electromagnetic simulation in the electromagnetic simulation analysis software through the 3D model of the device package. Specifically, the electromagnetic simulation can be performed in the Q3D module in the MAXWELL software to determine the value size. The device collector parasitic inductance 9 is the line inductance on the collector side introduced by the connection process such as the package bonding wire in the simulation of the actual device. The establishment of the model of the device collector parasitic inductance 9 can more accurately simulate the transient current waveform of the current loop where the collector and emitter are located, as well as the transient voltage oscillation and overshoot value between the collector and emitter. Further, it can also make the calculation of switching loss more accurate.

[0044] In one embodiment, the modeling method of the device collector-emitter parasitic capacitance 10 is as follows: the device collector-emitter parasitic capacitance is measured by a static analysis device, the capacitance value of the device collector-emitter parasitic capacitance 10 is plotted as a third curve with the change of the voltage from 0 to 18 kV, and the third curve is put into the multi-physics simulation software for fitting. The fitting result is as follows: Figure 4 As shown, Figure 4 The Coes curve in represents the sum of the device gate collector parasitic capacitance 3 and the device collector emitter parasitic capacitance 10. The capacitance value of the device collector emitter parasitic capacitance 10 is determined based on the fitting result. Specifically, the multi-physics field simulation software is Saber software. The device collector emitter parasitic capacitance 10 is the capacitance effect between the collector and emitter of the equivalent device. The establishment of the device collector emitter parasitic capacitance 10 in the simulation model can more accurately reflect the voltage change between the collector and emitter of the device during the switching process, making the calculation of switching loss and switching time more accurate and more consistent with the actual measurement value.

[0045] It should be noted that, in the present invention, Figure 4 In the figure, Cies is used to represent the sum of the device gate-collector parasitic capacitance 3 and the device gate-emitter parasitic capacitance 4, and the Coes curve is used to represent the sum of the device gate-collector parasitic capacitance 3 and the device collector-emitter parasitic capacitance 10. This is because compared with the three parasitic capacitances of device gate-collector parasitic capacitance 3, device gate-emitter parasitic capacitance 4 and device collector-emitter parasitic capacitance 10 in the model, Cies, Coes and Cres are more widely used in practice and are values that can be directly measured by instruments. Therefore, after further calculating the parasitic capacitances in the model, Cies, Coes and Cres are obtained and compared with the measured values, which can be more intuitive and more concerned about whether the values of these three parasitic capacitances are accurate when applied.

[0046] In one embodiment, the modeling method of the device's ideal body diode 11 is as follows: the voltage and current variation curves at both ends of the device's ideal body diode 11 are measured using an 18kV high-voltage dynamic characteristics test platform, the variation curves are placed into multi-physics simulation software for fitting, and the parameters of the ideal body diode 11 are determined based on the fitting results. Specifically, the multi-physics simulation software is Saber software. The function of the device's ideal body diode 11 is to simulate the forward current characteristics of the high-voltage silicon carbide diode connected in parallel for freewheeling in the device. This characteristic has almost no effect on the device's own characteristics, but can more accurately reflect the electrical characteristics of reverse freewheeling when the device is actually used.

[0047] For easier understanding, see Figure 5 The present invention provides an embodiment of a simulation method applied to the silicon carbide device simulation model provided in the present invention, comprising:

[0048] Step 101: Model the device gate parasitic inductance, device gate internal resistance, device gate-collector parasitic capacitance, device gate-emitter parasitic capacitance, electron current voltage-controlled current source, hole current source, device collector parasitic resistance, device emitter parasitic inductance, device collector parasitic inductance, device collector-emitter parasitic capacitance, and device ideal body diode, respectively.

[0049] It should be noted that the modeling methods of the device gate parasitic inductance, device gate internal resistance, device gate-collector parasitic capacitance, device gate-emitter parasitic capacitance, electron current voltage-controlled current source, hole current source, device collector parasitic resistance, device emitter parasitic inductance, device collector parasitic inductance, device collector-emitter parasitic capacitance and device ideal body diode in the embodiments of the present invention have been described in the embodiments of the silicon carbide device simulation model provided in the present invention and will not be repeated here.

[0050] Step 102: electrically connect the modeled device gate parasitic inductance, device gate internal resistance, device gate-collector parasitic capacitance, device gate-emitter parasitic capacitance, electron current voltage-controlled current source, hole current source, device collector parasitic resistance, device emitter parasitic inductance, device collector parasitic inductance, device collector-emitter parasitic capacitance, and device ideal body diode to obtain a silicon carbide device simulation model.

[0051] It should be noted that after the device gate parasitic inductance, device gate internal resistance, device gate collector parasitic capacitance, device gate emitter parasitic capacitance, electron current voltage-controlled current source, hole current source, device collector parasitic resistance, device emitter parasitic inductance, device collector parasitic inductance, device collector-emitter parasitic capacitance and device ideal body diode are modeled, the above devices are electrically connected to obtain the silicon carbide device simulation model provided in the present invention.

[0052] The terms "first," "second," "third," and the like in the present invention are used to distinguish similar objects and are not necessarily used to describe a particular order or precedence. It should be understood that the terms used in this manner are interchangeable where appropriate, so that the embodiments of the present invention described herein can, for example, be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having," and any variations thereof, are intended to cover non-exclusive inclusions. For example, a process, method, system, product, or apparatus comprising a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0053] As described above, the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit the same. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that the technical solutions described in the above embodiments can still be modified, or some of the technical features thereof can be replaced by equivalents. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A silicon carbide device simulation model, characterized in that: Including device gate parasitic inductance, device gate internal resistance, device gate collector parasitic capacitance, device gate emitter parasitic capacitance, electron current voltage-controlled current source, hole current source, device collector parasitic resistance, device emitter parasitic inductance, device collector parasitic inductance, device collector emitter parasitic capacitance and device ideal body diode; One end of the device gate parasitic inductance is the device gate connection end, the other end of the device gate parasitic inductance is connected to one end of the device gate internal resistance, the other end of the device gate internal resistance is respectively connected to one end of the device gate collector parasitic capacitance and one end of the device gate emitter parasitic capacitance, the other end of the device gate collector parasitic capacitance is respectively connected to the positive electrode of the electron current voltage-controlled current source, the positive electrode of the hole current source and one end of the device collector-emitter parasitic capacitance, the other end of the device gate-emitter parasitic capacitance is respectively connected to the negative electrode of the electron current voltage-controlled current source, the negative electrode of the hole current source, the other end of the device collector-emitter parasitic capacitance and the anode of the device ideal body diode; One end of the device collector parasitic inductance is the device drain connection end, the other end of the device collector parasitic inductance is connected to one end of the device collector parasitic resistance, and the other end of the device collector parasitic resistance is connected to a common end of the positive electrode of the hole current source, the positive electrode of the electron current voltage-controlled current source, and one end of the device collector-emitter parasitic capacitance; One end of the device emitter parasitic inductance is the device source connection end, the other end of the device emitter parasitic inductance is connected to the negative electrode of the hole current source, the negative electrode of the electron current voltage-controlled current source, the other end of the device collector-emitter parasitic capacitance and the common end of the anode of the device ideal body diode, and the cathode of the device ideal body diode is connected to the other end of the device collector parasitic inductance.

2. A simulation method applied to the silicon carbide device simulation model according to claim 1, characterized in that: include: Model the device gate parasitic inductance, device gate internal resistance, device gate-collector parasitic capacitance, device gate-emitter parasitic capacitance, electron current voltage-controlled current source, hole current source, device collector parasitic resistance, device emitter parasitic inductance, device collector parasitic inductance, device collector-emitter parasitic capacitance and device ideal body diode respectively; The modeled device gate parasitic inductance, device gate internal resistance, device gate collector parasitic capacitance, device gate emitter parasitic capacitance, electron current voltage-controlled current source, hole current source, device collector parasitic resistance, device emitter parasitic inductance, device collector parasitic inductance, device collector emitter parasitic capacitance and device ideal body diode are electrically connected to obtain the silicon carbide device simulation model described in claim 1.

3. The simulation method according to claim 2, wherein: The modeling method of the device gate parasitic inductance is to determine the value by performing electromagnetic simulation in electromagnetic simulation analysis software using a 3D model of the device package.

4. The simulation method according to claim 2, wherein: The modeling method of the device gate internal resistance is to determine the value by measuring the gate charging current peak when the device is turned on.

5. The simulation method according to claim 2, wherein: The modeling method of the device gate-collector parasitic capacitance is: measuring the capacitance value of the device gate-collector parasitic capacitance through a static analysis device, plotting the capacitance value of the device gate-collector parasitic capacitance as a function of the voltage from 0 to 18 kV into a first curve, putting the first curve into multi-physics field simulation software for fitting, and determining the capacitance value of the device gate-collector parasitic capacitance based on the fitting result.

6. The simulation method according to claim 2, wherein: The modeling method of the device gate-emitter parasitic capacitance is as follows: the capacitance value of the device gate-emitter parasitic capacitance is measured by a static analysis device, the capacitance value of the device gate-emitter parasitic capacitance is plotted as a second curve changes with the voltage of 0~18kV, the second curve is put into multi-physics field simulation software for fitting, and the capacitance value of the device gate-collector parasitic capacitance is determined based on the fitting results.

7. The simulation method according to claim 2, wherein: The modeling method of the device collector parasitic resistance is as follows: the steady-state resistance of the device in the double-pulse experiment is measured through an 18kV high-voltage dynamic characteristics test platform, and the steady-state resistance is subtracted from the device internal resistance to obtain the resistance value of the device collector parasitic resistance.

8. The simulation method according to claim 2, wherein: The modeling method of the device emitter parasitic inductance is to determine the value by performing electromagnetic simulation in electromagnetic simulation analysis software using a 3D model of the device package.

9. The simulation method according to claim 2, wherein: The modeling method of the device collector parasitic inductance is to determine the value by performing electromagnetic simulation in electromagnetic simulation analysis software using a 3D model of the device package.

10. The simulation method according to claim 2, characterized in that: The modeling method of the device collector-emitter parasitic capacitance is as follows: the device collector-emitter parasitic capacitance is measured by a static analysis device, the capacitance value of the device collector-emitter parasitic capacitance is plotted as a function of the voltage from 0 to 18 kV into a third curve, the third curve is put into the multi-physics field simulation software for fitting, and the capacitance value of the device collector-emitter parasitic capacitance is determined based on the fitting results.

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