SiC MOSFET drive circuit

Abstract

The invention discloses a SiC MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) driving circuit, which belongs to the field of power electronics and comprises an input side preprocessing and fault detection unit, an input side logic time sequence unit, a signal isolation unit, an output side logic unit, an output side power amplification and fault detection unit, an upper tube power supply management unit and a lower tube power supply management unit, the input side preprocessing and fault detection unit is electrically connected with the input side logic time sequence unit, the input side logic time sequence unit is electrically connected with the signal isolation unit, the signal isolation unit is electrically connected with the output side logic unit, and the output side logic unit is electrically connected with the output side power amplification and fault detection unit. The input side preprocessing and fault detection unit is electrically connected with the upper tube power supply management unit and the lower tube power supply management unit at the same time. According to the invention, different negative voltage values are used for suppressing crosstalk voltage; the crosstalk voltage is prevented from exceeding the threshold voltage to cause misconduction; the negative voltage is prevented from being too low, and the diode voltage drop is improved.

Description

Technical Field

[0001] The present invention relates to the field of power electronics, and in particular to a SiC MOSFET drive circuit. Background Art

[0002] Power electronic converters, as essential devices for utilizing electrical energy, play a vital role in production and daily life. The core of power electronic converters is power semiconductor devices, which largely determine their performance. Currently, most power semiconductors are made of Si semiconductor materials, whose properties have reached their theoretical limits, becoming a bottleneck for the further development of power electronic converters. Compared to Si power devices, SiC power devices offer superior characteristics: they offer higher switching speeds, can operate at higher junction temperatures, and can simultaneously achieve high frequencies, high voltages, and high currents. These characteristics significantly enhance the performance of semiconductor power converters, achieving higher energy conversion efficiency, higher power density, and lower system costs. In power electronic converters, the control signals from the microcontroller are weak signals and cannot directly drive the power semiconductor devices. Therefore, a driver circuit is required between the microcontroller and the power semiconductor devices. The driver circuit primarily shapes and amplifies the weak control signals from the microcontroller to control the on / off of the power semiconductor devices. In the event of a fault in the power semiconductor device or its circuit, the driver circuit also transmits fault information back to the microcontroller. Therefore, the drive circuit bridges the gap between weak-current control signals and high-current power circuits, and its reliability directly impacts the overall reliability of the power electronic converter. Existing drive circuit solutions generally employ a basic architecture that isolates the input and output signals and the power supply. This means that the input and output signals are isolated via optocouplers (optical isolation) or transformers (magnetic isolation). The input and output power supplies are also completely isolated and can withstand very high isolation voltages. When a bridge topology is used in the application circuit, the drive and power supply between the upper and lower transistors of the bridge arm are also isolated from each other.

[0003] The driver circuit uses a unipolar power supply, typically using discrete components such as Zener diodes to create positive and negative voltage generation circuits between the driver circuit output and the gate-source. The use of multiple discrete components increases the complexity of the drive circuit and reduces reliability. Among these discrete components, the Zener diode is the core component for functional implementation. This diode is affected by factors such as temperature and electromagnetic interference, resulting in poor voltage level accuracy. Furthermore, during actual circuit board layout, the space occupied by multiple discrete components increases the distance between the driver circuit and the SiC MOSFET, leading to complex parasitic parameters, particularly increased stray inductance, which affects driving performance. Bipolar-specific driver chips are required to achieve both positive and negative drive pulses, resulting in high cost and limited versatility. The negative voltage limit that SiC MOSFETs can withstand between the gate and source is very limited. Using a negative drive signal during shutdown, combined with crosstalk from the bridge arm and downward spikes, can lead to negative voltage exceeding the limit, potentially causing damage. When the diode is used for freewheeling, a negative voltage drive signal is used during shutdown. Because the diode voltage drop varies with the negative voltage, this results in significant diode losses during freewheeling. Without a negative voltage, crosstalk can easily lead to false turn-on. Applying a constant negative voltage can lead to overshooting the negative voltage limit, increasing the diode voltage drop and further losses. Summary of the Invention

[0004] In view of the above problems existing in the prior art, an object of the present invention is to provide a SiC MOSFET driving circuit to solve the problems raised in the above background technology.

[0005] To achieve the above object, the present invention provides the following technical solutions:

[0006] A SiC MOSFET drive circuit includes an input-side preprocessing and fault detection unit, an input-measurement logic timing unit, a signal isolation unit, an output-side logic unit, an output-side power amplification and fault detection unit, an upper-tube power management unit, and a lower-tube power management unit; the input-side preprocessing and fault detection unit is electrically connected to the input-measurement logic timing unit, the input-measurement logic timing unit is electrically connected to the signal isolation unit, the signal isolation unit is electrically connected to the output-side logic unit, the output-side logic unit is electrically connected to the output-side power amplification and fault detection unit, and the input-side preprocessing and fault detection unit is electrically connected to both the upper-tube power management unit and the lower-tube power management unit.

[0007] As a further solution of the present invention: the input side preprocessing and fault detection unit includes a resistor R61, a capacitor C33, a resistor R51, a capacitor C27, a resistor R57, a capacitor C35, a resistor R58, a capacitor C37, a resistor R62, a capacitor C34, a resistor R54, a capacitor C30, a resistor R60, a capacitor C32, a resistor R59, a capacitor C31, a drive enable module and an input side power supply detection module;

[0008] One end of the resistor R61 in the input side preprocessing and fault detection unit is connected to the fault feedback H signal; one end of the capacitor C33 is connected to the fault feedback H signal, and the other end of the capacitor C33 is connected to the ground terminal GND0;

[0009] One end of the resistor R51 is connected to the PWMH signal; the other end of the resistor R51 is connected to one end of the capacitor C27, and the other end of the capacitor C27 is connected to the ground terminal GND0;

[0010] One end of the resistor R57 is connected to the input side fault feedback signal; one end of the capacitor C35 is connected to the input side fault feedback signal, and the other end of the capacitor C35 is connected to the ground terminal GND0;

[0011] One end of the resistor R58 is connected to the auxiliary drive enable signal through the drive enable module; the other end of the resistor R58 is connected to one end of the capacitor C37, and the other end of the capacitor C37 is connected to the ground terminal GND0;

[0012] One end of the resistor R62 is connected to the fault feedback L signal; one end of the capacitor C34 is connected to the fault feedback L signal, and the other end of the capacitor C34 is connected to the ground terminal GND0;

[0013] One end of the resistor R54 is connected to the PWML signal; the other end of the resistor R54 is connected to one end of the capacitor C30, and the other end of the capacitor C30 is connected to the ground terminal GND0;

[0014] One end of the resistor R60 is connected to the main drive enable signal through the drive enable module; the other end of the resistor R60 is connected to one end of the capacitor C32, and the other end of the capacitor C32 is connected to the ground terminal GND0;

[0015] One end of the resistor R59 is connected to the power supply signal through the input side power supply detection module; the other end of the resistor R59 is connected to one end of the capacitor C31, and the other end of the capacitor C31 is also connected to the input side ground signal and the ground terminal GND0.

[0016] As a further solution of the present invention: the input measurement logic timing unit includes a Schmitt trigger U51, a Schmitt trigger U36, a Schmitt trigger U40, a Schmitt trigger U75, a Schmitt trigger U43, a Schmitt trigger U52, a Schmitt trigger U42, a Schmitt trigger U41, a Schmitt trigger U50, a Schmitt trigger U49, an XOR gate U53, an AND gate U81, an XOR gate U74, an AND gate U73, an XOR gate U55, an AND gate U54, a delay H1, a delay H2, a delay L1, and a delay L2;

[0017] The output end of the Schmitt trigger U51 in the input test logic timing unit is connected to the other end of the resistor R61 in the input side pre-processing and fault detection unit;

[0018] The input end of the Schmitt trigger U36 is connected to the other end of the resistor R51 in the input-side preprocessing and fault detection unit; the output end of the Schmitt trigger U36 is connected to the input end of the XOR gate U53 and the first input end of the AND gate U81; the output end of the XOR gate U53 is connected to the input end of the Schmitt trigger U41;

[0019] An input terminal of the Schmitt trigger U40 is connected to an output terminal of the XOR gate U55, and an output terminal of the Schmitt trigger U40 is connected to a second input terminal of the AND gate U81;

[0020] The output end of the Schmitt trigger U75 is connected to the other end of the resistor R57 in the input-side preprocessing and fault detection unit; the input end of the Schmitt trigger U75 is connected to the output end of the XOR gate U74; the input end of the XOR gate U74 is connected to the output end of the AND gate U73, and the two input ends of the AND gate U73 are connected to the other two input ends of the AND gate U81;

[0021] The input end of the Schmitt trigger U43 is connected to the other end of the resistor R58 in the input side pre-processing and fault detection unit;

[0022] The output end of the Schmitt trigger U52 is connected to the other end of the resistor R62 in the input side pre-processing and fault detection unit;

[0023] The input end of the Schmitt trigger U42 is connected to the other end of the resistor R54 in the input side preprocessing and fault detection unit; the output end of the Schmitt trigger U42 is simultaneously connected to the input end of the XOR gate U55 and the first input end of the AND gate U54;

[0024] The output terminal of the Schmitt trigger U41 is connected to the second input terminal of the AND gate U54;

[0025] The input end of the Schmitt trigger U50 is connected to the other end of the resistor R60 in the input side preprocessing and fault detection unit; the output end of the Schmitt trigger U50 is connected to the third input end of the AND gate U54;

[0026] The input end of the Schmitt trigger U49 is connected to the other end of the resistor R59 in the input side preprocessing and fault detection unit; the output end of the Schmitt trigger U49 is connected to the fourth input end of the AND gate U54;

[0027] The first input terminal of the delay device H1 is connected to the output terminal of the AND gate U81 and the output terminal of the Schmitt trigger U43 respectively;

[0028] The second input terminal of the delay device H2 is connected to the output terminal of the AND gate U81 and the output terminal of the Schmitt trigger U43 respectively;

[0029] The first input terminal of the delay device L1 is connected to the output terminal of the AND gate U81 and the output terminal of the Schmitt trigger U43 respectively;

[0030] The second input terminal of the delay device L2 is connected to the output terminal of the AND gate U81 and the output terminal of the Schmitt trigger U43 respectively.

[0031] The third input terminal of the delay device H1 is connected to the third input terminal of the delay device H2, the third input terminal of the delay device L1, and the third input terminal of the delay device L2 at the same time.

[0032] As a further solution of the present invention: the signal isolation unit includes an encoder H1, a transformer U32, a decoder H1, an encoder H2, a transformer U33, a decoder H2, an encoder H3, a transformer U34, a decoder H3, a fault feedback encoder H, a transformer U47, a fault feedback decoder H, an encoder L1, a transformer U69, a decoder L1, an encoder L2, a transformer U68, a decoder L2, an encoder L3, a transformer U67, a decoder L3, a fault feedback encoder L, a transformer U66, and a fault feedback decoder L;

[0033] The output end of the fault feedback decoder H is connected to the input end of the Schmitt trigger U51 in the input measurement logic timing unit; the input end of the fault feedback decoder H is connected to one side of the transformer U47, and the other end of the transformer U47 is connected to the output end of the fault feedback encoder H;

[0034] The input end of the encoder H1 is connected to the output end of the AND gate U81 in the input measurement logic timing unit; the output end of the encoder H1 is connected to one side of the transformer U32, and the other end of the transformer U32 is connected to the input end of the decoder H1;

[0035] The input end of the encoder H2 is connected to the output end of the delay device H1 in the input measurement logic timing unit; the output end of the encoder H2 is connected to one side of the transformer U33, and the other end of the transformer U33 is connected to the input end of the decoder H2;

[0036] The input end of the encoder H3 is connected to the output end of the delay device H2 in the input measurement logic timing unit; the output end of the encoder H3 is connected to one side of the transformer U34, and the other end of the transformer U34 is connected to the input end of the decoder H3.

[0037] As a further solution of the present invention: the output end of the fault feedback decoder L in the signal isolation unit is connected to the input end of the Schmitt trigger U52 in the input measurement logic timing unit; the input end of the fault feedback decoder L is connected to one side of the transformer U66, and the other end of the transformer U66 is connected to the output end of the fault feedback encoder L;

[0038] The input end of the encoder L1 is connected to the output end of the AND gate U54 in the input measurement logic timing unit; the output end of the encoder L1 is connected to one side of the transformer U69, and the other end of the transformer U69 is connected to the input end of the decoder L1;

[0039] The input end of the encoder L2 is connected to the output end of the delay device L1 in the input measurement logic timing unit; the output end of the encoder L2 is connected to one side of the transformer U68, and the other end of the transformer U68 is connected to the input end of the decoder L2;

[0040] The input end of the encoder L3 is connected to the output end of the delay device L2 in the input measurement logic timing unit; the output end of the encoder L3 is connected to one side of the transformer U67, and the other end of the transformer U67 is connected to the input end of the decoder L3.

[0041] As a further solution of the present invention: the output side logic unit includes an OR gate U56, an AND gate U57, an XOR gate U60, an AND gate U62, an AND gate U59, an OR gate U65, an AND gate U64, an XOR gate U58, an AND gate U61, and an AND gate U63;

[0042] The output end of the OR gate U56 is connected to the input end of the fault feedback encoder H;

[0043] One input terminal of the AND gate U57 is connected to the output terminal of the OR gate U56, and the other input terminal of the AND gate U57 is connected to the output terminal of the decoder H1;

[0044] The input end of the XOR gate U60 is connected to the output end of the AND gate U57, and the output end of the XOR gate U60 is simultaneously connected to the first input end of the AND gate U62 and the first input end of the AND gate U59;

[0045] The second input terminal of the AND gate U62 is connected to the output terminal of the OR gate U56; the third input terminal of the AND gate U62 is connected to the output terminal of the decoder H2;

[0046] The second input terminal of the AND gate U59 is connected to the output terminal of the OR gate U56; the third input terminal of the AND gate U59 is connected to the output terminal of the decoder H3;

[0047] The output end of the OR gate U65 is connected to the input end of the fault feedback encoder L;

[0048] One input terminal of the AND gate U64 is connected to the output terminal of the OR gate U65, and the other input terminal of the AND gate U64 is connected to the output terminal of the decoder L1;

[0049] The input end of the XOR gate U58 is connected to the output end of the AND gate U64, and the output end of the XOR gate U58 is simultaneously connected to the first input end of the AND gate U61 and the first input end of the AND gate U63;

[0050] The second input terminal of the AND gate U61 is connected to the output terminal of the OR gate U65; the third input terminal of the AND gate U61 is connected to the output terminal of the decoder L2;

[0051] The second input terminal of the AND gate U63 is connected to the output terminal of the OR gate U65; the third input terminal of the AND gate U63 is connected to the output terminal of the decoder L3.

[0052] As a further solution of the present invention: the output side power amplification and fault detection unit includes an output side power supply detection H module, a desaturation detection H module, a power amplifier PA1, a power conversion switch tube Q12, a resistor R49, a power amplifier PA2, a power conversion switch tube Q11, a diode D18, a resistor R47, a power amplifier PA3, a power conversion switch tube Q13, a diode D17, a power amplifier PA4, a power conversion switch tube Q10, an output side power supply detection L module, a desaturation detection L module, a power amplifier PA5, a power conversion switch tube Q15, a resistor R55, a power amplifier PA6, a power conversion switch tube Q16, a diode D19, a resistor R56, a power amplifier PA7, a power conversion switch tube Q14, a diode D20, a power amplifier PA8, and a power conversion switch tube Q17;

[0053] One end of the output side power supply detection H module is connected to an input end of the OR gate U56, and the other end of the output side power supply detection H module is connected to the voltage VCCH;

[0054] One end of the desaturation detection H module is connected to the other input end of the OR gate U56, and the other end of the output side power supply detection H module is connected to the power supply Vdc+;

[0055] The input end of the power amplifier PA1 is connected to the output end of the AND gate U57. The output end of the power amplifier PA1 is connected to the gate of the power conversion switch tube Q12. The drain of the power conversion switch tube Q12 and the power supply end of the power amplifier PA1 are both connected to the voltage VCCH. The source of the power conversion switch tube Q12 is connected to one end of the resistor R49. The other end of the resistor R49 is connected to the gate of the MOS tube U28. The drain of the MOS tube U28 is connected to the power supply Vdc+. The source of the MOS tube U28 is connected to the ground terminal GNDH.

[0056] The input terminal of the power amplifier PA2 is connected to the output terminal of the XOR gate U60, the output terminal of the power amplifier PA2 is connected to the gate of the power conversion switch tube Q11, the source of the power conversion switch tube Q11 and the ground terminal of the power amplifier PA2 are both connected to the ground terminal GNDH; the drain of the power conversion switch tube Q11 is connected to the cathode of the diode D18, the anode of the diode D18 is connected to one end of the resistor R47, and the other end of the resistor R47 is connected to the gate of the MOS tube U28;

[0057] The input terminal of the power amplifier PA3 is connected to the output terminal of the AND gate U62, the output terminal of the power amplifier PA3 is connected to the gate of the power conversion switch tube Q13, the source of the power conversion switch tube Q13 and the power supply terminal of the power amplifier PA3 are both connected to the voltage VEEH2, the drain of the power conversion switch tube Q13 is connected to the cathode of the diode D17, and the anode of the diode D17 is connected to the gate of the MOS tube U28;

[0058] The input end of the power amplifier PA4 is connected to the output end of the AND gate U59, the output end of the power amplifier PA4 is connected to the gate of the power conversion switch tube Q10, the source of the power conversion switch tube Q10 and the power supply end of the power amplifier PA4 are both connected to the voltage VEEH3, and the drain of the power conversion switch tube Q13 is connected to the gate of the MOS tube U28.

[0059] As a further solution of the present invention: one end of the output side power supply detection L module in the output side power amplification and fault detection unit is connected to an input end of the OR gate U65, and the other end of the output side power supply detection L module is connected to the voltage VCCL;

[0060] One end of the desaturation detection L module is connected to the other input end of the OR gate U65, and the other end of the output side power supply detection L module is connected to the ground terminal GNDH;

[0061] The input end of the power amplifier PA5 is connected to the output end of the AND gate U64. The output end of the power amplifier PA5 is connected to the gate of the power conversion switch tube Q15. The drain of the power conversion switch tube Q15 and the power supply end of the power amplifier PA1 are both connected to the voltage VCCL. The source of the power conversion switch tube Q15 is connected to one end of the resistor R55. The other end of the resistor R55 is connected to the gate of the MOS tube U70. The drain of the MOS tube U70 is connected to the ground terminal GNDH. The source of the MOS tube U70 is connected to the power supply Vdc-.

[0062] The input terminal of the power amplifier PA6 is connected to the output terminal of the XOR gate U58. The output terminal of the power amplifier PA6 is connected to the gate of the power conversion switch tube Q16. The source of the power conversion switch tube Q16 and the ground terminal of the power amplifier PA2 are both connected to the ground terminal GNDL. The drain of the power conversion switch tube Q16 is connected to the cathode of the diode D19. The anode of the diode D19 is connected to one end of the resistor R56. The other end of the resistor R56 is connected to the gate of the MOS tube U70.

[0063] The input terminal of the power amplifier PA7 is connected to the output terminal of the AND gate U61, the output terminal of the power amplifier PA7 is connected to the gate of the power conversion switch tube Q14, the source of the power conversion switch tube Q14 and the power supply terminal of the power amplifier PA7 are both connected to the voltage VEEL2, the drain of the power conversion switch tube Q14 is connected to the cathode of the diode D20, and the anode of the diode D20 is connected to the gate of the MOS tube U70;

[0064] The input end of the power amplifier PA8 is connected to the output end of the AND gate U63, the output end of the power amplifier PA8 is connected to the gate of the power conversion switch tube Q17, the source of the power conversion switch tube Q17 and the power supply end of the power amplifier PA8 are both connected to the voltage VEEL3, and the drain of the power conversion switch tube Q17 is connected to the gate of the MOS tube U70.

[0065] As a further solution of the present invention: the upper tube power management unit includes an isolated DC / DC H module U71, a non-isolated DC / DC H1 module, and a non-isolated DC / DC H2 module; the upper tube power management unit provides positive voltage VCCH, negative voltage VEEH1, and negative voltage VEEH2 based on GNDH.

[0066] As a further solution of the present invention: the lower tube power management unit includes an isolated DC / DC L module U72, a non-isolated DC / DC L1 module, and a non-isolated DC / DC L2 module; the lower tube power management unit provides a positive voltage VCCL, a negative voltage VEEL1, and a negative voltage VEEL2 based on GNDL.

[0067] Compared with the prior art, the present invention has the following beneficial effects:

[0068] The present invention sets two auxiliary driving signals and different negative voltage values, and adopts different negative voltage values ​​to suppress crosstalk voltage during the process of turning on and off the upper tube; a large negative voltage is used for the crosstalk when turning on the upper tube to prevent the crosstalk voltage from exceeding the threshold voltage and misleading on; a small negative voltage is used for the crosstalk when turning off the lower tube, which prevents the crosstalk voltage from exceeding the threshold voltage and misleading on, and prevents the negative voltage from being too low; when the non-tube is turned on and off, no negative voltage is used to improve the diode voltage drop. BRIEF DESCRIPTION OF THE DRAWINGS

[0069] Figure 1 A circuit framework diagram of a SiC MOSFET drive circuit disclosed in an embodiment.

[0070] Figure 2 A driving pulse circuit diagram of a SiC MOSFET driving circuit disclosed in an embodiment.

[0071] Figure 3 This is a DCDC application embodiment in a SiC MOSFET drive circuit disclosed in an embodiment.

[0072] Figure 4 for Figure 3 Waveform diagram of DCDC embodiment.

[0073] Figure 5 This is a DCAC application example in a SiC MOSFET drive circuit disclosed in the embodiments.

[0074] Figure 6 for Figure 5 Waveform diagram of DCAC embodiment. DETAILED DESCRIPTION

[0075] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of them. All other embodiments derived by persons of ordinary skill in the art based on the embodiments of the present invention without inventive effort shall fall within the scope of protection of the present invention.

[0076] In the description of the present invention, it should be noted that, unless otherwise expressly specified or limited, the terms "mounted," "provided with," "connected," and "connected" should be understood in a broad sense; for example, they may refer to fixed connections, detachable connections, or integral connections; they may refer to mechanical connections or electrical connections; they may refer to direct connections or indirect connections via an intermediate medium; and they may refer to internal communication between two components. Those skilled in the art will understand the specific meanings of the above terms in the present invention in specific contexts.

[0077] Aiming at the problems existing in the current application of SiC MOSFET bridge-arm circuits, the designers of the present invention have, through research and design, combined with the effects of the actual application of the bridge arms in H-bridges and three-phase full-bridges, researched and designed a SiC MOSFET drive circuit and method to overcome the problems existing in the above-mentioned SiC MOSFET bridge-arm circuits.

[0078] See also Figure 1-6, a SiC MOSFET drive circuit, including an input side pre-processing and fault detection unit, an input measurement logic timing unit, a signal isolation unit, an output side logic unit, an output side power amplification and fault detection unit, an upper tube power management unit and a lower tube power management unit;

[0079] The input side preprocessing and fault detection unit is electrically connected to the input measurement logic timing unit, the input measurement logic timing unit is electrically connected to the signal isolation unit, the signal isolation unit is electrically connected to the output side logic unit, the output side logic unit is electrically connected to the output side power amplification and fault detection unit, and the input side preprocessing and fault detection unit is electrically connected to the upper tube power management unit and the lower tube power management unit at the same time.

[0080] The input side preprocessing and fault detection unit includes a resistor R61, a capacitor C33, a resistor R51, a capacitor C27, a resistor R57, a capacitor C35, a resistor R58, a capacitor C37, a resistor R62, a capacitor C34, a resistor R54, a capacitor C30, a resistor R60, a capacitor C32, a resistor R59, a capacitor C31, a drive enable module and an input side power supply detection module;

[0081] One end of the resistor R61 in the input side preprocessing and fault detection unit is connected to the fault feedback H signal; one end of the capacitor C33 is connected to the fault feedback H signal, and the other end of the capacitor C33 is connected to the ground terminal GND0;

[0082] One end of the resistor R51 is connected to the PWMH signal; the other end of the resistor R51 is connected to one end of the capacitor C27, and the other end of the capacitor C27 is connected to the ground terminal GND0;

[0083] One end of the resistor R57 is connected to the input side fault feedback signal; one end of the capacitor C35 is connected to the input side fault feedback signal, and the other end of the capacitor C35 is connected to the ground terminal GND0;

[0084] One end of the resistor R58 is connected to the auxiliary drive enable signal through the drive enable module; the other end of the resistor R58 is connected to one end of the capacitor C37, and the other end of the capacitor C37 is connected to the ground terminal GND0;

[0085] One end of the resistor R62 is connected to the fault feedback L signal; one end of the capacitor C34 is connected to the fault feedback L signal, and the other end of the capacitor C34 is connected to the ground terminal GND0;

[0086] One end of the resistor R54 is connected to the PWML signal; the other end of the resistor R54 is connected to one end of the capacitor C30, and the other end of the capacitor C30 is connected to the ground terminal GND0;

[0087] One end of the resistor R60 is connected to the main drive enable signal through the drive enable module; the other end of the resistor R60 is connected to one end of the capacitor C32, and the other end of the capacitor C32 is connected to the ground terminal GND0;

[0088] One end of the resistor R59 is connected to the power supply signal through the input side power supply detection module; the other end of the resistor R59 is connected to one end of the capacitor C31, and the other end of the capacitor C31 is connected to the input side ground signal and the ground terminal GND0;

[0089] The input-side preprocessing and fault detection unit includes the upper-side drive signal PWMH, upper-side drive fault feedback signal, lower-side drive signal PWML, lower-side drive fault feedback signal, main drive enable, auxiliary drive enable, input-side fault feedback, power supply, and input-side ground interface. It also includes input-side voltage detection and drive enable modules. RC filters are installed at the module output and interface output.

[0090] The input measurement logic timing unit includes Schmitt trigger U51, Schmitt trigger U36, Schmitt trigger U40, Schmitt trigger U75, Schmitt trigger U43, Schmitt trigger U52, Schmitt trigger U42, Schmitt trigger U41, Schmitt trigger U50, Schmitt trigger U49, XOR gate U53, AND gate U81, XOR gate U74, AND gate U73, XOR gate U55, AND gate U54, delay H1, delay H2, delay L1, and delay L2;

[0091] The output end of the Schmitt trigger U51 in the input test logic timing unit is connected to the other end of the resistor R61 in the input side pre-processing and fault detection unit;

[0092] The input end of the Schmitt trigger U36 is connected to the other end of the resistor R51 in the input-side preprocessing and fault detection unit; the output end of the Schmitt trigger U36 is connected to the input end of the XOR gate U53 and the first input end of the AND gate U81; the output end of the XOR gate U53 is connected to the input end of the Schmitt trigger U41;

[0093] An input terminal of the Schmitt trigger U40 is connected to an output terminal of the XOR gate U55, and an output terminal of the Schmitt trigger U40 is connected to a second input terminal of the AND gate U81;

[0094] The output end of the Schmitt trigger U75 is connected to the other end of the resistor R57 in the input-side preprocessing and fault detection unit; the input end of the Schmitt trigger U75 is connected to the output end of the XOR gate U74; the input end of the XOR gate U74 is connected to the output end of the AND gate U73, and the two input ends of the AND gate U73 are connected to the other two input ends of the AND gate U81;

[0095] The input end of the Schmitt trigger U43 is connected to the other end of the resistor R58 in the input side pre-processing and fault detection unit;

[0096] The output end of the Schmitt trigger U52 is connected to the other end of the resistor R62 in the input side pre-processing and fault detection unit;

[0097] The input end of the Schmitt trigger U42 is connected to the other end of the resistor R54 in the input side preprocessing and fault detection unit; the output end of the Schmitt trigger U42 is simultaneously connected to the input end of the XOR gate U55 and the first input end of the AND gate U54;

[0098] The output terminal of the Schmitt trigger U41 is connected to the second input terminal of the AND gate U54;

[0099] The input end of the Schmitt trigger U50 is connected to the other end of the resistor R60 in the input side preprocessing and fault detection unit; the output end of the Schmitt trigger U50 is connected to the third input end of the AND gate U54;

[0100] The input end of the Schmitt trigger U49 is connected to the other end of the resistor R59 in the input side preprocessing and fault detection unit; the output end of the Schmitt trigger U49 is connected to the fourth input end of the AND gate U54;

[0101] The first input terminal of the delay device H1 is connected to the output terminal of the AND gate U81 and the output terminal of the Schmitt trigger U43 respectively;

[0102] The second input terminal of the delay device H2 is connected to the output terminal of the AND gate U81 and the output terminal of the Schmitt trigger U43 respectively;

[0103] The first input terminal of the delay device L1 is connected to the output terminal of the AND gate U81 and the output terminal of the Schmitt trigger U43 respectively;

[0104] The second input terminal of the delay device L2 is connected to the output terminal of the AND gate U81 and the output terminal of the Schmitt trigger U43 respectively.

[0105] The third input terminal of the delay device H1 is connected to the third input terminal of the delay device H2, the third input terminal of the delay device L1, and the third input terminal of the delay device L2 at the same time;

[0106] Input measurement logic timing unit, each signal circuit is equipped with a Schmitt trigger. Set the PWMH and PWML signals to interlock. Set the input undervoltage and enable signal logic to be negated to form the input side fault feedback signal. Set the input undervoltage and enable signals to participate in the production logic of the main drive signals PWMH01 and PWML01. Set delay device H1 to generate the auxiliary drive signal PWMH02, and delay device H2 to generate the auxiliary drive signal PWMH03; set delay device L1 to generate the auxiliary drive signal PWML02, and delay device L2 to generate the auxiliary drive signal PWML03;

[0107] The signal isolation unit includes an encoder H1, a transformer U32, a decoder H1, an encoder H2, a transformer U33, a decoder H2, an encoder H3, a transformer U34, a decoder H3, a fault feedback encoder H, a transformer U47, a fault feedback decoder H, an encoder L1, a transformer U69, a decoder L1, an encoder L2, a transformer U68, a decoder L2, an encoder L3, a transformer U67, a decoder L3, a fault feedback encoder L, a transformer U66, and a fault feedback decoder L;

[0108] The output end of the fault feedback decoder H is connected to the input end of the Schmitt trigger U51 in the input measurement logic timing unit; the input end of the fault feedback decoder H is connected to one side of the transformer U47, and the other end of the transformer U47 is connected to the output end of the fault feedback encoder H;

[0109] The input end of the encoder H1 is connected to the output end of the AND gate U81 in the input measurement logic timing unit; the output end of the encoder H1 is connected to one side of the transformer U32, and the other end of the transformer U32 is connected to the input end of the decoder H1;

[0110] The input end of the encoder H2 is connected to the output end of the delay device H1 in the input measurement logic timing unit; the output end of the encoder H2 is connected to one side of the transformer U33, and the other end of the transformer U33 is connected to the input end of the decoder H2;

[0111] The input end of the encoder H3 is connected to the output end of the delay device H2 in the input measurement logic timing unit; the output end of the encoder H3 is connected to one side of the transformer U34, and the other end of the transformer U34 is connected to the input end of the decoder H3;

[0112] The output end of the fault feedback decoder L is connected to the input end of the Schmitt trigger U52 in the input measurement logic timing unit; the input end of the fault feedback decoder L is connected to one side of the transformer U66, and the other end of the transformer U66 is connected to the output end of the fault feedback encoder L;

[0113] The input end of the encoder L1 is connected to the output end of the AND gate U54 in the input measurement logic timing unit; the output end of the encoder L1 is connected to one side of the transformer U69, and the other end of the transformer U69 is connected to the input end of the decoder L1;

[0114] The input end of the encoder L2 is connected to the output end of the delay device L1 in the input measurement logic timing unit; the output end of the encoder L2 is connected to one side of the transformer U68, and the other end of the transformer U68 is connected to the input end of the decoder L2;

[0115] The input end of the encoder L3 is connected to the output end of the delay device L2 in the input measurement logic timing unit; the output end of the encoder L3 is connected to one side of the transformer U67, and the other end of the transformer U67 is connected to the input end of the decoder L3;

[0116] The signal isolation unit is equipped with encoder H1, transformer U32, and decoder H1 to perform signal transmission isolation for PWMH01. Encoder H2, transformer U33, and decoder H2 are equipped to perform signal transmission isolation for PWMH02. Encoder H3, transformer U34, and decoder H3 are equipped to perform signal transmission isolation for PWMH03. Fault feedback encoder H, transformer U47, and fault feedback decoder H are equipped to perform signal transmission isolation for upper tube faults. Encoder L1, transformer U69, and decoder L1 are equipped to perform signal transmission isolation for PWML01. Encoder L2, transformer U68, and decoder L2 are equipped to perform signal transmission isolation for PWML02. Encoder L3, transformer U67, and decoder L3 are equipped to perform signal transmission isolation for PWML03. Fault feedback encoder L, transformer U66, and fault feedback decoder L are equipped to perform signal transmission isolation for lower tube faults.

[0117] The output side logic unit includes OR gate U56, AND gate U57, XOR gate U60, AND gate U62, AND gate U59, OR gate U65, AND gate U64, XOR gate U58, AND gate U61, and AND gate U63;

[0118] The output end of the OR gate U56 is connected to the input end of the fault feedback encoder H;

[0119] One input terminal of the AND gate U57 is connected to the output terminal of the OR gate U56, and the other input terminal of the AND gate U57 is connected to the output terminal of the decoder H1;

[0120] The input end of the XOR gate U60 is connected to the output end of the AND gate U57, and the output end of the XOR gate U60 is simultaneously connected to the first input end of the AND gate U62 and the first input end of the AND gate U59;

[0121] The second input terminal of the AND gate U62 is connected to the output terminal of the OR gate U56; the third input terminal of the AND gate U62 is connected to the output terminal of the decoder H2;

[0122] The second input terminal of the AND gate U59 is connected to the output terminal of the OR gate U56; the third input terminal of the AND gate U59 is connected to the output terminal of the decoder H3;

[0123] The output end of the OR gate U65 is connected to the input end of the fault feedback encoder L;

[0124] One input terminal of the AND gate U64 is connected to the output terminal of the OR gate U65, and the other input terminal of the AND gate U64 is connected to the output terminal of the decoder L1;

[0125] The input end of the XOR gate U58 is connected to the output end of the AND gate U64, and the output end of the XOR gate U58 is simultaneously connected to the first input end of the AND gate U61 and the first input end of the AND gate U63;

[0126] The second input terminal of the AND gate U61 is connected to the output terminal of the OR gate U65; the third input terminal of the AND gate U61 is connected to the output terminal of the decoder L2;

[0127] The second input terminal of the AND gate U63 is connected to the output terminal of the OR gate U65; the third input terminal of the AND gate U63 is connected to the output terminal of the decoder L3;

[0128] The output-side logic unit includes an OR gate U56 to aggregate the upper tube desaturation detection H signal and the upper tube output-side power supply detection H signal. AND gates U57, U62, and U59, as well as a NOT gate U60, are provided to implement the main drive signal PWMH1's locking function with the auxiliary drive signals PWMH2 and PWMH3. An OR gate U65 is provided to aggregate the lower tube desaturation detection L signal and the lower tube output-side power supply detection L signal. AND gates U64, U61, and U63, as well as a NOT gate U58, are provided to implement the main drive signal PWML1's locking function with the auxiliary drive signals PWML2 and PWML3.

[0129] The output side power amplification and fault detection unit includes an output side power supply detection H module, a desaturation detection H module, a power amplifier PA1, a power conversion switch tube Q12, a resistor R49, a power amplifier PA2, a power conversion switch tube Q11, a diode D18, a resistor R47, a power amplifier PA3, a power conversion switch tube Q13, a diode D17, a power amplifier PA4, a power conversion switch tube Q10, an output side power supply detection L module, a desaturation detection L module, a power amplifier PA5, a power conversion switch tube Q15, a resistor R55, a power amplifier PA6, a power conversion switch tube Q16, a diode D19, a resistor R56, a power amplifier PA7, a power conversion switch tube Q14, a diode D20, a power amplifier PA8, and a power conversion switch tube Q17;

[0130] One end of the output side power supply detection H module is connected to an input end of the OR gate U56, and the other end of the output side power supply detection H module is connected to the voltage VCCH;

[0131] One end of the desaturation detection H module is connected to the other input end of the OR gate U56, and the other end of the output side power supply detection H module is connected to the power supply Vdc+;

[0132] The input end of the power amplifier PA1 is connected to the output end of the AND gate U57. The output end of the power amplifier PA1 is connected to the gate of the power conversion switch tube Q12. The drain of the power conversion switch tube Q12 and the power supply end of the power amplifier PA1 are both connected to the voltage VCCH. The source of the power conversion switch tube Q12 is connected to one end of the resistor R49. The other end of the resistor R49 is connected to the gate of the MOS tube U28. The drain of the MOS tube U28 is connected to the power supply Vdc+. The source of the MOS tube U28 is connected to the ground terminal GNDH.

[0133] The input terminal of the power amplifier PA2 is connected to the output terminal of the XOR gate U60, the output terminal of the power amplifier PA2 is connected to the gate of the power conversion switch tube Q11, the source of the power conversion switch tube Q11 and the ground terminal of the power amplifier PA2 are both connected to the ground terminal GNDH; the drain of the power conversion switch tube Q11 is connected to the cathode of the diode D18, the anode of the diode D18 is connected to one end of the resistor R47, and the other end of the resistor R47 is connected to the gate of the MOS tube U28;

[0134] The input terminal of the power amplifier PA3 is connected to the output terminal of the AND gate U62, the output terminal of the power amplifier PA3 is connected to the gate of the power conversion switch tube Q13, the source of the power conversion switch tube Q13 and the power supply terminal of the power amplifier PA3 are both connected to the voltage VEEH2, the drain of the power conversion switch tube Q13 is connected to the cathode of the diode D17, and the anode of the diode D17 is connected to the gate of the MOS tube U28;

[0135] The input terminal of the power amplifier PA4 is connected to the output terminal of the AND gate U59, the output terminal of the power amplifier PA4 is connected to the gate of the power conversion switch tube Q10, the source of the power conversion switch tube Q10 and the power supply terminal of the power amplifier PA4 are both connected to the voltage VEEH3, and the drain of the power conversion switch tube Q13 is connected to the gate of the MOS tube U28;

[0136] One end of the output side power supply detection L module is connected to an input end of the OR gate U65, and the other end of the output side power supply detection L module is connected to the voltage VCCL;

[0137] One end of the desaturation detection L module is connected to the other input end of the OR gate U65, and the other end of the output side power supply detection L module is connected to the ground terminal GNDH;

[0138] The input end of the power amplifier PA5 is connected to the output end of the AND gate U64. The output end of the power amplifier PA5 is connected to the gate of the power conversion switch tube Q15. The drain of the power conversion switch tube Q15 and the power supply end of the power amplifier PA1 are both connected to the voltage VCCL. The source of the power conversion switch tube Q15 is connected to one end of the resistor R55. The other end of the resistor R55 is connected to the gate of the MOS tube U70. The drain of the MOS tube U70 is connected to the ground terminal GNDH. The source of the MOS tube U70 is connected to the power supply Vdc-.

[0139] The input terminal of the power amplifier PA6 is connected to the output terminal of the XOR gate U58. The output terminal of the power amplifier PA6 is connected to the gate of the power conversion switch tube Q16. The source of the power conversion switch tube Q16 and the ground terminal of the power amplifier PA2 are both connected to the ground terminal GNDL. The drain of the power conversion switch tube Q16 is connected to the cathode of the diode D19. The anode of the diode D19 is connected to one end of the resistor R56. The other end of the resistor R56 is connected to the gate of the MOS tube U70.

[0140] The input terminal of the power amplifier PA7 is connected to the output terminal of the AND gate U61, the output terminal of the power amplifier PA7 is connected to the gate of the power conversion switch tube Q14, the source of the power conversion switch tube Q14 and the power supply terminal of the power amplifier PA7 are both connected to the voltage VEEL2, the drain of the power conversion switch tube Q14 is connected to the cathode of the diode D20, and the anode of the diode D20 is connected to the gate of the MOS tube U70;

[0141] The input end of the power amplifier PA8 is connected to the output end of the AND gate U63, the output end of the power amplifier PA8 is connected to the gate of the power conversion switch tube Q17, the source of the power conversion switch tube Q17 and the power supply end of the power amplifier PA8 are both connected to the voltage VEEL3, and the drain of the power conversion switch tube Q17 is connected to the gate of the MOS tube U70;

[0142] The output-side power amplification and fault detection unit is configured with power supply detection H and desaturation detection H for the top-side output tube. Each drive signal is configured for the power amplifier and power conversion switch. The voltage converted from PWMH1 to VgsH is VCCH, the voltage converted from PWMH2 to VgsH is VEEH2, and the voltage converted from PWMH3 to VgsH is VEEH3. When PWMH1, PWMH2, and PWMH3 are all low, the voltage of VgsH is GNDH. The power supply detection L and desaturation detection L for the bottom-side output tube are configured. Each drive signal is configured for the power amplifier and power conversion switch. The voltage converted from PWML1 to VgsL is VCCL, the voltage converted from PWML2 to VgsL is VEEL2, and the voltage converted from PWML3 to VgsL is VEEL3. When PWML1, PWML2, and PWML3 are all low, the voltage of VgsL is GNDL.

[0143] The upper tube power management unit includes the isolated DC / DC H module U71, the non-isolated DC / DC H1 module, and the non-isolated DC / DC H2 module; the upper tube power management unit provides the positive voltage VCCH, negative voltage VEEH1, and negative voltage VEEH2 based on GNDH;

[0144] The lower tube power management unit includes an isolated DC / DC L module U72, a non-isolated DC / DC L1 module, and a non-isolated DC / DC L2 module. The lower tube power management unit provides positive voltage VCCL, negative voltage VEEL1, and negative voltage VEEL2 based on GNDL.

[0145] The upper tube power management unit is equipped with an isolated DC / DC H to achieve isolation and power supply voltage conversion between the input and output sides, forming a voltage reference GNDH and a positive voltage VCCH; a non-isolated DC / DC H1 is set on the output side to form a negative voltage VEEH1; a non-isolated DC / DC H2 is set on the output side to form a negative voltage VEEH2.

[0146] The lower tube power management unit is equipped with an isolated DC / DC L to achieve isolation and power supply voltage conversion between the input and output sides, forming a voltage reference GNDL and a positive voltage VCCL; a non-isolated DC / DC L1 is set on the output side to form a negative voltage VEEL1; a non-isolated DC / DC L2 is set on the output side to form a negative voltage VEEL2.

[0147] The main drive enable is high (enabled) and the auxiliary drive can be low (disabled):

[0148] The main drive channel works normally. When the PWMH01 signal corresponds to PWMH1, the voltage of VgsH formed by the PWMH1 output power amplifier stage is VgsH1, the voltage value is VCCH, and the positive pulse is output normally. When the PWML01 signal corresponds to PWML1, the voltage of VgsL formed by the PWML1 output power amplifier stage is VgsL1, the voltage value is VCCL, and the positive pulse is output normally.

[0149] The auxiliary drive function is turned off. When the PWMH02 signal corresponds to PWMH2, the voltage of VgsH formed by the PWMH2 output power amplifier stage is VgsH2, and the voltage value is VEEH2, providing a constant negative voltage output; when the PWML02 signal corresponds to PWML2, the voltage of VgsL formed by the PWML2 output power amplifier stage is VgsL2, and the voltage value is VEEL2, providing a constant negative voltage output.

[0150] The main drive enable is high (enabled) and the auxiliary drive can be low (enabled):

[0151] The logic timing of the upper tube main drive signal PWMH01, and the auxiliary drive signals PWMH02 and PWMH03 are as follows:

[0152] Delay device H1, PWMH01 falling edge trigger starts timing, and the delay time Td is set to high level; PWML01 rising edge trigger starts timing, and the delay time Td is set to low level; forming PWMH02.

[0153] Delay device H2, PWMH01 rising and falling edges trigger the start timing, PWMH01 high level maintains time THw, delay time 2*THw+Td is set to high level; PWML01 falling edge triggers the start timing, delay time Td is set to low level; forming PWMH03

[0154] The logic timing of the lower tube main drive signal PWML01, and the auxiliary drive signals PWML02 and PWML03 are as follows:

[0155] Delay device L1, PWML01 falling edge trigger starts timing, and the delay time Td is set to high level; PWMH01 rising edge trigger starts timing, and the delay time Td is set to low level; forming PWML02.

[0156] Delay device L2, the rising and falling edges of PWML01 trigger the start timing, the high level of PWML01 is maintained for time TLw, and the delay time 2*TLw+Td is set to high level; the falling edge of PWMH01 triggers the start timing, and the delay time Td is set to low level; forming PWML03.

[0157] The VgsH voltage values ​​corresponding to the main drive signal and auxiliary drive signal of the upper tube are:

[0158] When the PWMH01 signal corresponds to PWMH1, the voltage of VgsH formed by the PWMH1 output power amplifier stage is VgsH1, and the voltage value is VCCH.

[0159] When the PWMH02 signal corresponds to PWMH2, the voltage of VgsH formed by the PWMH2 output power amplifier stage is VgsH2, and the voltage value is VEEH2.

[0160] When the PWMH03 signal corresponds to PWMH3, the voltage of VgsH formed by the PWMH3 output power amplifier stage is VgsH3, and the voltage value is VEEH3.

[0161] When PWMH1, PWMH2 and PWMH3 are not in effect, the voltage VgsH formed by the output power amplifier stage is GNDH, and the voltage value is zero voltage.

[0162] The VgsL voltage values ​​corresponding to the main drive signal and auxiliary drive signal of the lower tube main drive are:

[0163] When the PWML01 signal corresponds to PWML1, the voltage of VgsL formed by the PWML1 output power amplifier stage is VgsL1, and the voltage value is VCCL.

[0164] When the PWML02 signal corresponds to PWML2, the voltage of VgsL formed by the PWML2 output power amplifier stage is VgsL2, and the voltage value is VEEL2.

[0165] When the PWML03 signal corresponds to PWML3, the voltage of VgsL formed by the PWML3 output power amplifier stage is VgsL3, and the voltage value is VEEL3.

[0166] When PWML1, PWML2, and PWML3 are all inactive, the voltage of VgsL formed by the output power amplifier stage is GNDL, and the voltage value is zero voltage.

[0167] The present invention can be used in a variety of applications using bridge circuits, typically in DC / DC power supplies and DC / AC inverter power supplies. When a DC / DC power supply uses a bridge topology such as a phase-shifted full-bridge or LLC, both the main drive enable and the auxiliary drive enable are enabled. In a DC / AC inverter power supply, since the transistors are designed to conduct within half a cycle of the output AC waveform, the main drive enable must be enabled while the auxiliary drive enable must be disabled.

[0168] In the present invention, when the upper tube is turned on, the positive value of the crosstalk voltage applied to the lower tube gate is greater than the negative value; when the upper tube is turned off, the negative value of the crosstalk voltage applied to the lower tube gate is greater than the positive value. Similarly, the peak value of the crosstalk voltage applied to the upper tube gate is the same when the lower tube is turned on and off.

[0169] In the existing technology, a constant negative voltage is used. If the negative voltage is small, the positive crosstalk voltage peak may not be suppressed enough, and there is a risk of misconduction. If the negative voltage is large, after the negative crosstalk voltage peak is superimposed, the negative voltage applied to the gate may be too large, causing the gate oxide layer to age and fail faster. The negative voltage causes the diode voltage drop to increase.

[0170] The present invention sets two auxiliary driving signals and different negative voltage values, and adopts different negative voltage values ​​to suppress crosstalk voltage during the process of turning on and off the upper tube; a large negative voltage is used for the crosstalk when turning on the upper tube to prevent the crosstalk voltage from exceeding the threshold voltage and misleading on; a small negative voltage is used for the crosstalk when turning off the lower tube, which prevents the crosstalk voltage from exceeding the threshold voltage and misleading on, and prevents the negative voltage from being too low; when the non-tube is turned on and off, no negative voltage is used to improve the diode voltage drop.

[0171] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above and that the invention can be implemented in other specific forms without departing from the spirit or essential characteristics of the invention. Therefore, the embodiments should be considered in all respects as illustrative and non-limiting. The scope of the invention is defined by the appended claims, not the foregoing description, and it is intended that all variations within the meaning and range of equivalents of the claims be encompassed within the present invention, and any reference signs in the claims should not be construed as limiting the claim to which they relate.

[0172] In addition, it should be understood that although this specification is described in terms of implementation methods, not every implementation method contains only one independent technical solution. This narrative method of the specification is only for the sake of clarity. Those skilled in the art should regard the specification as a whole. The technical solutions in each embodiment can also be appropriately combined to form other implementation methods that can be understood by those skilled in the art.

Claims

1. A SiC MOSFET drive circuit, characterized in that: It includes an input side preprocessing and fault detection unit, an input measurement logic timing unit, a signal isolation unit, an output side logic unit, an output side power amplification and fault detection unit, an upper tube power management unit and a lower tube power management unit; the input side preprocessing and fault detection unit is electrically connected to the input measurement logic timing unit, the input measurement logic timing unit is electrically connected to the signal isolation unit, the signal isolation unit is electrically connected to the output side logic unit, the output side logic unit is electrically connected to the output side power amplification and fault detection unit, and the input side preprocessing and fault detection unit is electrically connected to the upper tube power management unit and the lower tube power management unit at the same time.

2. A SiC MOSFET driving circuit according to claim 1, characterized in that: The input side preprocessing and fault detection unit includes a resistor R61, a capacitor C33, a resistor R51, a capacitor C27, a resistor R57, a capacitor C35, a resistor R58, a capacitor C37, a resistor R62, a capacitor C34, a resistor R54, a capacitor C30, a resistor R60, a capacitor C32, a resistor R59, a capacitor C31, a drive enable module and an input side power supply detection module; One end of the resistor R61 in the input side preprocessing and fault detection unit is connected to the fault feedback H signal; one end of the capacitor C33 is connected to the fault feedback H signal, and the other end of the capacitor C33 is connected to the ground terminal GND0; One end of the resistor R51 is connected to the PWMH signal; the other end of the resistor R51 is connected to one end of the capacitor C27, and the other end of the capacitor C27 is connected to the ground terminal GND0; One end of the resistor R57 is connected to the input side fault feedback signal; one end of the capacitor C35 is connected to the input side fault feedback signal, and the other end of the capacitor C35 is connected to the ground terminal GND0; One end of the resistor R58 is connected to the auxiliary drive enable signal through the drive enable module; the other end of the resistor R58 is connected to one end of the capacitor C37, and the other end of the capacitor C37 is connected to the ground terminal GND0; One end of the resistor R62 is connected to the fault feedback L signal; one end of the capacitor C34 is connected to the fault feedback L signal, and the other end of the capacitor C34 is connected to the ground terminal GND0; One end of the resistor R54 is connected to the PWML signal; the other end of the resistor R54 is connected to one end of the capacitor C30, and the other end of the capacitor C30 is connected to the ground terminal GND0; One end of the resistor R60 is connected to the main drive enable signal through the drive enable module; the other end of the resistor R60 is connected to one end of the capacitor C32, and the other end of the capacitor C32 is connected to the ground terminal GND0; One end of the resistor R59 is connected to the power supply signal through the input side power supply detection module; the other end of the resistor R59 is connected to one end of the capacitor C31, and the other end of the capacitor C31 is also connected to the input side ground signal and the ground terminal GND0.

3. A SiC MOSFET driving circuit according to claim 2, characterized in that: The input measurement logic timing unit includes a Schmitt trigger U51, a Schmitt trigger U36, a Schmitt trigger U40, a Schmitt trigger U75, a Schmitt trigger U43, a Schmitt trigger U52, a Schmitt trigger U42, a Schmitt trigger U41, a Schmitt trigger U50, a Schmitt trigger U49, an XOR gate U53, an AND gate U81, an XOR gate U74, an AND gate U73, an XOR gate U55, an AND gate U54, a delay H1, a delay H2, a delay L1, and a delay L2; The output end of the Schmitt trigger U51 in the input test logic timing unit is connected to the other end of the resistor R61 in the input side pre-processing and fault detection unit; The input end of the Schmitt trigger U36 is connected to the other end of the resistor R51 in the input side pre-processing and fault detection unit; The output terminal of the Schmitt trigger U36 is connected to the input terminal of the XOR gate U53 and the first input terminal of the AND gate U81, and the output terminal of the XOR gate U53 is connected to the input terminal of the Schmitt trigger U41; An input terminal of the Schmitt trigger U40 is connected to an output terminal of the XOR gate U55, and an output terminal of the Schmitt trigger U40 is connected to a second input terminal of the AND gate U81; The output end of the Schmitt trigger U75 is connected to the other end of the resistor R57 in the input side pre-processing and fault detection unit; The input end of the Schmitt trigger U75 is connected to the output end of the XOR gate U74; the input end of the XOR gate U74 is connected to the output end of the AND gate U73, and the two input ends of the AND gate U73 are connected to the other two input ends of the AND gate U81; The input end of the Schmitt trigger U43 is connected to the other end of the resistor R58 in the input side pre-processing and fault detection unit; The output end of the Schmitt trigger U52 is connected to the other end of the resistor R62 in the input side pre-processing and fault detection unit; The input end of the Schmitt trigger U42 is connected to the other end of the resistor R54 in the input side pre-processing and fault detection unit; The output terminal of the Schmitt trigger U42 is connected to the input terminal of the XOR gate U55 and the first input terminal of the AND gate U54 at the same time; The output terminal of the Schmitt trigger U41 is connected to the second input terminal of the AND gate U54; The input end of the Schmitt trigger U50 is connected to the other end of the resistor R60 in the input side pre-processing and fault detection unit; The output terminal of the Schmitt trigger U50 is connected to the third input terminal of the AND gate U54; The input end of the Schmitt trigger U49 is connected to the other end of the resistor R59 in the input side pre-processing and fault detection unit; The output terminal of the Schmitt trigger U49 is connected to the fourth input terminal of the AND gate U54; The first input terminal of the delay device H1 is connected to the output terminal of the AND gate U81 and the output terminal of the Schmitt trigger U43 respectively; The second input terminal of the delay device H2 is connected to the output terminal of the AND gate U81 and the output terminal of the Schmitt trigger U43 respectively; The first input terminal of the delay device L1 is connected to the output terminal of the AND gate U81 and the output terminal of the Schmitt trigger U43 respectively; The second input terminal of the delay device L2 is connected to the output terminal of the AND gate U81 and the output terminal of the Schmitt trigger U43 respectively. The third input terminal of the delay device H1 is connected to the third input terminal of the delay device H2, the third input terminal of the delay device L1, and the third input terminal of the delay device L2 at the same time.

4. A SiC MOSFET driving circuit according to claim 3, characterized in that: The signal isolation unit includes an encoder H1, a transformer U32, a decoder H1, an encoder H2, a transformer U33, a decoder H2, an encoder H3, a transformer U34, a decoder H3, a fault feedback encoder H, a transformer U47, a fault feedback decoder H, an encoder L1, a transformer U69, a decoder L1, an encoder L2, a transformer U68, a decoder L2, an encoder L3, a transformer U67, a decoder L3, a fault feedback encoder L, a transformer U66, and a fault feedback decoder L; The output end of the fault feedback decoder H is connected to the input end of the Schmitt trigger U51 in the input measurement logic timing unit; The input end of the fault feedback decoder H is connected to one side of the transformer U47, and the other end of the transformer U47 is connected to the output end of the fault feedback encoder H; The input end of the encoder H1 is connected to the output end of the AND gate U81 in the input measurement logic timing unit; the output end of the encoder H1 is connected to one side of the transformer U32, and the other end of the transformer U32 is connected to the input end of the decoder H1; The input end of the encoder H2 is connected to the output end of the delay device H1 in the input measurement logic timing unit; the output end of the encoder H2 is connected to one side of the transformer U33, and the other end of the transformer U33 is connected to the input end of the decoder H2; The input end of the encoder H3 is connected to the output end of the delay device H2 in the input measurement logic timing unit; the output end of the encoder H3 is connected to one side of the transformer U34, and the other end of the transformer U34 is connected to the input end of the decoder H3.

5. A SiC MOSFET driving circuit according to claim 4, characterized in that: The output end of the fault feedback decoder L in the signal isolation unit is connected to the input end of the Schmitt trigger U52 in the input measurement logic timing unit; The input end of the fault feedback decoder L is connected to one side of the transformer U66, and the other end of the transformer U66 is connected to the output end of the fault feedback encoder L; The input end of the encoder L1 is connected to the output end of the AND gate U54 in the input measurement logic timing unit; the output end of the encoder L1 is connected to one side of the transformer U69, and the other end of the transformer U69 is connected to the input end of the decoder L1; The input end of the encoder L2 is connected to the output end of the delay device L1 in the input measurement logic timing unit; the output end of the encoder L2 is connected to one side of the transformer U68, and the other end of the transformer U68 is connected to the input end of the decoder L2; The input end of the encoder L3 is connected to the output end of the delay device L2 in the input measurement logic timing unit; the output end of the encoder L3 is connected to one side of the transformer U67, and the other end of the transformer U67 is connected to the input end of the decoder L3.

6. A SiC MOSFET driving circuit according to claim 5, characterized in that: The output side logic unit includes an OR gate U56, an AND gate U57, an XOR gate U60, an AND gate U62, an AND gate U59, an OR gate U65, an AND gate U64, an XOR gate U58, an AND gate U61, and an AND gate U63; The output end of the OR gate U56 is connected to the input end of the fault feedback encoder H; One input terminal of the AND gate U57 is connected to the output terminal of the OR gate U56, and the other input terminal of the AND gate U57 is connected to the output terminal of the decoder H1; The input end of the XOR gate U60 is connected to the output end of the AND gate U57, and the output end of the XOR gate U60 is simultaneously connected to the first input end of the AND gate U62 and the first input end of the AND gate U59; The second input terminal of the AND gate U62 is connected to the output terminal of the OR gate U56; the third input terminal of the AND gate U62 is connected to the output terminal of the decoder H2; The second input terminal of the AND gate U59 is connected to the output terminal of the OR gate U56; the third input terminal of the AND gate U59 is connected to the output terminal of the decoder H3; The output end of the OR gate U65 is connected to the input end of the fault feedback encoder L; One input terminal of the AND gate U64 is connected to the output terminal of the OR gate U65, and the other input terminal of the AND gate U64 is connected to the output terminal of the decoder L1; The input end of the XOR gate U58 is connected to the output end of the AND gate U64, and the output end of the XOR gate U58 is simultaneously connected to the first input end of the AND gate U61 and the first input end of the AND gate U63; The second input terminal of the AND gate U61 is connected to the output terminal of the OR gate U65; the third input terminal of the AND gate U61 is connected to the output terminal of the decoder L2; The second input terminal of the AND gate U63 is connected to the output terminal of the OR gate U65; the third input terminal of the AND gate U63 is connected to the output terminal of the decoder L3.

7. A SiC MOSFET driving circuit according to claim 6, characterized in that: The output side power amplification and fault detection unit includes an output side power supply detection H module, a desaturation detection H module, a power amplifier PA1, a power conversion switch tube Q12, a resistor R49, a power amplifier PA2, a power conversion switch tube Q11, a diode D18, a resistor R47, a power amplifier PA3, a power conversion switch tube Q13, a diode D17, a power amplifier PA4, a power conversion switch tube Q10, an output side power supply detection L module, a desaturation detection L module, a power amplifier PA5, a power conversion switch tube Q15, a resistor R55, a power amplifier PA6, a power conversion switch tube Q16, a diode D19, a resistor R56, a power amplifier PA7, a power conversion switch tube Q14, a diode D20, a power amplifier PA8, and a power conversion switch tube Q17; One end of the output side power supply detection H module is connected to an input end of the OR gate U56, and the other end of the output side power supply detection H module is connected to the voltage VCCH; One end of the desaturation detection H module is connected to the other input end of the OR gate U56, and the other end of the output side power supply detection H module is connected to the power supply Vdc+; The input end of the power amplifier PA1 is connected to the output end of the AND gate U57. The output end of the power amplifier PA1 is connected to the gate of the power conversion switch tube Q12. The drain of the power conversion switch tube Q12 and the power supply end of the power amplifier PA1 are both connected to the voltage VCCH. The source of the power conversion switch tube Q12 is connected to one end of the resistor R49. The other end of the resistor R49 is connected to the gate of the MOS tube U28. The drain of the MOS tube U28 is connected to the power supply Vdc+. The source of the MOS tube U28 is connected to the ground terminal GNDH. The input terminal of the power amplifier PA2 is connected to the output terminal of the XOR gate U60, the output terminal of the power amplifier PA2 is connected to the gate of the power conversion switch tube Q11, the source of the power conversion switch tube Q11 and the ground terminal of the power amplifier PA2 are both connected to the ground terminal GNDH; the drain of the power conversion switch tube Q11 is connected to the cathode of the diode D18, the anode of the diode D18 is connected to one end of the resistor R47, and the other end of the resistor R47 is connected to the gate of the MOS tube U28; The input terminal of the power amplifier PA3 is connected to the output terminal of the AND gate U62, the output terminal of the power amplifier PA3 is connected to the gate of the power conversion switch tube Q13, the source of the power conversion switch tube Q13 and the power supply terminal of the power amplifier PA3 are both connected to the voltage VEEH2, the drain of the power conversion switch tube Q13 is connected to the cathode of the diode D17, and the anode of the diode D17 is connected to the gate of the MOS tube U28; The input end of the power amplifier PA4 is connected to the output end of the AND gate U59, the output end of the power amplifier PA4 is connected to the gate of the power conversion switch tube Q10, the source of the power conversion switch tube Q10 and the power supply end of the power amplifier PA4 are both connected to the voltage VEEH3, and the drain of the power conversion switch tube Q13 is connected to the gate of the MOS tube U28.

8. The SiC MOSFET driving circuit according to claim 7, wherein: One end of the output side power supply detection L module in the output side power amplification and fault detection unit is connected to an input end of the OR gate U65, and the other end of the output side power supply detection L module is connected to the voltage VCCL; One end of the desaturation detection L module is connected to the other input end of the OR gate U65, and the other end of the output side power supply detection L module is connected to the ground terminal GNDH; The input end of the power amplifier PA5 is connected to the output end of the AND gate U64. The output end of the power amplifier PA5 is connected to the gate of the power conversion switch tube Q15. The drain of the power conversion switch tube Q15 and the power supply end of the power amplifier PA1 are both connected to the voltage VCCL. The source of the power conversion switch tube Q15 is connected to one end of the resistor R55. The other end of the resistor R55 is connected to the gate of the MOS tube U70. The drain of the MOS tube U70 is connected to the ground terminal GNDH. The source of the MOS tube U70 is connected to the power supply Vdc-. The input terminal of the power amplifier PA6 is connected to the output terminal of the XOR gate U58. The output terminal of the power amplifier PA6 is connected to the gate of the power conversion switch tube Q16. The source of the power conversion switch tube Q16 and the ground terminal of the power amplifier PA2 are both connected to the ground terminal GNDL. The drain of the power conversion switch tube Q16 is connected to the cathode of the diode D19. The anode of the diode D19 is connected to one end of the resistor R56. The other end of the resistor R56 is connected to the gate of the MOS tube U70. The input terminal of the power amplifier PA7 is connected to the output terminal of the AND gate U61, the output terminal of the power amplifier PA7 is connected to the gate of the power conversion switch tube Q14, the source of the power conversion switch tube Q14 and the power supply terminal of the power amplifier PA7 are both connected to the voltage VEEL2, the drain of the power conversion switch tube Q14 is connected to the cathode of the diode D20, and the anode of the diode D20 is connected to the gate of the MOS tube U70; The input end of the power amplifier PA8 is connected to the output end of the AND gate U63, the output end of the power amplifier PA8 is connected to the gate of the power conversion switch tube Q17, the source of the power conversion switch tube Q17 and the power supply end of the power amplifier PA8 are both connected to the voltage VEEL3, and the drain of the power conversion switch tube Q17 is connected to the gate of the MOS tube U70.

9. The SiC MOSFET driving circuit according to claim 8, wherein: The upper tube power management unit includes an isolated DC / DC H module U71, a non-isolated DC / DC H1 module, and a non-isolated DC / DC H2 module; The upper tube power management unit provides positive voltage VCCH, negative voltage VEEH1, and negative voltage VEEH2 based on GNDH.

10. The SiC MOSFET driving circuit according to claim 9, characterized in that: The lower tube power management unit includes an isolated DC / DC L module U72, a non-isolated DC / DC L1 module, and a non-isolated DC / DC L2 module; the lower tube power management unit provides positive voltage VCCL, negative voltage VEEL1, and negative voltage VEEL2 based on GNDL.

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