Embedded resistor circuit board and preparation method thereof

Abstract

The invention provides a buried resistor circuit board and a preparation method thereof. According to the resistance element, one resistance material is arranged on the dielectric layer to form the first resistance layer, and then the other resistance material is arranged on the first resistance layer to form the second resistance layer, so that the binding force of the resistance layers and the dielectric layer can be enhanced, and the surface flatness of the resistance element can be improved. The resistive layer of the resistive element is protected by using the protective film, so that the shape and the length of the resistive layer are prevented from being influenced by subsequent processes. According to the preparation method, the whole process is a dry process, a differential etching process is omitted, an alkaline etching solution does not need to be used, and the preparation method is environmentally friendly.

Description

Technical Field

[0001] The present application relates to the technical field of circuit boards, and in particular to a buried resistor circuit board and a preparation method thereof. Background Art

[0002] Currently, the industry often uses thin-film technology to manufacture embedded resistors. Thin-film technology involves using a special resistor copper foil consisting of a resistor layer and copper foil instead of ordinary copper foil for lamination. The resistor layer material is pressed between the dielectric material and the copper foil. Then, through the relevant resistor manufacturing process, a printed circuit board with embedded resistors is formed.

[0003] This method requires multiple etching steps, resulting in a complex production process. The resistor line shape is difficult to control, making it difficult to determine the resistance value of the embedded resistor. Furthermore, the thin-film resistor layer lacks adhesion to the dielectric material after hot pressing, and multiple etching and stripping processes can easily lead to hollowing or even peeling. This method also requires the use of large amounts of alkaline etching solution, which is not environmentally friendly. Summary of the Invention

[0004] In view of this, the present application proposes a buried resistor circuit board to solve at least one of the above problems.

[0005] An embodiment of the present application provides a method for preparing a buried resistor circuit board, comprising the following steps:

[0006] Disposing a first resistance layer on the dielectric layer;

[0007] sintering the dielectric layer and the first resistance layer;

[0008] A second resistance layer is provided on a surface of the first resistance layer facing away from the dielectric layer, wherein the first resistance layer and the second resistance layer constitute a resistance layer;

[0009] Disposing a protective film on the surface of the resistance layer away from the dielectric layer to obtain a resistance element;

[0010] A groove is formed in the copper-clad laminate, and the resistor element is disposed in the groove; wherein the copper-clad laminate includes a substrate layer and a copper foil layer disposed on a surface of the substrate layer, and the groove penetrates the substrate layer along the thickness direction of the copper-clad laminate; and the surface of the dielectric layer away from the resistor layer is flush with the surface of the substrate layer away from the copper foil layer;

[0011] The copper foil layer is made into a circuit layer, and the circuit layer is electrically connected to the electrodes of the resistor element to obtain the buried resistor circuit board.

[0012] In one embodiment, after the step of "disposing a second resistance layer on a surface of the first resistance layer facing away from the dielectric layer", the preparation method further comprises: disposing an electrode on the resistance layer, wherein the electrode is electrically connected to the resistance layer.

[0013] In one embodiment, the electrode is exposed from the protective film, and the electrode is electrically connected to the circuit layer.

[0014] In one embodiment, before the step of "providing a protective film on the surface of the resistor layer facing away from the dielectric layer", the preparation method further comprises: adjusting the resistance value of the resistor layer by using a laser.

[0015] In one embodiment, in the sintering step, the sintering temperature is below 90°C.

[0016] In one embodiment, before the step of "disposing a first resistance layer on the dielectric layer", the preparation method further comprises: etching the dielectric layer.

[0017] In one embodiment, the material of the second resistor layer is different from that of the first resistor layer. The material of the first resistor layer includes carbon paste, and the material of the second resistor layer includes one or more of nickel, chromium, tungsten, nickel-phosphorus alloy, and titanium-tungsten alloy.

[0018] One embodiment of the present application provides a buried resistor circuit board, comprising a substrate and a resistor element. The substrate comprises at least one base material layer and at least one circuit layer, the base material layer being provided with a groove. The resistor element is provided in the groove. The resistor element comprises a dielectric layer, a resistor layer, and a protective film, the resistor layer comprising a first resistor layer and a second resistor layer. The first resistor layer is located between the dielectric layer and the second resistor layer, and the protective film covers the resistor layer. The surface of the dielectric layer facing away from the resistor layer is flush with the surface of the base material layer facing away from the circuit layer, and the resistor layer is electrically connected to the circuit layer.

[0019] In one embodiment, an electrode is provided on the resistance layer, and the electrode electrically connects the resistance layer and the circuit layer.

[0020] In one embodiment, the material of the first resistance layer includes carbon paste, and the material of the second resistance layer includes one or more of nickel, chromium, tungsten, nickel-phosphorus alloy, and titanium-tungsten alloy.

[0021] The present application first arranges a resistor material on a dielectric layer to form a first resistor layer, and then arranges another resistor material on the first resistor layer to form a second resistor layer. This can enhance the bonding strength between the resistor layer and the dielectric layer and improve the surface flatness of the resistor element. The present application uses a protective film to protect the resistor layer of the resistor element to prevent the shape and length of the resistor layer from being affected by subsequent processes. The preparation method of the present application is an entirely dry process, eliminating the differential etching process and the need for alkaline etching solution, making it environmentally friendly. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 A cross-sectional view of a dielectric layer provided in one embodiment of the present application.

[0023] Figure 2 For Figure 1 A cross-sectional view of a first resistance layer disposed on a dielectric layer is shown.

[0024] Figure 3 For Figure 2 Cross-sectional view of a structure showing a second resistive layer disposed on a first resistive layer.

[0025] Figure 4 For Figure 3 A cross-sectional view of the structure shown with electrodes arranged thereon.

[0026] Figure 5 For Figure 4 Cross-sectional view of laser resistance trimming performed on the structure shown.

[0027] Figure 6 For Figure 5 A cross-sectional view of a resistor element obtained by providing a protective film on the structure shown.

[0028] Figure 7 A cross-sectional view of a copper clad laminate provided in accordance with one embodiment of the present application.

[0029] Figure 8 For the general Figure 6 The resistor element shown is located at Figure 7 A cross-sectional view inside a groove of the copper clad laminate shown.

[0030] Figure 9 For the general Figure 8 The cross-sectional view of an embedded resistor circuit board obtained by forming a circuit layer from the copper foil layer of the copper clad laminate in one embodiment is shown.

[0031] Description of main component symbols

[0032] Embedded resistance circuit board 100

[0033] Dielectric layer 10

[0034] Resistive layer 20

[0035] First resistance layer 21

[0036] Second resistance layer 22

[0037] Electrode 30

[0038] Protective film 40

[0039] Resistor 50

[0040] Copper Clad Laminate 60

[0041] Base material layer 61

[0042] Copper foil layer 62

[0043] Circuit layer 63

[0044] Groove 601

[0045] Base plate 70

[0046] The following specific implementation methods will further illustrate the embodiments of the present application in conjunction with the above-mentioned drawings. DETAILED DESCRIPTION

[0047] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art in the art of the present application. The terms used herein are only for the purpose of describing specific embodiments and are not intended to limit the present application.

[0048] It should be noted that all directional indications in the embodiments of the present application (such as up, down, left, right, front, back, etc.) are only used to explain the relative position relationship, movement status, etc. between the various components under a certain specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indication will also change accordingly.

[0049] It will be understood that when a layer is referred to as being "on" another layer, it can be directly on the other layer or intervening layers may be present therebetween. Conversely, when a layer is referred to as being "directly on" another layer, there are no intervening layers. When a component is referred to as being "disposed on" another component, it can be directly disposed on the other component or an intervening component may also be present.

[0050] The embodiments of the present application are described herein with reference to cross-sectional views, which are schematic diagrams of idealized embodiments (and intermediate configurations) of the present application. Thus, it is foreseeable that the shapes of the diagrams may differ due to manufacturing processes and / or tolerances. Therefore, the embodiments of the present application should not be interpreted as being limited to the specific shapes of the regions illustrated herein, but should include deviations in shapes, such as those resulting from manufacturing. The regions shown in the figures are merely schematic, and their shapes are not intended to represent the actual shapes of the illustrated devices and are not intended to limit the scope of the present application.

[0051] The following describes some embodiments of the present application in detail with reference to the accompanying drawings. In the absence of conflict, the following embodiments and features of the embodiments may be combined with each other.

[0052] See also Figures 1 to 9 In a first aspect, the present application provides a method for preparing a buried resistor circuit board 100, which includes steps S10 to S60. It is understood that the numbering of the steps is intended to clarify the specific preparation method, and does not limit the order of the steps.

[0053] Step S10, see Figure 1 and Figure 2 , a first resistance layer 21 is provided on the dielectric layer 10 .

[0054] In some embodiments, the dielectric layer 10 may be, but is not limited to, one or more flexible materials such as polyimide (PI), polyethylene terephthalate (PET), polyethylene naphthalate diformic acid glycol ester (PEN), polyethylene (PE), Teflon (Teflon), liquid crystal polymer (LCP), polyvinyl chloride (PVC), or rigid materials such as fiberglass board.

[0055] In some embodiments, dielectric layer 10 may be pretreated before first resistive layer 21 is provided. This pretreatment may include, but is not limited to, etching. Dielectric layer 10 may be micro-etched using an organic solvent to increase the surface roughness of dielectric layer 10, thereby improving the bonding strength between dielectric layer 10 and the subsequently provided first resistive layer 21. In some embodiments, pretreatment may be omitted.

[0056] In some embodiments, the first resistive layer 21 can be disposed on the dielectric layer 10 by, but not limited to, printing. The first resistive layer 21 can cover a portion of the surface of the dielectric layer 10. The material of the first resistive layer 21 can be, but is not limited to, carbon paste (also known as carbon slurry, conductive carbon oil, or conductive carbon slurry). Carbon paste is increasingly used as conductors, resistors, and contact points in circuit board production. Carbon paste primarily includes ink, glue, and solvents.

[0057] In step S20 , please continue to refer to step 2 , the dielectric layer 10 and the first resistor layer 21 are sintered.

[0058] The sintering step must be performed at a low temperature, below 90°C (≤90°C). Low-temperature sintering allows the solvent in the first resistor layer 21 (carbon paste) to slowly evaporate. If the temperature is too high, holes will form in the first resistor layer 21, affecting the resistance value.

[0059] After sintering, the first resistor layer 21 can be subjected to a heat shock at 288°C for 10 seconds, repeated three times. The first resistor layer 21 is then observed for deformation and bubbles. If the first resistor layer 21 maintains its shape and has no bubbles, the sintering step is complete. If the first resistor layer 21 deforms or has bubbles, it indicates that the sintering process was not complete and the first resistor layer 21 needs to be sintered again.

[0060] After sintering, the surface of the first resistor layer 21 is uneven. In this embodiment, the surface roughness Ra of the first resistor layer 21 after sintering is measured by Safcom 550A and is 5.5 μm (cut value 0.8 mm, reference length 2.5 mm).

[0061] Step S30, see Figure 3 A second resistor layer 22 is provided on the surface of the first resistor layer 21 facing away from the dielectric layer 10. The first resistor layer 21 and the second resistor layer 22 constitute the resistor layer 20, and the material of the second resistor layer 22 is different from that of the first resistor layer 21.

[0062] In some embodiments, the second resistor layer 22 may be formed by, but not limited to, sputtering. Along the thickness direction, the orthographic projection of the second resistor layer 22 on the dielectric layer 10 completely overlaps with the orthographic projection of the first resistor layer 21 on the dielectric layer 10.

[0063] In some embodiments, the material of the second resistance layer 22 may be, but is not limited to, one or more of nickel, chromium, tungsten, nickel-phosphorus alloy, and titanium-tungsten alloy.

[0064] See also Figure 4 In some embodiments, after step S30 , step S31 may be further performed: disposing an electrode 30 on the resistance layer 20 so that the electrode 30 is electrically connected to the resistance layer 20 .

[0065] In some embodiments, the electrode 30 may be disposed on the resistor layer 20 by sputtering. Figure 4 As shown, the electrode 30 may cover the side surfaces of the first resistive layer 21 and the second resistive layer 22, and cover a portion of the top surface of the second resistive layer 22 (the surface of the second resistive layer 22 facing away from the first resistive layer 21). The electrode 30 may be, but is not limited to, copper.

[0066] See also Figure 5 In some embodiments, after step S31, step S32 may be performed: adjusting the resistance of the resistor layer 20 using a laser. The laser may ablate the second resistor layer 22 to remove a portion of the second resistor layer 22, thereby adjusting the thickness, shape, etc. of the resistor layer 20 to obtain a resistor layer 20 with a desired resistance value.

[0067] In some embodiments, step S32 “adjusting the resistance of the resistor layer 20 using a laser” may be performed first, and then step S31 “arranging the electrode 30 on the resistor layer 20” may be performed. This application does not limit this.

[0068] In some embodiments, when the resistance value of the resistor layer 20 does not need to be further adjusted, step S32 of “adjusting the resistance value of the resistor layer 20 using a laser” may be omitted.

[0069] Step S40, see Figure 6 A protective film 40 is provided on the surface of the resistor layer 20 facing away from the dielectric layer 10 to obtain a resistor element 50. The protective film 40 protects the resistor layer 20 from being affected by subsequent manufacturing processes, thereby maintaining the linear shape of the resistor layer 20.

[0070] In some embodiments, the protective film 40 can be provided on the surface of the resistor layer 20 facing away from the dielectric layer 10 by lamination. Figure 6 As shown, in addition to covering the surface of the resistor layer 20 exposed from the electrode 30, the protective film 40 may also cover the surface of the dielectric layer 10 not covered by the resistor layer 20 and the electrode 30. The surface of the electrode 30 facing away from the dielectric layer 10 is not covered by the protective film 40, and the surface of the electrode 30 facing away from the dielectric layer 10 may be flush with the surface of the protective film 40 facing away from the dielectric layer 10. The protective film 40 may be, but is not limited to, a flexible printed circuit (FPC) cover film, also known as a CVL (cover-layer).

[0071] Step S50, see Figure 7 and Figure 8 , a groove 601 is formed on the copper clad plate 60 , and the resistor element 50 is disposed in the groove 601 .

[0072] like Figure 7As shown, a copper-clad laminate 60 includes a substrate layer 61 and a copper foil layer 62 disposed on a surface of the substrate layer 61. In this embodiment, the copper-clad laminate 60 is a single-sided copper-clad laminate, with the copper foil layer 62 disposed only on one surface of the substrate layer 61. In some embodiments, a groove 601 can be formed in the copper-clad laminate by, but not limited to, laser drilling or mechanical drilling. The groove 601 extends through the substrate layer 61 along the thickness of the copper-clad laminate 60. The sidewalls of the groove 601 are the substrate layer 61, and the bottom wall is the copper foil layer 62. Part of the surface of the copper foil layer 62 may be exposed from the groove 601.

[0073] In some embodiments, the material of the substrate layer 61 may be, but is not limited to, hard or flexible insulating materials such as polyimide, polyethylene terephthalate, polyethylene naphthalate, polydimethylsiloxane, liquid crystal polymer, and modified polyimide.

[0074] like Figure 8 As shown, the resistor element 50 is disposed within the recess 601, with the resistor layer 20 facing downward (and the dielectric layer 10 positioned above the resistor layer 20). The dimensions of the recess 601 can be adapted to those of the resistor element 50, allowing the resistor element 50 to be precisely embedded within the recess 601. The surface of the dielectric layer 10 facing away from the resistor layer 20 can be flush with the surface of the substrate layer 61 facing away from the copper foil layer 62. Compared to the dielectric layer 10, the resistor layer 20 is closer to the copper foil layer 62. The electrode 30 and the protective film 40 can contact the copper foil layer 62. The electrode 30 can be connected to the surface of the copper foil layer 62 near the substrate layer 61 by welding, thereby achieving electrical continuity between the electrode 30 and the copper foil layer 62.

[0075] Step S60, see Figure 9 The copper foil layer 62 is made into a circuit layer 63, and the circuit layer 63 is electrically connected to the electrode 30 of the resistor element 50 to obtain the buried resistor circuit board 100.

[0076] In some embodiments, the circuit layer 63 can be formed by steps such as lamination, exposure, development, etching, and film stripping. The lamination, exposure, development, etching, and film stripping steps are commonly used technical means in the field and will not be repeated here.

[0077] In some embodiments, additional layers can be added to the side of the circuit layer 63 facing away from the substrate layer 61. For example, a copper-clad laminate (not shown) can be laminated to the side of the circuit layer 63 facing away from the substrate layer 61, with the substrate layer of the copper-clad laminate positioned between the circuit layer 63 and the copper foil layer of the copper-clad laminate. The outer copper foil layer can then be fabricated to form the circuit layer. The above steps can be repeated multiple times to form a buried circuit board with more circuit layers 63.

[0078] See also Figure 9 In a second aspect, the present application provides a buried resistor circuit board 100 prepared by the above-mentioned preparation method, which includes a substrate 70 and a resistor element 50.

[0079] The substrate 70 includes at least one base material layer 61 and at least one circuit layer 63. It is understood that when the substrate 70 includes multiple circuit layers 63, a base material layer 61 is provided between two adjacent circuit layers 63. Figure 9 As shown, substrate 70 includes only one base layer 61 and one circuit layer 63. Base layer 61 is provided with a groove 601. When substrate 70 includes multiple base layers 61, groove 601 is formed in the outermost base layer 61. Groove 601 penetrates base layer 61 along the thickness direction, with its sidewalls formed by base layer 61 and its bottom wall formed by circuit layer 63.

[0080] Resistor element 50 is disposed in recess 601. Resistor element 50 includes a dielectric layer 10, a resistor layer 20, and a protective film 40. Resistor layer 20 includes a first resistor layer 21 and a second resistor layer 22 made of different materials. First resistor layer 21 is located between dielectric layer 10 and second resistor layer 22. Protective film 40 covers resistor layer 20. Compared to dielectric layer 10, resistor layer 20 is closer to circuit layer 63 and is electrically connected to circuit layer 63.

[0081] In some embodiments, an electrode 30 is provided on the resistor layer 20, and the resistor layer 20 and the circuit layer 63 are electrically connected via the electrode 30. The electrode 30 may cover the side surfaces of the first resistor layer 21 and the second resistor layer 22, and may also cover a portion of the surface of the second resistor layer 22 facing away from the first resistor layer 21. The electrode 30 may be made of, but is not limited to, copper.

[0082] In some embodiments, dielectric layer 10 may be made of, but not limited to, one or more flexible materials such as PI, PET, PEN, PE, Teflon, LCP, PVC, or rigid materials such as fiberglass. The material of first resistor layer 21 may be, but not limited to, carbon paste. The material of second resistor layer 22 may be, but not limited to, one or more of nickel, chromium, tungsten, nickel-phosphorus alloy, or titanium-tungsten alloy. Protective film 40 may be, but not limited to, CVL.

[0083] The present application first arranges a resistor material on the dielectric layer 10 to form a first resistor layer 21, and then arranges another resistor material on the first resistor layer 21 to form a second resistor layer 22. This can enhance the bonding strength between the resistor layer 20 and the dielectric layer 10, and can also improve the flatness of the surface of the resistor element 50. The present application also uses a protective film 40 to protect the resistor layer 20 of the resistor element 50 to prevent the shape and length of the resistor layer 20 from being affected by subsequent processes. The preparation method of the present application is a dry process throughout, eliminating the differential etching process (in the prior art, a differential etching process is required between the resistor layer and the copper conductive circuit formed by etching respectively), and does not require the use of alkaline etching solution, which is environmentally friendly.

[0084] The above description is some specific implementation methods of the present application, but in actual application, it is not limited to these implementation methods. For ordinary technicians in this field, other variations and changes made according to the technical concept of the present application should fall within the scope of protection of the present application.

Claims

1. A method for preparing a buried resistor circuit board, characterized in that: The steps include: Disposing a first resistance layer on the dielectric layer; sintering the dielectric layer and the first resistance layer; A second resistance layer is provided on a surface of the first resistance layer facing away from the dielectric layer, wherein the first resistance layer and the second resistance layer constitute a resistance layer; Disposing a protective film on the surface of the resistance layer away from the dielectric layer to obtain a resistance element; A groove is formed in the copper-clad laminate, and the resistor element is disposed in the groove; wherein the copper-clad laminate includes a substrate layer and a copper foil layer disposed on a surface of the substrate layer, and the groove penetrates the substrate layer along the thickness direction of the copper-clad laminate; and the surface of the dielectric layer away from the resistor layer is flush with the surface of the substrate layer away from the copper foil layer; The copper foil layer is made into a circuit layer, and the circuit layer is electrically connected to the resistor layer to obtain the buried resistor circuit board.

2. The method for preparing a buried resistor circuit board according to claim 1, wherein: After the step of "arranging a second resistance layer on a surface of the first resistance layer facing away from the dielectric layer", the preparation method further includes: arranging an electrode on the resistance layer, wherein the electrode is electrically connected to the resistance layer.

3. The method for preparing a buried resistor circuit board according to claim 2, wherein: The electrode is exposed from the protective film, and the electrode is electrically connected to the circuit layer.

4. The method for preparing a buried resistor circuit board according to claim 1, wherein: Before the step of "providing a protective film on the surface of the resistance layer facing away from the dielectric layer", the preparation method further includes: adjusting the resistance value of the resistance layer by using a laser.

5. The method for preparing a buried resistor circuit board according to claim 1, wherein: In the sintering step, the sintering temperature is below 90°C.

6. The method for preparing a buried resistor circuit board according to claim 1, wherein: Before the step of "arranging a first resistance layer on the dielectric layer", the preparation method further includes: etching the dielectric layer.

7. The method for preparing a buried resistor circuit board according to claim 1, wherein: The material of the second resistance layer is different from that of the first resistance layer. The material of the first resistance layer includes carbon paste, and the material of the second resistance layer includes one or more of nickel, chromium, tungsten, nickel-phosphorus alloy, and titanium-tungsten alloy.

8. A buried resistor circuit board, characterized in that: include: A substrate comprising at least one base material layer and at least one circuit layer, wherein the base material layer is provided with a groove; and A resistor element is provided in the groove, the resistor element comprising a dielectric layer, a resistor layer and a protective film, the resistor layer comprising a first resistor layer and a second resistor layer, the first resistor layer being located between the dielectric layer and the second resistor layer, and the protective film covering the resistor layer; the surface of the dielectric layer away from the resistor layer is flush with the surface of the substrate layer away from the circuit layer, and the resistor layer is electrically connected to the circuit layer.

9. The embedded resistor circuit board according to claim 8, wherein: Electrodes are provided on the resistance layer, and the electrodes electrically connect the resistance layer and the circuit layer.

10. The embedded resistor circuit board according to claim 8, wherein: The material of the first resistance layer includes carbon paste, and the material of the second resistance layer includes one or more of nickel, chromium, tungsten, nickel-phosphorus alloy, and titanium-tungsten alloy.

Images