Integer frequency signal generating circuit and generating method of microprocessor

Abstract

The present invention relates to the field of pulse signal generation and discloses a microprocessor integer frequency signal generation circuit and generation method, comprising a flip register, a frequency division register, a counter, a frequency signal flip module, an integer frequency calculation unit, and a delay unit; the integer frequency calculation unit is configured to calculate the delay level of the fractional portion of the frequency division value when an enable signal 1 is valid and send the delay level to the delay unit; the delay unit is configured to delay the frequency signal output by the frequency signal flip module by less than one clock cycle based on the delay level sent by the integer frequency calculation unit and output the integer frequency signal. The integer frequency signal output circuit disclosed in the present invention automatically changes the frequency division value and delay level of the frequency division register through the integer calculation module and the delay level calculation module. The delay level controls a 256-to-1 selector to select the frequency signal output of the corresponding delay module in the delay unit, thereby achieving the generation of the integer frequency signal.

Description

Technical Field

[0001] The present invention relates to the field of pulse signal generation, and in particular to an integer frequency signal generating circuit and a generating method for a microprocessor. Background Art

[0002] Integer frequency signals are often required in power electronic equipment systems. For example, in test and measurement instruments, integer frequency signals are used to generate baseband signals to meet various testing requirements. Integer frequency signals are also used in various situations requiring precise frequency control, such as precise timing and frequency standards.

[0003] In existing technology, the duty cycle of the frequency signal output by the device's microprocessor is related to the division value of the toggle register. The frequency of the frequency signal is achieved by configuring the division value of the division register. Counters operate on a series of regular pulse signals (called clocks), so the frequency signal's frequency changes in clock units. However, microprocessor clock frequencies typically range from tens to hundreds of MHz, falling short of the GHz standard. Therefore, achieving picosecond (ps) frequency signal changes is unrealistic. For example, if the microprocessor operates at a 100 MHz clock with a 10 nanosecond period, achieving a 175 kHz frequency signal requires a division value of 571.428. While the integer portion can be achieved by configuring the division register, the fractional portion cannot be achieved because each increment in the division register represents an additional count by the counter, and the fractional portion represents less than a clock cycle. Therefore, it is impossible to output arbitrary integer frequency signals. Summary of the Invention

[0004] To solve the above technical problems, the present invention provides an integer frequency signal generating circuit and generating method for a microprocessor, so as to achieve the purpose of outputting any integer frequency signal.

[0005] To achieve the above object, the technical solution of the present invention is as follows:

[0006] A microprocessor integer frequency signal generating circuit includes a flip register, a frequency division register, a counter, a frequency signal flip module, an integer frequency calculation unit and a delay unit;

[0007] The flip register is used to control the duty cycle of the frequency signal, allowing the user to configure its frequency division value;

[0008] The frequency division register is used for integer frequency division of the frequency signal, and the user configures its frequency division value. When the frequency division value calculated by the user contains a decimal, the integer part of the frequency division value is configured into the frequency division register, 1 / 2 of the integer part of the frequency division value is configured into the flip register, and the decimal part of the frequency division value is converted into hexadecimal and configured into the integer frequency calculation unit;

[0009] The counter is used to generate an enable signal. When the count value of the counter is equal to the frequency division value of the flip register, the enable signal 1 is output to the frequency signal flip module and the integer frequency calculation unit. When the count value of the counter is equal to the frequency division value of the frequency division register, the enable signal 2 is output to the frequency signal flip module.

[0010] The frequency signal flip module is used to generate a frequency signal. When the enable signal 1 is valid, the frequency signal flip module outputs a high-level pulse to the frequency signal. When the enable signal 2 is valid, the frequency signal flip module outputs a low-level pulse to the frequency signal.

[0011] The integer frequency calculation unit is used to calculate the delay level of the fractional part of the frequency division value when the enable signal 1 is valid, and send it to the delay unit;

[0012] The delay unit is used to delay the frequency signal output by the frequency signal inversion module by less than one clock cycle according to the delay level sent by the integer frequency calculation unit, and output an integer frequency signal.

[0013] In the above solution, the integer frequency calculation unit includes a decimal register, an integer calculation module and a delay series calculation module;

[0014] The decimal register is used to receive the decimal part of the frequency division value configured by the user and output it to the integer calculation module;

[0015] The integer calculation module is used to receive the frequency division value sent by the decimal register. When the enable signal 1 is valid, the fractional delay number of the frequency signal is calculated, and the calculated fractional delay number is compared with 256. When the fractional delay number is less than 256, it is directly output to the delay series calculation module; when the fractional delay number is greater than 256, the output configuration is enabled to the frequency division register, the frequency division value of the frequency division register is added by 1 on the basis of the current value, and the fractional delay number remaining after subtracting 256 from the fractional delay number is output to the delay series calculation module;

[0016] The delay series calculation module is used to calculate the decimal delay number output by the integer calculation module to obtain the delay series and send it to the delay unit.

[0017] In the above solution, the delay unit includes 256 delay modules connected in series and a 256-to-1 selector;

[0018] The delay module is used to delay the frequency signal. The input of the first delay module is the frequency signal generated by the frequency signal flip module. The input of the i-th delay module is A i , the output is Z i , the output of each delay module enters the next level delay module and 256 to 1 selector simultaneously;

[0019] The 256 to 1 selector is used to select the frequency signal of a delay module to be output according to the delay series sent by the integer frequency calculation unit, that is, to obtain an integer frequency signal. When the delay series is x, the output Z of the xth delay module is output. x Output, that is, integer frequency signal is Z x .

[0020] A method for generating an integer frequency signal for a microprocessor, using the above-mentioned integer frequency signal generating circuit for a microprocessor, comprises the following steps:

[0021] Step 1. The user calculates the frequency division value according to the frequency signal to be implemented, allocates the integer part of the frequency division value to the frequency division register, allocates 1 / 2 of the integer part of the frequency division value to the flip register, and converts the decimal part of the frequency division value into hexadecimal and allocates it to the decimal register;

[0022] Step 2: The counter starts counting. When the count value of the counter is equal to the frequency division value of the flip register, the enable signal 1 is output. When the count value of the counter is equal to the frequency division value of the frequency division register, the enable signal 2 is output.

[0023] Step 3: When the frequency signal flip module receives the enable signal, it generates a frequency signal. When the enable signal 1 is valid, the frequency signal flip module outputs a high-level pulse. When the enable signal 2 is valid, the frequency signal flip module outputs a low-level pulse.

[0024] Step 4. When the enable signal 1 is valid, the integer calculation module starts to calculate the fractional delay number and compares it with 256. When the fractional delay number is less than 256, it is directly output to the delay series calculation module; when the fractional delay number is greater than 256, the output configuration is enabled to the frequency divider register, the frequency divider value of the frequency divider register is added by 1 on the basis of the current value, and the fractional delay number minus 256 is output to the delay series calculation module.

[0025] Step 5: The delay series calculation module calculates the delay series according to the fractional delay number and sends it to the delay unit;

[0026] Step 6: After receiving the delay level, the 256-to-1 selector in the delay unit selects the frequency signal of the corresponding delay module for output, thereby obtaining an integer frequency signal.

[0027] In a further technical solution, in step 1, the hexadecimal conversion formula is as follows:

[0028] F=M×256;

[0029] Where F is the frequency division value configured by the fractional register, and M is the fractional part of the frequency division value calculated by the user.

[0030] In a further technical solution, in step 4, the calculation formula of the fractional delay number is as follows:

[0031] D=D+F;

[0032] Where D is the fractional delay number, and F is the frequency division value configured by the fractional register.

[0033] In a further technical solution, in step 5, the calculation formula for the delay level is as follows:

[0034] N=(D×S+128)÷256;

[0035] Where N is the delay level, D is the fractional delay number, and S is the step size, that is, the delay of the delay modules in one clock cycle.

[0036] S=W / P;

[0037] Where W is the clock period and P is the delay of the delay module.

[0038] Through the above technical solution, the present invention provides a microprocessor integer frequency signal generating circuit and generating method, which have the following beneficial effects:

[0039] The integer frequency signal output circuit disclosed in the present invention automatically changes the frequency division value and delay series of the frequency division register through the integer calculation module and the delay series calculation module of the integer frequency calculation unit, under the premise that the user does not change the frequency division value of the flip register, the frequency division register and the decimal register. The delay series controls the 256-to-1 selector in the delay unit to select the frequency signal output of the corresponding delay module in the delay unit, thereby realizing the generation of the integer frequency signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for describing the embodiments or the prior art.

[0041] Figure 1 This is a schematic diagram of an integer frequency signal generating circuit for a microprocessor disclosed in an embodiment of the present invention.

[0042] Figure 2 Figure 3 is the specific process of generating an integer frequency signal. (a) is the counting process of the counter, (b) is the generation process of enable signal 1 and enable signal 2, (c) is the generation process of the frequency signal, and (d) is the generation process of the integer frequency signal. DETAILED DESCRIPTION

[0043] The technical solutions in the embodiments of the present invention will be described clearly and completely below with reference to the accompanying drawings in the embodiments of the present invention.

[0044] The present invention provides a microprocessor integer frequency signal generating circuit, such as Figure 1 As shown, it includes a flip register, a frequency division register, a counter, a frequency signal flip module, an integer frequency calculation unit and a delay unit; the functions of each unit are as follows:

[0045] 1. Flip register

[0046] The flip register is used to control the duty cycle of the frequency signal, allowing the user to configure its frequency division value;

[0047] Duty cycle = division value of the flip register / division value of the division register. In order to achieve a frequency signal duty cycle of 50%, the division value of the flip register is 1 / 2 of the division value of the division register.

[0048] 2. Frequency division register

[0049] The frequency divider register is used for integer division of a frequency signal, allowing the user to configure the division value. The counter operates based on a clock. The division value equals the clock frequency divided by the integer frequency of the implemented frequency signal. When the user-calculated division value contains a decimal, the integer portion of the division value is allocated to the frequency divider register, half of the integer portion of the division value is allocated to the rollover register, and the decimal portion of the division value is converted to hexadecimal and allocated to the integer frequency calculation unit.

[0050] 3. Counter

[0051] The counter is used to generate an enable signal. When the counter's count value is equal to the frequency division value of the flip register, the enable signal 1 is output to the frequency signal flip module and the integer frequency calculation unit. When the counter's count value is equal to the frequency division value of the frequency division register, the enable signal 2 is output to the frequency signal flip module.

[0052] 4. Frequency signal flip module

[0053] The frequency signal flip module is used to generate the frequency signal. When the enable signal 1 is valid, the frequency signal flip module outputs a high-level pulse of the frequency signal. When the enable signal 2 is valid, the frequency signal flip module outputs a low-level pulse of the frequency signal.

[0054] 5. Integer frequency calculation unit

[0055] The integer frequency calculation unit is used to calculate the delay level of the fractional part of the frequency division value when the enable signal 1 is valid, and send it to the delay unit.

[0056] The integer frequency calculation unit includes a decimal register, an integer calculation module and a delay series calculation module.

[0057] (1) Decimal register

[0058] The decimal register receives the decimal portion of the user-configured frequency division value and outputs it to the integer calculation module. Since the decimal portion of the frequency division value cannot be configured into the decimal register, it needs to be converted into a hexadecimal integer before configuration.

[0059] The formula for hexadecimal conversion is as follows:

[0060] F=M×256;

[0061] Where F is the frequency division value configured by the fractional register, and M is the fractional part of the frequency division value calculated by the user.

[0062] (2) Integer calculation module

[0063] The integer calculation module is used to receive the frequency division value sent by the decimal register. When the enable signal 1 is valid, it calculates the fractional delay of the frequency signal. The calculation formula of the fractional delay is as follows:

[0064] D=D+F;

[0065] Where D is the fractional delay number, and F is the frequency division value configured by the fractional register.

[0066] When the fractional delay number D is calculated, it is compared with 256. When D < 256, D is directly output to the delay series calculation module. When D > 256, it means that D already has an integer part. At this time, two operations are required: the first part outputs the configuration enable to the frequency divider register, and adds 1 to the frequency divider value of the frequency divider register based on the current value. The second part calculates D'=D-256 and outputs D' to the delay series calculation module.

[0067] The reason for comparing D with 256 here is that the decimal part of the frequency division value is converted to hexadecimal. For example, the decimal part M of the frequency division value calculated by the user is 0.4, and the frequency division value F configured by the decimal register is 0.4×256=102, D=D+102. When D is accumulated for the first time, D=102, and the corresponding M=0.4. When D is accumulated for the second time, D=204, and the corresponding M=0.8. For the first two accumulations, D is less than 256, and the corresponding M is less than 1, so D is directly output to the delay series calculation module. When D is accumulated for the third time, D=306, and the corresponding M=1.2. At this time, D is greater than 256, and the corresponding M is greater than 1, so there is an integer part. At this time, the integer part needs to be accumulated to the frequency division register, and the remaining decimal part is output to the delay series calculation module.

[0068] The reason for accumulation here is that each cycle of the frequency signal generated by the frequency signal flip module must be delayed by the frequency division value F of the decimal register. If accumulation is not performed, only the first cycle of the frequency signal generated by the frequency signal flip module will be delayed to meet the integer frequency.

[0069] (3) Delay series calculation module

[0070] The delay series calculation module is used to calculate the decimal delay number output by the integer calculation module to obtain the delay series and send it to the delay unit.

[0071] The calculation formula of the delay level is as follows:

[0072] N=(D×S+128)÷256;

[0073] Where N is the delay level, D is the fractional delay number, and S is the step size, that is, the delay of the delay modules in one clock cycle.

[0074] S=W / P;

[0075] Where W is the clock period and P is the delay of the delay module.

[0076] 128 represents rounding, and dividing by 256 means shifting the calculated value right by 8 bits, ignoring the lower 8 bits and not participating in the delay calculation.

[0077] 6. Delay unit

[0078] The delay unit is used to delay the frequency signal output by the frequency signal inversion module by less than one clock cycle according to the delay level sent by the integer frequency calculation unit, and output an integer frequency signal.

[0079] The delay unit includes 256 delay modules connected in series and a 256-to-1 selector.

[0080] (1) Delay module

[0081] The delay module is used to delay the frequency signal. The input of the first delay module is the frequency signal generated by the frequency signal flip module. The input of the i-th delay module is A i , the output is Z i The output of each delay module enters the next level delay module and the 256 to 1 selector at the same time.

[0082] The input of the delay module is A, and the output is Z. The inputs of the 256 delay modules are A1, A2, ...A 256 , the outputs are Z1, Z2, ...Z 256For example, if the delay of the delay module is 160ps, Z is the frequency signal output after A is delayed by 160ps. 256 delay modules are connected in series, that is, the frequency signal output Z of the previous delay module is the frequency signal input A of the current delay module, and the frequency signal output Z of the current delay module is the frequency signal input A of the next delay module.

[0083] (2) 256-to-1 selector

[0084] The 256-to-1 selector is used to select the frequency signal of a delay module to be output according to the delay series sent by the integer frequency calculation unit, that is, to obtain the integer frequency signal. When the delay series is x, the output Z of the xth delay module is output. x Output, that is, integer frequency signal is Z x .

[0085] The input of the 256-to-1 selector is the frequency signal output Z of the 256 delay modules. After the delay level N, the frequency signal of one delay module B among the 256 delay modules is selected and output, that is, the integer frequency signal. The relationship is as follows:

[0086] When N=1, the integer frequency signal is the frequency signal output of the first delay module, that is, Z1;

[0087] When N=2, the integer frequency signal is the frequency signal output of the second delay module, namely Z2;

[0088] When N=255, the integer frequency signal is the frequency signal output of the 255th delay module, that is, Z 255 ;

[0089] When N=256, the integer frequency signal is the frequency signal output of the 256th delay module, that is, Z 256 .

[0090] A method for generating an integer frequency signal for a microprocessor, using the above-mentioned integer frequency signal generating circuit for a microprocessor, comprises the following steps:

[0091] Step 1. The user calculates the frequency division value according to the frequency signal to be implemented, allocates the integer part of the frequency division value to the frequency division register, allocates 1 / 2 of the integer part of the frequency division value to the flip register, and converts the decimal part of the frequency division value into hexadecimal and allocates it to the decimal register;

[0092] Step 2: The counter starts counting. When the count value of the counter is equal to the frequency division value of the flip register, the enable signal 1 is output. When the count value of the counter is equal to the frequency division value of the frequency division register, the enable signal 2 is output.

[0093] Step 3: When the frequency signal flip module receives the enable signal, it generates a frequency signal. When the enable signal 1 is valid, the frequency signal flip module outputs a high-level pulse. When the enable signal 2 is valid, the frequency signal flip module outputs a low-level pulse.

[0094] Step 4. When the enable signal 1 is valid, the integer calculation module starts to calculate the fractional delay number and compares it with 256. When the fractional delay number is less than 256, it is directly output to the delay series calculation module; when the fractional delay number is greater than 256, the output configuration is enabled to the frequency divider register, the frequency divider value of the frequency divider register is added by 1 on the basis of the current value, and the fractional delay number minus 256 is output to the delay series calculation module.

[0095] Step 5: The delay series calculation module calculates the delay series according to the fractional delay number and sends it to the delay unit;

[0096] Step 6: After receiving the delay level, the 256-to-1 selector in the delay unit selects the frequency signal of the corresponding delay module for output, thereby obtaining an integer frequency signal.

[0097] For example, the clock frequency is 100 MHz, the period is 10 ns, the delay of the delay module in the delay unit is 160 ps, ​​and there are 256 delay modules in the delay unit, that is, 256 levels of delay. The user wants to achieve an integer frequency signal output of 175 kHz. The working process is as follows:

[0098] 1. The user calculates the frequency division value = 100Mhz / 175Khz = 571.428 based on the integer frequency to be achieved;

[0099] Step size S = 10ns / 160ps = 62;

[0100] Based on the calculated division value, the user configures the division value of the division register to 571 and the division value of the flip register to 285. Convert the decimal part 0.428 to hexadecimal, 0.428 × 256 = 109, and configure the division value F of the decimal register to 109.

[0101] 2. The counter starts counting. When the counter value is equal to 285, the enable signal 1 is valid and the integer calculation module starts working to calculate the decimal delay number D:

[0102] D=D+109;

[0103] The fractional delay number D is accumulated and compared with 256. After the first and second accumulations, the accumulated values ​​of D are 109 and 218, respectively, both less than 256. At this time, D is directly output to the delay count calculation module. After the third accumulation, the accumulated value of D is 327, which is greater than 256. At this time, two operations are required. The first part outputs the configuration enable and adds 1 to the current value of the frequency divider register. The second part uses the following formula to calculate the fractional delay number D':

[0104] D'=D-256;

[0105] That is, 327-256=71, and 71 is output to the delay series calculation module.

[0106] 3. The decimal delay number D or D' is input to the delay series calculation module, which calculates the delay series N according to the following formula:

[0107] N=(D×S+128)÷256;

[0108] When the enable signal 1 is valid for the first and second time, that is, after D is accumulated for the first and second time, the value of D is 109 and 218 respectively, both less than 256. When the enable signal 1 is valid for the third time, the value of D is 327, which is greater than 256. At this time, two operations are required. The first part adds 1 to the value of the divider register to become 572, and the second part is the fractional delay number D' which is 327-256=71.

[0109] According to the formula, the delay counts N of these three accumulations are 26, 53 and 17 respectively.

[0110] When N=26, the integer frequency signal is the output of the frequency signal of the 26th delay module, that is, the delay is 4.16ns;

[0111] When N=53, the integer frequency signal is the output of the frequency signal of the 53rd delay module, that is, the delay is 8.48ns;

[0112] When N=17, the integer frequency signal is the output of the frequency signal of the 17th delay module, that is, the delay is 2.72ns, but the division value of the division register is increased by 1, and the total delay is 12.72ns.

[0113] The delay changes from 4.16ns to 8.48ns and then to 12.72ns. The difference between each two delays is about 4.16ns, which can realize the output of integer frequency signals.

[0114] like Figure 2As shown, the frequency signal period is 5710ns, and the frequency signal frequency is 1 / 5710ns=175.13Khz. After the delay unit delay, the first period of the integer frequency signal is 5710+4.16=5714.16ns, the second period is 5710+8.48-4.16=5714.32ns, and the third period is 5710+12.72-8.48=5720+2.72-8.48=5714.24ns. Each period is about 5714.16ns, that is, the integer frequency signal frequency is 1 / 5714.16ns=175Khz. Therefore, after the user calculates the frequency division value and configures the flip register, frequency register and decimal register respectively, it starts, from Figure 2 As can be seen from (a), during the counting process of the counter, when the counter value is equal to the frequency division value of the frequency division register, it is automatically cleared and restarts counting; Figure 2 As can be seen from (b), when the counter count value is equal to the frequency division value of the flip register, the enable signal 1 is valid, and when the counter count value is equal to the frequency division value of the frequency division register, the enable signal 2 is valid; Figure 2 It can be seen from (c) that when the enable signal 1 is valid, the frequency signal outputs a high-level pulse, and when the enable signal 2 is valid, the frequency signal outputs a low-level pulse; Figure 2 As can be seen in (d), when the enable signal 1 is valid, the integer frequency signal is output with a delay compared to the frequency signal. The delay time of the integer frequency signal will not change until the next time the enable signal 1 is valid.

[0115] The above description of the disclosed embodiments is intended to enable one skilled in the art to implement or use the present invention. Various modifications to these embodiments will be readily apparent to one skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention is not limited to the embodiments shown herein but is intended to conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A microprocessor integer frequency signal generating circuit, characterized in that: It includes a flip register, a frequency division register, a counter, a frequency signal flip module, an integer frequency calculation unit and a delay unit; The flip register is used to control the duty cycle of the frequency signal, allowing the user to configure its frequency division value; The frequency division register is used for integer frequency division of the frequency signal, and the user configures its frequency division value. When the frequency division value calculated by the user contains a decimal, the integer part of the frequency division value is configured into the frequency division register, 1 / 2 of the integer part of the frequency division value is configured into the flip register, and the decimal part of the frequency division value is converted into hexadecimal and configured into the integer frequency calculation unit; The counter is used to generate an enable signal. When the count value of the counter is equal to the frequency division value of the flip register, the enable signal 1 is output to the frequency signal flip module and the integer frequency calculation unit. When the count value of the counter is equal to the frequency division value of the frequency division register, the enable signal 2 is output to the frequency signal flip module. The frequency signal flip module is used to generate a frequency signal. When the enable signal 1 is valid, the frequency signal flip module outputs a high-level pulse to the frequency signal. When the enable signal 2 is valid, the frequency signal flip module outputs a low-level pulse to the frequency signal. The integer frequency calculation unit is used to calculate the delay level of the fractional part of the frequency division value when the enable signal 1 is valid, and send it to the delay unit; The delay unit is used to delay the frequency signal output by the frequency signal inversion module by less than one clock cycle according to the delay level sent by the integer frequency calculation unit, and output an integer frequency signal.

2. The integer frequency signal generating circuit of a microprocessor according to claim 1, characterized in that: The integer frequency calculation unit includes a decimal register, an integer calculation module and a delay series calculation module; The decimal register is used to receive the decimal part of the frequency division value configured by the user and output it to the integer calculation module; The integer calculation module is used to receive the frequency division value sent by the decimal register. When the enable signal 1 is valid, the fractional delay number of the frequency signal is calculated, and the calculated fractional delay number is compared with 256. When the fractional delay number is less than 256, it is directly output to the delay series calculation module; when the fractional delay number is greater than 256, the output configuration is enabled to the frequency division register, the frequency division value of the frequency division register is added by 1 on the basis of the current value, and the fractional delay number remaining after subtracting 256 from the fractional delay number is output to the delay series calculation module; The delay series calculation module is used to calculate the decimal delay number output by the integer calculation module to obtain the delay series and send it to the delay unit.

3. The integer frequency signal generating circuit of a microprocessor according to claim 1, characterized in that: The delay unit includes 256 delay modules connected in series and a 256-to-1 selector; The delay module is used to delay the frequency signal. The input of the first delay module is the frequency signal generated by the frequency signal flip module. The input of the i-th delay module is A i , the output is Z i , the output of each delay module enters the next level delay module and 256 to 1 selector simultaneously; The 256 to 1 selector is used to select the frequency signal of a delay module to be output according to the delay series sent by the integer frequency calculation unit, that is, to obtain an integer frequency signal. When the delay series is x, the output Z of the xth delay module is output. x Output, that is, integer frequency signal is Z x .

4. A method for generating an integer frequency signal for a microprocessor, using the integer frequency signal generating circuit for a microprocessor according to any one of claims 1 to 3, characterized in that: The steps include: Step 1. The user calculates the frequency division value according to the frequency signal to be implemented, allocates the integer part of the frequency division value to the frequency division register, allocates 1 / 2 of the integer part of the frequency division value to the flip register, and converts the decimal part of the frequency division value into hexadecimal and allocates it to the decimal register; Step 2: The counter starts counting. When the count value of the counter is equal to the frequency division value of the flip register, the enable signal 1 is output. When the count value of the counter is equal to the frequency division value of the frequency division register, the enable signal 2 is output. Step 3: When the frequency signal flip module receives the enable signal, it generates a frequency signal. When the enable signal 1 is valid, the frequency signal flip module outputs a high-level pulse. When the enable signal 2 is valid, the frequency signal flip module outputs a low-level pulse. Step 4. When the enable signal 1 is valid, the integer calculation module starts to calculate the fractional delay number and compares it with 256. When the fractional delay number is less than 256, it is directly output to the delay series calculation module; when the fractional delay number is greater than 256, the output configuration is enabled to the frequency divider register, the frequency divider value of the frequency divider register is added by 1 on the basis of the current value, and the fractional delay number minus 256 is output to the delay series calculation module. Step 5: The delay series calculation module calculates the delay series according to the fractional delay number and sends it to the delay unit; Step 6: After receiving the delay level, the 256-to-1 selector in the delay unit selects the frequency signal of the corresponding delay module for output, thereby obtaining an integer frequency signal.

5. The method for generating an integer frequency signal of a microprocessor according to claim 4, wherein: In step 1, the hexadecimal conversion formula is as follows: F=M×256; Where F is the frequency division value configured by the fractional register, and M is the fractional part of the frequency division value calculated by the user.

6. The method for generating an integer frequency signal of a microprocessor according to claim 4, wherein: In step 4, the calculation formula of the fractional delay number is as follows: D=D+F; Where D is the fractional delay number, and F is the frequency division value configured by the fractional register.

7. The method for generating an integer frequency signal of a microprocessor according to claim 4, wherein: In step 5, the calculation formula for the delay level is as follows: N=(D×S+128)÷256; Where N is the delay level, D is the fractional delay number, and S is the step size, that is, the delay of the delay modules in one clock cycle. S=W / P; Where W is the clock period and P is the delay of the delay module.

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