Probe card simulation method, device, medium and program product

Abstract

The invention discloses a simulation method and device of a probe card, a medium and a program product, and relates to the technical field of semiconductor testing, the simulation method of the probe card comprises the steps that a simulation model of each substructure in a plurality of substructures contained in the probe card is constructed, parameterization setting is conducted on the simulation model of each substructure, and the simulation model of each substructure is obtained; the method comprises the following steps: setting link configuration information among parameterized substructure simulation models to obtain a simulation template file, and carrying out simulation test based on an input actual parameter value of a probe card and the simulation template file, so that potential risks existing in design can be found in time according to a simulation test result, the number of times of repeated modification of the design is reduced, and the design efficiency is improved. Product design quality is improved, and product development progress is accelerated. Besides, by constructing the parameterized simulation model, the constructed simulation model can be reused to products of the same type, repeated model creation and link establishment are not needed, time and labor cost are saved, and efficiency is improved.

Description

Technical Field

[0001] The present application relates to the field of semiconductor testing technology, and in particular to a simulation method, device, medium, and program product of a probe card. Background Art

[0002] In the field of probe card products, as a key component connecting the test machine and the chip to be tested, the design of the probe card is extremely complex. Specifically, a large number of networks need to be connected in the circuit design of the probe card, which makes planning difficult. At the same time, the printed circuit board of the probe card has many layers, each layer has a specific functional layout, and some complex designs also require a multi-layer ceramic substrate (Multi-Layer Ceramic, MLC). The printed circuit board and the multi-layer ceramic substrate are connected by probes to realize the functions and effects of the semiconductor probe card, which increases the difficulty and complexity of the design. Due to the existence of complex design factors, designers need to devote a lot of energy to key links such as circuit planning, layout and wiring, which involves the consideration of many complex factors. Any slight omission may have a global impact on the overall design effect.

[0003] The traditional solution for designing a probe card is to design a probe card based on specific requirements and then evaluate it after the design is completed. If the evaluation is abnormal, rework and adjustment are required. This will cause serious delays in product development progress and the product delivery date cannot be guaranteed. Summary of the Invention

[0004] The present application provides a probe card simulation method, device, medium and program product. By performing simulation tests on the probe card, potential risks in the design can be discovered in a timely manner based on the simulation test results, the number of repeated design modifications can be reduced, the product design quality can be improved, and the product development progress can be accelerated.

[0005] To achieve the above objectives, the present application proposes a probe card simulation method, the method comprising: constructing a simulation model of each of the plurality of substructures included in the probe card; Parameterize the simulation models of each substructure; Setting link configuration information between each parameterized substructure simulation model to obtain a simulation template file; A simulation test is performed based on the input probe card actual parameter values ​​and the simulation template file.

[0006] In one embodiment, the step of setting link configuration information between the parameterized substructure simulation models to obtain a simulation template file includes: Configuring link connectivity information between each of the parameterized substructure simulation models; Add a link sending port and a link receiving port for each link; adding stimulus sources and detection points on the link; The link connectivity relationship among the excitation source, the detection point, the link sending port and the link receiving port is configured to obtain the simulation template file.

[0007] In one embodiment, after parameterizing each substructure simulation model, the method further includes: Saving model creation information of each parameterized substructure simulation model respectively to obtain each substructure simulation model file; The configuring link connectivity information between the parameterized substructure simulation models includes: Obtaining each of the substructure simulation model files; Associating each of the substructure simulation model files to the same project file; A link connectivity operation is performed on each of the parameterized substructure simulation models to obtain link connectivity information between the parameterized substructure simulation models.

[0008] In one embodiment, the performing simulation test based on the input probe card actual parameter values ​​and the simulation template file includes: Parsing the simulation template file to obtain a full-link parameterized simulation model including each of the parameterized substructure simulation models and their link relationships; Inputting the actual parameter values ​​of the probe card into the full-link parameterized simulation model to update the full-link parameterized simulation model to obtain a target full-link simulation model; A simulation test is performed in the target full-link simulation model.

[0009] In one embodiment, performing simulation testing in the target full-link simulation model includes: Acquiring simulation setting information, the simulation setting information including settings of parameter values ​​of the excitation source and / or settings of rise time and fall time of the excitation source; A simulation test is performed in the target full-link simulation model based on the simulation setting information.

[0010] In one embodiment, parameterizing each substructure simulation model includes: Determining variable parameters of each of the substructure simulation models; configuring an independent variable for each of the variable parameters; Each variable is associated with the corresponding substructure simulation model.

[0011] In one embodiment, the substructure simulation model includes a printed circuit board simulation model, a multilayer ceramic substrate simulation model, and a probe simulation model.

[0012] In addition, to achieve the above-mentioned purpose, the present application also proposes an electronic device, which includes: a memory, a processor, and a computer program stored on the memory and executable on the processor, wherein the computer program is configured to implement the steps of the probe card simulation method as described above.

[0013] In addition, to achieve the above-mentioned purpose, the present application also proposes a storage medium, which is a computer-readable storage medium. A computer program is stored on the storage medium, and when the computer program is executed by the processor, the steps of the probe card simulation method as described above are implemented.

[0014] In addition, to achieve the above-mentioned purpose, the present application also provides a computer program product, which includes a computer program. When the computer program is executed by a processor, it implements the steps of the probe card simulation method as described above.

[0015] One or more technical solutions proposed in this application have at least the following technical effects: By constructing a simulation model for each of the multiple substructures contained in the probe card, parameterizing each substructure simulation model, and setting the link configuration information between the parameterized substructure simulation models, a simulation template file is obtained. Simulation testing is performed based on the input probe card actual parameter values ​​and the simulation template file. Based on the simulation test results, potential risks in the design can be promptly identified, reducing the number of repeated design revisions, improving product design quality, and accelerating product development progress. In addition, by constructing a parameterized simulation model, the constructed simulation model can be reused on the same type of product, eliminating the need to repeatedly create models and build links, saving time and labor costs and improving efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0017] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0018] Figure 1 A schematic diagram of a flow chart of an embodiment of a simulation method for a probe card of the present application; Figure 2 A schematic diagram of a PCB simulation model involved in the simulation method of the probe card of this application; Figure 3 A schematic diagram of an MLC simulation model involved in the simulation method of the probe card of this application; Figure 4 A schematic diagram of a probe simulation model involved in the probe card simulation method of this application; Figure 5 Schematic diagram of the device structure of the hardware operating environment involved in the probe card simulation method in the embodiment of the present application. DETAILED DESCRIPTION

[0019] It should be understood that the specific embodiments described herein are merely used to explain the technical solutions of the present application and are not intended to limit the present application.

[0020] In order to better understand the technical solution of the present application, a detailed description will be given below in conjunction with the accompanying drawings and specific implementation methods.

[0021] The traditional solution for designing a probe card is to design a probe card based on specific requirements and then evaluate it after the design is completed. If the evaluation is abnormal, rework and adjustment are required. This will cause serious delays in product development progress and the product delivery date cannot be guaranteed.

[0022] In order to solve the above problems, an embodiment of the present application provides a simulation method of a probe card. The simulation method of the probe card of this embodiment is described in detail below with reference to the accompanying drawings.

[0023] See Figure 1 , Figure 1 1 is a flow chart of an embodiment of a probe card simulation method of the present application. In this embodiment, the probe card simulation method includes steps S10 to S40: Step S10 : constructing a simulation model of each of the multiple substructures included in the probe card.

[0024] Specifically, the probe card includes multiple substructures, including a printed circuit board (PCB), a multi-layer ceramic (MLC) substrate, and probes for connecting the PCB and MLC. Consequently, the multiple substructure simulation models constructed include a printed circuit board simulation model (hereinafter collectively referred to as the PCB simulation model), a multi-layer ceramic substrate simulation model (hereinafter collectively referred to as the MLC simulation model), and a probe simulation model.

[0025] In some embodiments, when modeling multiple substructures such as a PCB, an MLC, and a probe, parameter values ​​of material parameters, electrical parameters, and geometric parameters in each substructure are set to default initial values.

[0026] In some embodiments, constructing a PCB simulation model includes modeling a PCB stacking structure, a Pogo resource docking module, and a PCB-DUT docking module. As an example, the constructed PCB simulation model is as follows: Figure 2 shown.

[0027] Among them, the Pogo resource docking module refers to the connection structure on the probe card that is connected to the tester (i.e., the Pogo Pin and its surrounding structure), which is simulated to accurately simulate its electrical characteristics, mechanical behavior, and signal transmission performance.

[0028] The PCB-DUT docking module refers to the connection structure on the probe card that connects the wafer chip to be tested. By simulating it, the performance of the signal transmission process from the PCB to the wafer chip can be accurately simulated.

[0029] For example, when modeling a PCB stacked structure, key parameters such as PCB board thickness, number of PCB stacked layers, thickness of each layer, PCB board material, board dielectric constant, board dielectric loss factor, copper foil etching factor, and copper foil roughness are modeled to accurately simulate the physical and electrical properties of the PCB stacked structure.

[0030] Exemplarily, modeling the Pogo resource docking module includes modeling the pads, vias, wires, and separate components of the Pogo resource docking module.

[0031] Exemplarily, modeling the PCB-DUT interface module includes modeling the pads, vias, wires, and discrete components of the PCB-DUT interface module.

[0032] In some embodiments, constructing an MLC simulation model includes modeling an MLC stacking structure, an MLC-DUT docking module, and a wafer-DUT docking module. As an example, the constructed MLC simulation model is as follows: Figure 3 shown.

[0033] The MLC-DUT interface module connects the PCB-DUT interface module via probes. The wafer-DUT interface module is the connection structure within the MLC that connects to the wafer-based chip under test (DUT). Simulations are performed to simulate the electrical, thermal, and mechanical performance of signals transmitted from the MLC to the wafer chip.

[0034] For example, the MLC stack structure is modeled, including parameters such as MLC board thickness, number of MLC stack layers, thickness of each layer, MLC board material, board dielectric constant, board dielectric loss factor, copper foil etching factor, and copper foil roughness. By modeling the MLC stack structure, the physical and electrical characteristics of the MLC can be simulated, providing a solid foundation for subsequent simulation analysis.

[0035] Exemplarily, modeling the MLC-DUT interface module includes modeling pads, vias, wires, and discrete components of the MLC-DUT interface module.

[0036] Exemplarily, modeling the wafer-DUT interface module includes modeling pads, vias, wires, and discrete components of the wafer-DUT interface module.

[0037] In some embodiments, establishing a probe simulation model includes: converting the 3D structural model of the probe into a model suitable for simulation analysis, and modeling the probe material and the contact port of the probe. As an example, the constructed probe simulation model is as follows: Figure 4 shown.

[0038] Step S20: performing parameter setting on each substructure simulation model.

[0039] In some embodiments, parameterizing each substructure simulation model may include: Determine the variable parameters of each substructure simulation model; Configure independent variables for each variable parameter; Associate each variable with the corresponding substructure simulation model.

[0040] Specifically, when each substructure is modeled in step S10, the parameter values ​​of the material parameters, electrical parameters and geometric parameters in each substructure are set to default initial values.

[0041] In order to enable each substructure simulation model to be applied to other probe card products of the same type, this embodiment parameterizes each substructure simulation model. Specifically, the parameters that affect the model performance or results in each substructure simulation model are first determined. These parameters are variable parameters. For example, the geometric parameters, physical parameters, and electrical parameters of the PCB simulation model, MLC simulation model, and probe simulation model can be set as variable parameters. The variable parameters include but are not limited to pad diameter, pad spacing, via diameter, wire width, the size and number of discrete components, and the number of probes.

[0042] Then, for each variable parameter, assign it a separate variable and associate it with the corresponding substructure simulation model. For example, for pad diameter, set it as variable D. Then, in the PCB simulation model, locate the pad at a specific location and associate variable D with the pad's diameter parameter. This way, when the pad diameter needs to be adjusted, simply modify the value of variable D, and the corresponding pad's diameter in the PCB simulation model will automatically update.

[0043] In some embodiments, after completing the parameterization of each substructure simulation model, the model creation information of each parameterized substructure simulation model is saved to obtain each substructure simulation model file. By recording the model creation information of each parameterized substructure simulation model in a file, subsequent simulation operations, model management, and reuse are facilitated.

[0044] Step S30 : setting link configuration information between each parameterized substructure simulation model to obtain a simulation template file.

[0045] In some embodiments, the simulation template file is obtained by performing the following steps: Configure the link connectivity information between each parameterized substructure simulation model; Add a link sending port and a link receiving port for each link; Add stimulus sources and probe points on the link; Configure the link connectivity relationship between the stimulus source, the detection point, the link sending port, and the link receiving port to obtain a simulation template file.

[0046] During implementation, first interconnect the simulation links between the parameterized PCB simulation model, MLC simulation model, and probe simulation model. Once the links are interconnected, add a link transmit port and a link receive port for each link. The link transmit port is responsible for transmitting signals, while the link receive port is used to receive incoming signals. Then, based on actual simulation requirements, add corresponding stimulus sources and probe points to the link. The stimulus source provides input signals to the simulation system. Common stimulus sources include voltage, eye diagram, and current. Different stimulus sources are suitable for different simulation scenarios. For example, a voltage stimulus source can be used to simulate DC or AC voltage signals, while an eye diagram stimulus source is often used for simulation analysis of high-speed signal transmission. Probe points collect signal information from the link to analyze and evaluate signal parameters such as waveform, amplitude, and frequency. Common probe points include voltage, eye diagram, and current. Furthermore, a reference ground is required to provide a stable potential reference for the entire simulation link. Finally, using tools such as Circuit Wire provided by the simulation software, the excitation source, port, detection point and reference ground in the link are connected to form a complete closed-loop link.

[0047] In some embodiments, link connectivity information between parameterized substructure simulation models is configured through the following steps: Obtain simulation model files of each substructure; Associate each substructure simulation model file to the same project file; A link connectivity operation is performed on each parameterized substructure simulation model to obtain link connectivity information between each parameterized substructure simulation model.

[0048] Specifically, first obtain each substructure simulation model file from the storage location corresponding to each substructure simulation model file, then associate each substructure simulation model file obtained to the same project file, so that each substructure simulation model is uniformly managed through the project file. Then, utilizing the tools and interfaces provided by the simulation software, establish the connection relationship between each substructure by dragging, connecting lines, etc., such as connecting the network structure between the PCB simulation model, the MLC simulation model and the probe simulation model to realize the interconnection of multiple substructure simulation models. After completing the link connectivity operation, the system automatically records the link connectivity information between each parameterized substructure simulation model. Since each substructure simulation model file is all associated under the same project file, when one of the substructure simulation model files is modified, the modification information is automatically synchronized to all substructure simulation models interconnected therewith.

[0049] The above steps generate a simulation template file containing each parameterized substructure simulation model and its link configuration information. This file provides a complete model framework and data support for subsequent simulation analysis. Users only need to adjust the model parameters and simulation conditions according to actual needs to quickly conduct simulation tests in different scenarios, greatly improving simulation efficiency.

[0050] Step S40 , performing simulation testing based on the input probe card actual parameter values ​​and simulation template file.

[0051] In some implementations, the above S40 may include: Parse the simulation template file to obtain a full-link parameterized simulation model including each parameterized substructure simulation model and its link relationship; Input the actual parameter values ​​of the probe card to update the full-link parameterized simulation model to obtain the target full-link simulation model; Perform simulation tests in the target full-link simulation model.

[0052] Specifically, the input actual parameter values ​​of the probe card are imported into the full-link parameterized simulation model obtained by parsing, and the parameter values ​​of the relevant parameters in the link parameterized simulation model are set to obtain the target full-link simulation model.

[0053] In some implementations, performing simulation testing in a target full-link simulation model may include: Acquiring simulation setting information, where the simulation setting information includes settings of parameter values ​​of an excitation source and / or settings of a rise time and a fall time of the excitation source; Perform simulation tests in the target full-link simulation model based on the simulation setting information.

[0054] During specific implementation, simulation setting information input by the user is obtained, and the simulation setting information includes but is not limited to the voltage setting of the voltage excitation source, the rise time and fall time setting of the eye diagram excitation source, the symbol rate and symbol type setting of the link channel transmission, the rise time and fall time setting of the current excitation source, and the signal frequency and pulse width setting of the link channel.

[0055] After completing the simulation settings, various types of simulation analysis can be performed to comprehensively evaluate the performance of the target full-link simulation model. Simulation analysis can include transient analysis, fast eye diagram analysis, and linear network analysis. Transient analysis aims to analyze the signal response of the target full-link simulation model during transient processes, such as the rising edge, falling edge, overshoot, undershoot and other characteristics of the signal, in order to evaluate the performance of the probe card under rapid signal changes. Eye diagram analysis can be used to intuitively observe the eye diagram quality of the signal, including parameters such as eye height and eye width. Among them, the eye height of the eye diagram represents noise; the eye width represents jitter. Linear network analysis is to perform linear network analysis on the target full-link simulation model, calculate parameters such as the insertion loss, return loss and impedance of the power distribution network (PDN) of the test points on the link, to evaluate the electrical characteristics of the probe card at different frequencies, and provide a reference for optimizing the design of the probe card.

[0056] After completing the simulation analysis, the simulation analysis results of the target full-link simulation model are output. The output content includes but is not limited to voltage results, fast eye diagram results, current results, insertion loss and return loss results, and power distribution network impedance results. The output format can be data tables, curve graphs, etc., so that users can intuitively view and analyze the simulation analysis results, providing strong support for probe card design and optimization.

[0057] In some embodiments, the probe card simulation method further includes: Obtain the simulation test result corresponding to the actual parameter value of the probe card input at that time, and record it as the simulation test result of that time; If the simulation test results do not meet the preset conditions, the parameter values ​​of the full-link parameterized simulation model are updated, and the full-link parameterized simulation model is simulated and tested based on the updated parameter values ​​until the simulation test results meet the preset conditions.

[0058] Specifically, after each simulation test, the system automatically retrieves the simulation test results corresponding to the actual probe card parameter values ​​entered that time from the simulation software or storage module. The simulation test results include data from multiple dimensions, such as voltage waveforms, current waveforms, insertion loss, return loss, and other key indicators.

[0059] Then, it is determined whether the current simulation test result meets the preset conditions. The preset conditions can be formulated based on the actual application scenarios, performance requirements, and relevant industry standards of the probe card. In some embodiments, the simulation results of each specific performance indicator in the current simulation test result can be extracted, and it is determined whether each specific performance indicator simulation result meets the corresponding specific performance indicator target setting conditions. If all specific performance indicator simulation results meet the corresponding specific performance indicator target setting conditions, it is determined that the current simulation test result meets the preset conditions. If any specific performance indicator simulation result does not meet the corresponding specific performance indicator target setting conditions, it is determined that the current simulation test result does not meet the preset conditions.

[0060] As an example, the peak value of the voltage waveform (hereinafter referred to as "voltage peak value"), the peak value of the current waveform (hereinafter referred to as "current peak value"), eye height, eye width, insertion loss and return loss can be used as specific performance indicators. Then, obtain the simulation results of the voltage peak value (hereinafter referred to as "simulated voltage peak value"), the simulation results of the current peak value (hereinafter referred to as "simulated voltage peak value"), the simulation results of the eye height (hereinafter referred to as "eye height simulation value"), the simulation results of the eye width (hereinafter referred to as "eye width simulation value"), the simulation results of the insertion loss (hereinafter referred to as "insertion loss simulation value") and the simulation results of the return loss (hereinafter referred to as "return loss simulation value") output by the simulation test, and judge in turn whether the simulation voltage peak value, the simulation current peak value, the eye height simulation value, the eye width simulation value, the insertion loss simulation value and the return loss simulation value all meet the corresponding specific performance indicator target setting conditions. Specifically, if the simulation voltage peak value is equal to the current peak value, If the difference between the voltage peak value threshold and the current peak value threshold is within a preset first range, the difference between the simulated current peak value and the current peak value threshold is within a preset second range, the difference between the eye height simulation value and the eye height threshold is within a preset third range, the difference between the eye width simulation value and the eye width threshold is within a preset fourth range, the difference between the insertion loss simulation value and the insertion loss threshold is within a preset fifth range, and the difference between the return loss simulation value and the return loss threshold is within a preset sixth range, then it is determined that the current simulation test result meets the preset conditions. Among them, the preset first range, preset second range, preset third range, preset fourth range, preset fifth range, and preset sixth range can be set according to actual needs or experience, and this application is not limited thereto.

[0061] In some implementations, if the simulation test result does not meet the preset conditions, updating the parameter values ​​of the full-link parameterized simulation model may include: Determine the specific performance indicators in the current simulation test results that do not meet the corresponding specific performance indicator target setting conditions, and record them as specific performance indicators to be optimized; Determine the parameters that are associated with each specific performance indicator to be optimized and record them as the parameters to be optimized; For each parameter to be optimized, the difference between the simulation result of the corresponding specific performance indicator to be optimized and the set threshold of the corresponding specific performance indicator is calculated, and the difference range of the difference is determined according to the pre-set rules; Adjust the parameter value of the corresponding parameter to be optimized according to the adjustment amplitude and adjustment direction that match the corresponding difference range.

[0062] Specifically, the current simulation test results are first analyzed, and the specific performance indicators that do not meet the target setting conditions of the corresponding specific performance indicators are screened out and recorded as specific performance indicators to be optimized. Then, the parameters corresponding to each specific performance indicator to be optimized are determined through a pre-established performance indicator association reference table. In addition, the simulation results of each specific performance indicator to be optimized are subtracted from the corresponding specific performance indicator setting threshold to obtain a difference. Taking the specific performance indicator to be optimized as the voltage peak as an example, the simulation voltage peak is subtracted from the voltage peak threshold to obtain the difference between the simulation voltage peak and the voltage peak threshold.

[0063] Afterwards, based on the correspondence between the parameters, the difference range, the adjustment direction and the adjustment amplitude, for each parameter to be optimized, the parameter value of the parameter to be optimized is adjusted according to the adjustment amplitude and adjustment direction that match the corresponding difference range. Among them, the adjustment direction includes a positive direction and a negative direction. The positive direction refers to increasing the parameter value of the parameter on the basis of the original parameter value, and the negative direction refers to decreasing the parameter value of the parameter on the basis of the original parameter value. For example, assuming that the pad diameter is A, the adjustment direction is the positive direction, and the adjustment amplitude is F%, then the adjusted pad diameter A'=A+A*F%; and assuming that the pad diameter is A, the adjustment direction is the negative direction, and the adjustment amplitude is F%, then the adjusted pad diameter A'=AA*F%.

[0064] It should be noted that the difference ranges for different parameters can be different. For example, for the pad diameter parameter, the difference range can be divided into [D1, D3), [D3, D4]; for the PCB thickness parameter, the difference range can be divided into [D1, D2), [D2, D3), [D3, D5]. Among them, D1, D2, D3, D4 and D5 are all preset thresholds, and D1 <D2<D3<D4<D5。

[0065] Through the above-mentioned difference alienation adjustment strategy, the influence of different parameters on system performance and the severity of deviation are fully considered, and the parameters can be adjusted reasonably, thereby improving the system performance more effectively.

[0066] It should be noted that the above examples are only used to understand the present application and do not constitute a limitation on the simulation method of the probe card of the present application. More simple transformations based on this technical concept are all within the scope of protection of the present application.

[0067] The present application provides an electronic device, which includes: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions that can be executed by the at least one processor, and the instructions are executed by the at least one processor so that the at least one processor can execute the simulation method of the probe card in the above-mentioned embodiment one.

[0068] Reference below Figure 5 , which shows a schematic diagram of the structure of an electronic device suitable for implementing the embodiments of the present application. The electronic devices in the embodiments of the present application may include, but are not limited to, mobile terminals such as mobile phones, laptop computers, digital broadcast receivers, PDAs (Personal Digital Assistants), PADs (Portable Application Descriptions), PMPs (Portable Media Players), in-vehicle terminals (such as in-vehicle navigation terminals), and fixed terminals such as digital TVs and desktop computers. Figure 5 The electronic device shown is merely an example and should not limit the functions and scope of use of the embodiments of the present application.

[0069] like Figure 5As shown, the electronic device may include a processing device 1001 (e.g., a central processing unit, a graphics processing unit, etc.), which can perform various appropriate actions and processes based on programs stored in a read-only memory (ROM) 1002 or programs loaded from a storage device 1003 into a random access memory (RAM) 1004. RAM 1004 also stores various programs and data required for the operation of the electronic device. Processing device 1001, ROM 1002, and RAM 1004 are interconnected via a bus 1005. An input / output (I / O) interface 1006 is also connected to the bus. Typically, the following systems may be connected to I / O interface 1006: input devices 1007 including, for example, a touchscreen, touchpad, keyboard, mouse, image sensor, microphone, accelerometer, gyroscope, etc.; output devices 1008 including, for example, a liquid crystal display (LCD), speaker, vibrator, etc.; storage device 1003 including, for example, a magnetic tape or hard disk; and communication devices 1009. The communication device 1009 can allow the electronic device to communicate with other devices wirelessly or by wire to exchange data. Although the figure shows an electronic device with various systems, it should be understood that it is not required to implement or have all the systems shown. More or fewer systems can be implemented or have instead.

[0070] In particular, according to the embodiments disclosed in the present application, the processes described above with reference to the flowcharts can be implemented as computer software programs. For example, the embodiments disclosed in the present application include a computer program product comprising a computer program carried on a computer-readable medium, the computer program comprising program code for executing the method shown in the flowchart. In such an embodiment, the computer program can be downloaded and installed from a network via a communication device, or installed from a storage device 1003, or installed from a ROM 1002. When the computer program is executed by the processing device 1001, the above-mentioned functions defined in the method of the embodiment disclosed in the present application are executed.

[0071] The electronic device provided in this application utilizes the probe card simulation method of the aforementioned embodiment. Compared to the prior art, the electronic device provided in this application has the same beneficial effects as the probe card simulation method of the aforementioned embodiment, and the other technical features of the electronic device are the same as those disclosed in the aforementioned embodiment, and are not further described here.

[0072] It should be understood that the various parts disclosed in this application can be implemented using hardware, software, firmware, or a combination thereof. In the description of the above embodiments, specific features, structures, materials, or characteristics can be combined in any one or more embodiments or examples in a suitable manner.

[0073] The present application provides a computer-readable storage medium having computer-readable program instructions (ie, a computer program) stored thereon, wherein the computer-readable program instructions are used to execute the simulation method of the probe card in the above-mentioned embodiment.

[0074] The computer-readable storage medium provided herein may be, for example, a USB flash drive, but is not limited to electrical, magnetic, optical, electromagnetic, infrared, or semiconductor systems, systems, or devices, or any combination thereof. More specific examples of computer-readable storage media may include, but are not limited to, an electrical connection having one or more wires, a portable computer disk, a hard disk, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination thereof. In this embodiment, the computer-readable storage medium may be any tangible medium that contains or stores a program that can be used by or in conjunction with an instruction execution system, system, or device. The program code contained on the computer-readable storage medium may be transmitted using any suitable medium, including, but not limited to, wires, optical cables, RF (Radio Frequency), etc., or any suitable combination thereof.

[0075] The computer-readable storage medium may be included in the electronic device, or may exist independently without being incorporated into the electronic device.

[0076] Computer program code for performing the operations of the present application may be written in one or more programming languages, or a combination thereof, including object-oriented programming languages ​​such as Java, Smalltalk, C++, and conventional procedural programming languages ​​such as "C" or similar programming languages. The program code may be executed entirely on the user's computer, partially on the user's computer, as a stand-alone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In the case of a remote computer, the remote computer may be connected to the user's computer via any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computer (e.g., via the Internet using an Internet service provider).

[0077] The flow charts and block diagrams in the accompanying drawings illustrate the possible architecture, functions and operations of the systems, methods and computer program products according to various embodiments of the present application. In this regard, each box in the flow chart or block diagram can represent a module, program segment or a part of code, and the module, program segment or a part of code contains one or more executable instructions for realizing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the box can also occur in a different order than that marked in the accompanying drawings. For example, two boxes represented in succession can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram and / or flow chart, and the combination of the boxes in the block diagram and / or flow chart can be implemented by a dedicated hardware-based system that performs the specified function or operation, or can be implemented by a combination of dedicated hardware and computer instructions.

[0078] The modules described in the embodiments of the present application may be implemented in software or hardware, wherein the name of a module does not necessarily limit the unit itself.

[0079] The computer-readable storage medium provided in this application is a computer-readable storage medium that stores computer-readable program instructions (i.e., a computer program) for executing the aforementioned probe card simulation method. Compared to the prior art, the computer-readable storage medium provided in this application offers the same beneficial effects as the probe card simulation method provided in the aforementioned embodiment, and therefore will not be further elaborated here.

[0080] The present application also provides a computer program product, including a computer program, which implements the steps of the above-mentioned probe card simulation method when executed by a processor.

[0081] Compared with the prior art, the beneficial effects of the computer program product provided in this application are the same as the beneficial effects of the probe card simulation method provided in the above embodiment, and are not described in detail here.

[0082] The above are only some embodiments of the present application and are not intended to limit the patent scope of the present application. All equivalent structural transformations made using the contents of the present application specification and drawings under the technical concept of the present application, or direct / indirect application in other related technical fields are included in the patent protection scope of the present application.

Claims

1. A probe card simulation method, characterized in that: include: constructing a simulation model of each of the plurality of substructures included in the probe card; Parameterize the simulation models of each substructure; Setting link configuration information between each parameterized substructure simulation model to obtain a simulation template file; A simulation test is performed based on the input probe card actual parameter values ​​and the simulation template file.

2. The probe card simulation method according to claim 1, wherein: The link configuration information between the parameterized substructure simulation models is set to obtain a simulation template file, including: Configuring link connectivity information between each of the parameterized substructure simulation models; Add a link sending port and a link receiving port for each link; adding stimulus sources and detection points on the link; The link connectivity relationship among the excitation source, the detection point, the link sending port and the link receiving port is configured to obtain the simulation template file.

3. The probe card simulation method according to claim 2, wherein: After parameterizing each substructure simulation model, the method further includes: Saving model creation information of each parameterized substructure simulation model respectively to obtain each substructure simulation model file; The configuring link connectivity information between the parameterized substructure simulation models includes: Obtaining each of the substructure simulation model files; Associating each of the substructure simulation model files to the same project file; A link connectivity operation is performed on each of the parameterized substructure simulation models to obtain link connectivity information between the parameterized substructure simulation models.

4. The probe card simulation method according to claim 3, wherein: The performing simulation test based on the input probe card actual parameter values ​​and the simulation template file includes: Parsing the simulation template file to obtain a full-link parameterized simulation model including each of the parameterized substructure simulation models and their link relationships; Inputting the actual parameter values ​​of the probe card into the full-link parameterized simulation model to update the full-link parameterized simulation model to obtain a target full-link simulation model; A simulation test is performed in the target full-link simulation model.

5. The probe card simulation method according to claim 4, wherein: The performing simulation testing in the target full-link simulation model includes: Acquiring simulation setting information, the simulation setting information including settings of parameter values ​​of the excitation source and / or settings of rise time and fall time of the excitation source; A simulation test is performed in the target full-link simulation model based on the simulation setting information.

6. The probe card simulation method according to claim 1, wherein: The parameterization of each substructure simulation model includes: Determining variable parameters of each of the substructure simulation models; configuring an independent variable for each of the variable parameters; Each variable is associated with the corresponding substructure simulation model.

7. The probe card simulation method according to claim 1, wherein: The substructure simulation model includes a printed circuit board simulation model, a multilayer ceramic substrate simulation model and a probe simulation model.

8. An electronic device, characterized in that: The electronic device includes a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the computer program is configured to implement the steps of the probe card simulation method according to any one of claims 1 to 7.

9. A storage medium, characterized in that: The storage medium is a computer-readable storage medium. A computer program is stored on the storage medium. When the computer program is executed by a processor, the steps of the probe card simulation method according to any one of claims 1 to 7 are implemented.

10. A computer program product, characterized in that The computer program product includes a computer program, and when the computer program is executed by a processor, the steps of the probe card simulation method according to any one of claims 1 to 7 are implemented.

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