Embedded packaging module for power chip

Abstract

The invention discloses a power chip embedded type packaging module which comprises a chip carrier plate which comprises a first circuit substrate and a conducting strip embedded in the first circuit substrate; a ceramic substrate disposed on the first surface side of the chip carrier; the second circuit substrate is arranged on the second surface side of the chip carrier; the plurality of power chips are packaged between the chip carrier plate and the ceramic substrate; the first side of the power chip is electrically connected with the first circuit substrate and the conducting strip, and the second side, opposite to the first side, of the power chip is electrically connected with the ceramic substrate; two opposite sides of each ceramic heat conduction block are respectively connected with the conducting strip and the ceramic substrate; and the heat-conducting ceramic blocks and the power chips are alternately arranged along the length direction of the conducting strip. The packaging module has the advantages of being high in integration level and good in heat dissipation performance, the circuit loop area of the module can be reduced, circuit impedance is effectively reduced, and the parasitic inductance effect is reduced.

Description

Technical Field

[0001] The present invention relates to the field of power chip packaging, and in particular to a power chip embedded packaging module. Background Art

[0002] Power modules, which include power chips such as IGBTs and / or MOSFETs, are widely used in various power electronic devices. These power chips generate a large amount of heat during operation. If the packaging module cannot dissipate this heat in a timely manner, the operation of the power devices and surrounding electronic components will be seriously affected. Therefore, the packaging module is required to have excellent heat dissipation performance.

[0003] In switching power supply applications, the parasitic inductance of the power chip circuit easily generates high peak voltages, which in turn leads to significant electromagnetic interference and increased switching power losses. Therefore, it is necessary to minimize the parasitic inductance of the power module. Furthermore, as power modules become increasingly miniaturized, they are required to have a higher degree of package integration. Summary of the Invention

[0004] The main purpose of the present invention is to provide a power chip packaging module with good heat dissipation performance, high integration, low circuit impedance and parasitic effects.

[0005] In order to achieve the above-mentioned main objectives, an embodiment of the present invention discloses a power chip embedded packaging module, comprising:

[0006] A chip carrier, comprising a first circuit substrate and a conductive sheet embedded in the first circuit substrate;

[0007] A ceramic substrate, disposed on the first surface side of the chip carrier;

[0008] a second circuit substrate, disposed on the second surface side of the chip carrier;

[0009] a plurality of power chips packaged between the chip carrier and the ceramic substrate; wherein a first side of the power chip is electrically connected to the first circuit substrate and the conductive sheet, and a second side of the power chip opposite to the first side is electrically connected to the ceramic substrate;

[0010] A plurality of thermally conductive ceramic blocks, two opposite sides of each ceramic thermally conductive block are respectively connected to the conductive sheet and the ceramic substrate; wherein, along the length direction of the conductive sheet, the thermally conductive ceramic blocks and the power chips are alternately arranged.

[0011] In this technical solution, the power chip and thermally conductive ceramic blocks are packaged between a ceramic substrate and a chip carrier equipped with a conductive sheet. The thermally conductive ceramic blocks are arranged alternately with the power chip. Heat generated by the power chip is conducted to the ceramic substrate via the conductive sheet and thermally conductive ceramic blocks on its first side and directly to the ceramic substrate on its second side, thereby achieving three-dimensional heat dissipation of the power chip and improving the heat dissipation performance of the packaged module. Furthermore, a second circuit substrate, on which various circuit components can be mounted, is provided on the second surface of the chip carrier. This eliminates the need for the power chip and circuit components to be mounted on the same mounting surface. This not only improves the module's packaging integration but also reduces the circuit loop area of ​​the power chip, effectively lowering circuit impedance and minimizing parasitic inductance effects.

[0012] Furthermore, along the length direction of the conductive sheet, the size of the thermally conductive ceramic block in the middle is twice that of the thermally conductive ceramic blocks at both ends, so as to ensure uniform heat dissipation and current distribution of the module and avoid local overheating of the module.

[0013] Furthermore, a lateral protrusion embedded in the first circuit substrate is provided on a side edge of the conductive sheet to more firmly connect the conductive sheet to the first circuit substrate.

[0014] Furthermore, the conductive sheet is provided with pins protruding to the outside of the packaging module to facilitate connection to an external power supply.

[0015] Furthermore, the ceramic substrate includes a ceramic core plate and a metal conductive layer and a metal heat dissipation layer respectively arranged on opposite sides of the ceramic core plate, and the metal conductive layer is connected to the power chip and the thermally conductive ceramic block.

[0016] Furthermore, a radiator is connected to the metal heat dissipation layer, and the radiator is provided with heat dissipation fins.

[0017] Furthermore, the heat sink forms a cavity sealed to the ceramic substrate to accommodate the cooling medium, and the inner wall of the cavity is provided with a capillary structure. During operation, the ceramic substrate forms an evaporation zone, and the heat dissipation fins form a condensation zone. Through the evaporation-cooling cycle of the cooling medium, heat from the ceramic substrate is quickly and evenly transferred to all the heat dissipation fins.

[0018] Furthermore, a driving component and circuit elements are provided on the second circuit substrate.

[0019] Furthermore, the second circuit substrate includes a multilayer conductive circuit, and the conductive circuits of the first circuit substrate are electrically connected to the conductive circuits of the second circuit substrate, so that some circuit elements can be encapsulated inside the second circuit substrate, further improving the integration of the packaging module.

[0020] Furthermore, at least one group of the conductive sheets is provided in the first circuit substrate, each group of the conductive sheets includes a first conductive sheet and a second conductive sheet, and the thermal conductive ceramic blocks and the power chips are alternately provided on the first conductive sheet and the second conductive sheet.

[0021] Furthermore, a source and a gate are provided on the first side of the power chip, a drain is provided on the second side of the power chip, the source and the gate are electrically connected to the conductive sheet and the first circuit substrate respectively, and the drain is electrically connected to the ceramic substrate.

[0022] In order to more clearly illustrate the purpose, technical solutions and advantages of the present invention, the present invention is further described in detail below with reference to the accompanying drawings and specific embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 This is a schematic diagram of the overall structure of the first viewing angle of Example 1 of the present invention;

[0024] Figure 2 This is a schematic diagram of the overall structure of the second viewing angle of Example 1 of the present invention;

[0025] Figure 3 This is a schematic diagram of the first decomposition structure of Example 1 of the present invention;

[0026] Figure 4 Schematic diagram of the structure of the ceramic substrate and the heat sink in Example 1 of the present invention;

[0027] Figure 5 This is a second decomposition structure diagram of Example 1 of the present invention;

[0028] Figure 6 This is a schematic diagram of the first three-dimensional structure of the chip carrier in Example 1 of the present invention;

[0029] Figure 7 is a schematic structural diagram of the conductive sheet assembly in Example 1 of the present invention;

[0030] Figure 8 1 is a schematic structural diagram of the conductive portion on the ceramic substrate in Example 1 of the present invention;

[0031] Figure 9 This is a schematic diagram of the three-dimensional structure of a power chip and a ceramic heat-conducting block arranged on a chip carrier in Example 1 of the present invention;

[0032] Figure 10 2 is a schematic diagram of a second three-dimensional structure of the chip carrier in Example 1 of the present invention;

[0033] Figure 11 yes Figure 9 A schematic diagram of the front structure of FIG.

[0034] Figure 12 Schematic diagram of the conductive connection structure of the power chip in Example 1 of the present invention;

[0035] Figure 13 is an equivalent circuit diagram of the power chipset in Example 1 of the present invention;

[0036] Figure 14 This is a schematic diagram of the overall structure of Example 2 of the present invention;

[0037] Figure 15 This is a schematic diagram of the first decomposition structure of Example 2 of the present invention;

[0038] Figure 16 This is a second decomposition structure diagram of Example 2 of the present invention;

[0039] Figure 17 2 is a schematic diagram of the three-dimensional structure of the chip carrier portion in Example 2 of the present invention;

[0040] Figure 18 2 is a schematic front view of the first surface side of the chip carrier in Example 2 of the present invention;

[0041] Figure 19 2 is a schematic diagram of the front view of the second surface side of the chip carrier in Example 2 of the present invention. DETAILED DESCRIPTION

[0042] In the following description, many specific details are set forth in conjunction with specific embodiments to facilitate a full understanding of the present invention. However, it should be understood that the following specific embodiments and detailed descriptions are only for illustrative purposes and do not limit the scope of protection of the present invention.

[0043] Example 1

[0044] like Figure 1-Figure 5 As shown, the power chip embedded package module disclosed in the embodiment includes a chip carrier 10, multiple power chips 21, a ceramic substrate 30, and a second circuit substrate 40. The ceramic substrate 30 is arranged on the first surface side of the chip carrier 10, the second circuit substrate 40 is arranged on the second surface side of the ceramic substrate 30, and a heat sink 50 is provided on the side of the ceramic substrate 30 facing away from the chip carrier 10.

[0045] like Figure 3 and Figure 4 As shown, the ceramic substrate 30 includes a ceramic core 31, and a metal conductive layer 32 and a metal heat dissipation layer 33 disposed on opposite sides of the ceramic core 31. The metal conductive layer 32 and the metal heat dissipation layer 33 are typically copper foil layers or composite metal layers including copper foil layers. The metal conductive layer 32 is disposed facing the chip carrier 10, and the metal heat dissipation layer 33 is connected to the heat sink 50.

[0046] like Figure 6As shown, the chip carrier 10 includes a first circuit substrate 11 and a conductive sheet 12 embedded in the first circuit substrate 11. The first circuit substrate 11 is used to transmit relatively small currents (e.g., control signals), while the conductive sheet 12 is used to transmit relatively large currents. The first circuit substrate 11 can have conductive circuit layers on both surfaces (e.g., a double-sided FR-4 circuit board), or it can have a conductive circuit layer only on the side facing the ceramic substrate 30 (e.g., a single-sided FR-4 circuit board). The conductive sheet 12 is preferably a copper sheet, but this application is not limited thereto.

[0047] The conductive sheet 12 can have substantially the same thickness as the first circuit substrate 11 and extend through the first circuit substrate 11 in the thickness direction of the first circuit substrate 11. Alternatively, the conductive sheet 12 can be thinner than the first circuit substrate 11 and be embedded within the first circuit substrate 11 in the thickness direction of the first circuit substrate 11. Preferably, the surfaces of the conductive sheet 12 and the first circuit substrate 11 facing the ceramic substrate 30 are flush with each other to facilitate mounting of the power chip 21.

[0048] Further, if Figure 7 As shown, the side of the conductive sheet 12 is provided with a lateral protrusion 120 embedded in the first circuit substrate 11 in a plane direction perpendicular to the thickness direction of the first circuit substrate 11, so as to more reliably fix the conductive sheet 12 in the first circuit substrate 11. The thickness of the lateral protrusion 120 is less than the thickness of the conductive sheet 12. The side of each conductive sheet 12 can be provided with multiple lateral protrusions 120 distributed at intervals (such as Figure 7 In addition, each conductive sheet 12 may have a single lateral protrusion continuously distributed along multiple sides thereof to facilitate manufacturing and processing.

[0049] like Figure 5 As shown, power chip 21 is packaged between chip carrier 10 and ceramic substrate 30, and the gap between chip carrier 10 and ceramic substrate 30 is filled with a packaging material layer 60, such as resin. Power chip 21 can be an IGBT (insulated gate bipolar transistor), MOSFET (metal-oxide semiconductor field-effect transistor), GTO (gate turn-off thyristor), GTR (power transistor), BJT (bipolar junction transistor), UJT (unijunction transistor), or other chips. The embodiment uses an IGBT chip as an example.

[0050] In the present invention, multiple power chips 21 can form at least one power chipset group 20. The chip carrier 10 is provided with at least one set of conductive sheets 12, and the metal conductive layer 32 of the ceramic substrate 30 is provided with at least one set of conductive portions 321. The first side of the power chip 21 is electrically connected to the first circuit substrate 11 and the conductive sheet 12, and the second side of the power chip 21, opposite the first side, is electrically connected to the ceramic substrate 30. Furthermore, multiple thermally conductive ceramic blocks 13 are provided between the chip carrier 10 and the ceramic substrate 30. Opposite sides of each thermally conductive ceramic block 13 are connected to the conductive sheet 12 and the ceramic substrate 30, respectively. The thermally conductive ceramic blocks 13 and the power chips 21 are alternately arranged along the length of the conductive sheet 12.

[0051] In this embodiment, the package module is provided with three power chipset groups 20, each power chipset group 20 including 20 power chips 21. The chip carrier 10 is provided with three groups of conductive sheets 12, each group of conductive sheets 12 including a first conductive sheet 121, a second conductive sheet 122, and a third conductive sheet 123. The metal conductive layer 32 of the ceramic substrate 30 is provided with three groups of conductive portions 321, each group of conductive portions 321 including a first conductive portion 321a and a second conductive portion 321b. It should be noted that the specific number of conductive sheets in each group of conductive sheets 12 and the specific number of conductive portions in each group of conductive portions 321 can be designed according to requirements and are not limited in this application.

[0052] like Figure 9 Zhihe Figure 12 As shown, a portion of the power chips 21 (e.g., ten power chips 21a) in each power chipset group 20 are arranged along the length direction of the first conductive sheet 121, and another portion of the power chips 21 (e.g., another ten power chips 21b) in each power chipset group 20 are arranged along the length direction of the second conductive sheet 122. The length directions of the first conductive sheet 121 and the second conductive sheet 122 may be parallel to each other.

[0053] The equivalent circuit diagram of the power chipset 20 can be found in Figure 13 Specifically, a source S and a gate G are provided on the first side of the power chip 21, and a drain D is provided on the second side of the power chip 21. The source S and the gate G on the first side of the power chip 21a are electrically connected to the first conductive sheet 121 and the first circuit substrate 11, respectively, and the drain D on the second side of the power chip 21a is electrically connected to the first conductive portion 321a of the ceramic substrate 30. The source S and the gate G on the first side of the power chip 21b are electrically connected to the second conductive sheet 122 and the first circuit substrate 11, respectively, and the drain D on the second side of the power chip 21b is electrically connected to the second conductive portion 321b of the ceramic substrate 30.

[0054] The first conductive plate 121 includes a first pin 121a extending outside the package module and a lateral extension 121b extending toward the side of the second conductive plate 122. The lateral extension 121b is provided with a first intermediate conductive portion 101 connected to the second conductive portion 321b of the ceramic substrate 30, thereby achieving electrical connection between the first conductive plate 121 and the second conductive portion 321b via the first intermediate conductive portion 101. The second conductive plate 122 includes a second pin 122a extending outside the package module. The first pin 121a can be a SW pin (switch pin), and the second pin 122a can be a source pin. As a variation of this embodiment, the first pin 121a may not be part of the first conductive plate 121, but may be electrically connected to the first conductive plate 121 via welding or screw fastening. The second pin 122a may not be part of the second conductive plate 122, but may be electrically connected to the second conductive plate 122 via welding or screw fastening.

[0055] The third conductive sheet 123 is provided with a second intermediate conductive portion 102 connected to the first conductive portion 321a of the ceramic substrate 30. This second intermediate conductive portion 102 provides electrical connection between the third conductive sheet 123 and the first conductive portion 321a. The third conductive sheet 123 has a third pin 123a extending outside the module. This third pin 123a may be a drain pin. As a variation of this embodiment, the third conductive sheet 123 may not be embedded in the first circuit substrate 11, but may instead be electrically connected to the first conductive portion 321a of the ceramic substrate 30 by welding, screwing, or other means.

[0056] Thermally conductive ceramic blocks 13 are connected to the first and second conductive sheets 121, 122, and are arranged alternately with the power chips 21. The thermally conductive ceramic blocks 13 are connected to the metal conductive layer 32 of the ceramic substrate 30. For example, the thermally conductive ceramic blocks 13 on the first conductive sheet 121 are connected to the first conductive portion 321a, and the thermally conductive ceramic blocks 13 on the second conductive sheet 122 are connected to the second conductive portion 321b. Heat from the power chip 21 is conducted from the first surface to the first and second conductive sheets 121, 122, and then further conducted to the ceramic substrate 30 through the thermally conductive ceramic blocks 13. Preferably, metal layers, such as copper foil layers, may be provided on opposite sides of the thermally conductive ceramic blocks 13 to facilitate connection (e.g., welding) of the opposite sides of the thermally conductive ceramic blocks 13 to the conductive sheet 12 and the metal conductive layer 32 of the ceramic substrate 30.

[0057] Considering that the heat-conducting ceramic block 13b disposed between adjacent power chips 21 needs to conduct the heat of the adjacent power chips 21 at the same time, Figure 11As shown, along the length direction of the first conductive sheet 121 or the second conductive sheet 122, the size of the thermally conductive ceramic blocks 13a at both ends is preferably half the size of the thermally conductive ceramic blocks 13b located between the power chips 21. This design ensures uniform heat dissipation and current distribution for each power chip 21 in the module, preventing local overheating of the module.

[0058] Preferably, Figure 10 As shown, a plurality of Rg resistors (gate resistors) 14 are provided on the second surface side of the first circuit substrate 11 . The plurality of Rg resistors 14 are provided in one-to-one correspondence with the plurality of power chips 21 and are electrically connected to the gates G of the corresponding power chips 21 .

[0059] Please continue reading Figure 4 and Figure 5 The metal heat dissipation layer 33 of the ceramic substrate 30 is connected to the heat sink 50, which has heat dissipation fins 51. The heat sink 50 can be a traditional fin-type heat sink or a temperature-equalizing heat sink with an evaporation-condensation chamber, which is not limited in this application.

[0060] Preferably, the radiator 50 and its heat dissipating fins 51 both have a hollow cavity structure, which is sealed by the ceramic substrate 30 and preferably forms a negative pressure environment. The inner wall of the cavity is preferably provided with a capillary structure. The capillary structure can be a porous metal layer formed by sintering metal powder (such as copper powder), a capillary woven mesh formed by weaving fiber filaments or metal wires (such as copper wires, aluminum wires), and / or capillary grooves processed on the inner wall of the cavity. Similarly, a capillary structure can also be provided on the metal heat dissipation layer 33.

[0061] When the power module is working, the ceramic substrate 30 forms an evaporation zone and the heat dissipation fins 51 form a condensation zone. Through the evaporation-cooling cycle of the cooling medium, the heat of the ceramic substrate 30 can be further quickly and evenly transferred to all the heat dissipation fins 51.

[0062] The second circuit substrate 40 may be an FR-4 circuit board, preferably having a multi-layered conductive circuit structure to improve the integration of the package module. The second circuit substrate 40 and the first circuit substrate 11 can be considered as a single multi-layer circuit board. The conductive circuits of the second circuit substrate 40 can be electrically connected to the conductive circuits of the first circuit substrate 11, for example, through conductive vias commonly found in multi-layer circuit boards.

[0063] In an embodiment, the second circuit substrate 40 may include a first core board 41 having a first circuit layer and a second circuit layer provided on both side surfaces, respectively, and a second core board 42 having a third circuit layer and a fourth circuit layer provided on both side surfaces, respectively; the second core board 42 is located between the first core board 41 and the chip carrier board 10, and is connected to the first core board 41 and the chip carrier board 10 via an insulating adhesive sheet 43. Circuit elements 44 such as capacitors and resistors may be provided on the first core board 41 and the second core board 42. In addition, a drive component 45 for the power chip 21 and an electrical connector 46 for transmitting control signals may be provided on the circuit substrate 40. A temperature sensor may also be provided on the second circuit substrate 40 to monitor the operating temperature of the module.

[0064] In the embodiment, the second circuit substrate 40 is a multi-layer structure having a first core board 41 and a second core board 42. The circuit elements can be separately arranged on the first core board 41 and the second core board 42. Compared with arranging the power chip 21 and the circuit element 44 on the same surface, the power chip 21 and the circuit element 44 are arranged on different surfaces, and the line length of the power chip 21 and the circuit element 44 can be made smaller. Therefore, the packaging module of the embodiment can reduce the circuit loop area of ​​the module, effectively reduce the on-resistance, reduce the parasitic inductance effect, and thus obtain better efficiency and electrical performance, and at the same time greatly improve the overall power density of the packaging module.

[0065] Example 2

[0066] like Figures 14 to 19 As shown, in embodiment 2, each group of conductive sheets 12 includes only a first conductive sheet 121 and a second conductive sheet 122, the first pin 121a is separately provided with the first conductive sheet 121, the second pin 122a is separately provided with the second conductive sheet 122, and the first pin 121a, the second pin 122a and the third pin 123a are all provided to be exposed from the front side of the second circuit substrate 40 (i.e., the surface away from the chip carrier 10), for example, from the window 40a of the second circuit substrate 40 (see FIG. Figure 15 ) exposed.

[0067] The first pin 121a extends through the second circuit substrate 40 and is electrically connected to the first conductive sheet 121 (e.g., soldered to the first conductive sheet 121). The second pin 122a extends through the second circuit substrate 40 and is electrically connected to the second conductive sheet 122 (e.g., soldered to the second conductive sheet 122). The third pin 123a extends through the second circuit substrate 40, the first circuit substrate 11, and the packaging material layer 60, and is electrically connected to the first conductive portion 321a of the ceramic substrate 30. Specifically, the first conductive portion 321a has a first lateral protrusion 321a1, and the third pin 123a can be soldered to the first lateral protrusion 321a1.

[0068] Further, if Figure 18 and Figure 19 As shown, the first conductive sheet 121 is provided with a transition portion 121c on one side of the second conductive sheet 122, and the transition portion 121c is provided with an intermediate conductive portion 103 electrically connected to the second conductive portion 321b of the ceramic substrate 30, so as to realize the electrical connection between the first conductive sheet 121 and the second conductive portion 321b through the intermediate conductive portion 103. Specifically, as Figure 15 As shown, the second conductive portion 321b has a second lateral protrusion 321b1, and the two ends of the intermediate conductive portion 103 can be welded to the second lateral protrusion 321b1 and the transition portion 121c respectively. The intermediate conductive portion 103 can be a copper block, but is not limited thereto.

[0069] For other descriptions of Example 2, please refer to Example 1 and will not be repeated here.

[0070] Although the present invention has been described above through embodiments, the above embodiments are only used to exemplify the possible implementation schemes of the present invention and are not used to limit the scope of protection of the present invention. Any equivalent substitutions or changes made by those skilled in the art in accordance with the present invention should also be covered by the scope of protection defined by the claims of the present invention.

Claims

1. A power chip embedded packaging module, comprising: A chip carrier, comprising a first circuit substrate and a conductive sheet embedded in the first circuit substrate; A ceramic substrate, disposed on the first surface side of the chip carrier; a second circuit substrate, disposed on the second surface side of the chip carrier; a plurality of power chips packaged between the chip carrier and the ceramic substrate; wherein a first side of the power chip is electrically connected to the first circuit substrate and the conductive sheet, and a second side of the power chip opposite to the first side is electrically connected to the ceramic substrate; A plurality of thermally conductive ceramic blocks, two opposite sides of each ceramic thermally conductive block are respectively connected to the conductive sheet and the ceramic substrate; wherein, along the length direction of the conductive sheet, the thermally conductive ceramic blocks and the power chips are alternately arranged.

2. The power chip embedded package module according to claim 1, wherein: Along the length direction of the conductive sheet, the size of the heat-conducting ceramic block in the middle is twice that of the heat-conducting ceramic blocks at both ends.

3. The power chip embedded package module according to claim 1, wherein: A lateral protrusion embedded in the first circuit substrate is provided on a side edge of the conductive sheet.

4. The power chip embedded package module according to claim 1, wherein: The conductive sheet is provided with pins protruding to the outside of the packaging module.

5. The power chip embedded package module according to claim 1, wherein: The ceramic substrate includes a ceramic core plate and a metal conductive layer and a metal heat dissipation layer respectively arranged on opposite sides of the ceramic core plate. The metal conductive layer is connected to the power chip and the heat-conducting ceramic block.

6. The power chip embedded package module according to claim 5, wherein: The metal heat dissipation layer is connected to a radiator, and the radiator is provided with heat dissipation fins.

7. The power chip embedded package module according to claim 6, wherein: The heat sink is formed with a cavity which is sealed and connected to the ceramic substrate to accommodate a cooling medium, and an inner wall of the cavity is provided with a capillary structure.

8. The power chip embedded package module according to claim 1, wherein: The second circuit substrate includes a multi-layer conductive circuit, and the conductive circuit of the first circuit substrate is electrically connected to the conductive circuit of the second circuit substrate.

9. The power chip embedded package module according to claim 1, wherein: The second circuit substrate is provided with a driving component and circuit elements.

10. The power chip embedded package module according to claim 1, wherein: At least one group of conductive sheets is provided in the first circuit substrate. Each group of conductive sheets includes a first conductive sheet and a second conductive sheet. The thermal conductive ceramic blocks and the power chips are alternately provided on the first conductive sheet and the second conductive sheet.

11. The power chip embedded package module according to claim 1, wherein: A source and a gate are provided on the first side of the power chip, and a drain is provided on the second side of the power chip. The source and the gate are electrically connected to the conductive sheet and the first circuit substrate respectively, and the drain is electrically connected to the ceramic substrate.

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