Low electromagnetic parasitic parameter SiC power semiconductor module based on multi-loop decoupling

Abstract

The invention belongs to the field of module parasitic parameter reduction, and discloses a multi-loop decoupling-based low electromagnetic parasitic parameter SiC power semiconductor module, which is characterized in that an independent copper substrate is adopted as an alternating current copper layer to be laminated on a DBC (Direct Bond Copper) ceramic substrate, and a lower tube chip is flipped and then welded on the lower DBC substrate which is disconnected from a radiator; an upper tube chip and a lower tube chip are connected with a copper substrate above through a copper-molybdenum-copper cushion block, and an alternating current output end of the module is suspended above the DBC substrate through the chips and the cushion block. According to the invention, parasitic capacitance of the module AC output end to the grounding radiator can be almost completely eliminated, power-heat transfer loop capacitive decoupling is realized, common-mode current of a SiC device under high-speed switching is significantly reduced, and electromagnetic interference of a high-frequency switching circuit to a driving circuit and a control system is effectively reduced. And meanwhile, the parasitic inductance of the module is remarkably reduced, and orthogonal decoupling of a signal-power loop magnetic flux space is realized.

Description

Technical Field

[0001] The present invention belongs to but is not limited to the technical field of module parasitic parameter reduction, and in particular relates to a low electromagnetic parasitic parameter SiC power semiconductor module based on multi-loop decoupling. Background Art

[0002] With the growing demand for high frequency and high power density in power electronics, silicon carbide (SiC) devices are gradually replacing traditional silicon devices. Due to their excellent material properties, such as high electron saturation drift velocity and wide bandgap, SiC devices can operate at high frequencies and switching speeds. However, fully leveraging the switching performance of SiC devices presents challenges in power module packaging structure and system design. SiC device package spurious parameters are key factors limiting their switching characteristics and electromagnetic compatibility performance. The electromagnetic structure of traditional SiC device packages is limited by two-dimensional commutation on the surface of a double-sided copper-clad ceramic substrate. This results in large package parasitic inductance and severe inductive coupling in the power-signal loop, which compromises the switching performance of SiC devices. Furthermore, significant electric field coupling exists between the ceramic substrate and the grounded heat sink in traditional package electromagnetic structures, resulting in large package parasitic capacitance and tight capacitive coupling in the power-heat transfer loop. This generates severe common-mode electromagnetic interference (EMI), compromising the long-term reliable operation of SiC devices and power electronic converters.

[0003] Past research has done a lot of work to solve the problem of power module packaging parasitic parameters.

[0004] For example, efforts to reduce package parasitic inductance include:

[0005] (1) Integrate decoupling capacitors within the module and optimize the module DBC layout to control the current flow and achieve mutual cancellation of coupled inductance. This method is limited to optimization on the XY axis plane and has limited degree of freedom of optimization.

[0006] (2) Design a hybrid packaging structure consisting of a PCB and a DBC substrate. This stacked structure can achieve three-dimensional commutation in the Z axis, thereby further reducing the parasitic inductance of the loop. However, this structure does not comprehensively optimize the parasitic capacitance of the module.

[0007] For example, efforts to reduce package parasitic capacitance include:

[0008] (1) Stacking the PCB board on the DBC ceramic substrate to accommodate the AC output terminals reduces the area of ​​the AC copper layer on the DBC ceramic substrate, thereby reducing the parasitic capacitance of the module's AC output terminal to ground. However, due to limitations in chip area, manufacturing process, and insulation spacing, the AC copper layer cannot be further reduced to completely eliminate the parasitic capacitance to ground.

[0009] (2) Removing part of the copper layer at the bottom of the DBC ceramic substrate. Although this method can also reduce the parasitic capacitance of the module to the ground, it conflicts with the heat dissipation of the chip. In order not to excessively affect the heat dissipation, the copper layer directly under the chip cannot be removed, which makes this method also limited by the chip area. In addition, too little copper layer at the bottom of the ceramic substrate will lead to unbalanced forces between the upper and lower parts of the ceramic when heated, causing the substrate to bend downward excessively, which may cause the copper layer to fall off or the ceramic substrate to break.

[0010] (3) An additional ceramic substrate is used as a shielding layer beneath the DBC ceramic substrate. The parasitic capacitance between the AC output terminal and the ground is eliminated by connecting the copper layer between the two substrates to the positive or negative terminal of the power supply. This method will lead to an imbalance in the parasitic capacitance between the positive and negative terminals of the module and the ground, causing differential-mode EMI to convert to common-mode EMI, which may deteriorate the overall switching performance of the module.

[0011] The closest existing technology discloses a double-sided cooling power module structure for SiC devices. It consists of two DBC substrates, each supporting the upper and lower switching devices, electrically connected via metal pillars or brazing. The module's AC output is located between the upper and lower chips, and symmetrical packaging is used to reduce parasitic parameters. While this solution incorporates basic three-dimensional structural optimization ideas, its AC output still exhibits significant coupling with the upper and lower power circuits. It also focuses primarily on thermal management and compact layout, lacking in-depth consideration of the design of electromagnetic suppression paths for common-mode interference and differential-mode noise.

[0012] The main technical problem with this existing technology is that its AC terminal layout fails to effectively decouple from the electromagnetic coupling region of the DC power supply plane. This allows high-frequency dv / dt interference to be easily coupled to the DC side through the parasitic capacitance of the ceramic substrate, triggering common-mode current backflow, which in turn adversely affects the drive signal integrity and system EMI performance. Furthermore, this structure still relies on some bond wires for device interconnection, failing to fully achieve the goal of "debonding wires," limiting the ability to minimize inductance and control package consistency in high-frequency applications. Summary of the Invention

[0013] In view of the problems existing in the prior art, the present invention provides a low electromagnetic parasitic parameter SiC power semiconductor module based on multi-loop decoupling.

[0014] The present invention is implemented as follows: a low electromagnetic parasitic parameter SiC power semiconductor module based on multi-loop decoupling is characterized in that the power module uses a separate copper substrate as an AC copper layer stacked on a DBC ceramic substrate, the lower tube chip is flipped and flip-chip soldered on the DBC substrate below that is in contact with the heat sink, the upper and lower tube chips are connected to the upper copper substrate through copper-molybdenum-copper pads, and the AC output end of the module is suspended above the DBC substrate through the chip and the pad.

[0015] Furthermore, the power module removes the corresponding copper layer below the gate-source driver copper layer on the DBC substrate.

[0016] Furthermore, the main power circuit of the power module no longer requires bonding wires.

[0017] Furthermore, in the power module, the decoupling capacitor is welded on the DBC substrate near the chip to form a three-dimensional commutation circuit. When welding the flip chip, it is necessary to cut grooves on the copper layer below to separate the gate and source of the chip. At the same time, it is necessary to add a solder mask and insulating glue around the chip to facilitate the welding of the flip chip and strengthen the insulation.

[0018] In combination with the above technical solutions and the technical problems solved, the advantages and positive effects of the technical solutions to be protected by the present invention are as follows:

[0019] After modeling the module's packaging parasitic parameters and current loop, the present invention proposes a new SiC power semiconductor module using a flip-chip and a laminated AC copper substrate. Because the AC copper layer is far away from the grounded heat sink at the bottom of the DBC substrate and has a DC copper layer as a natural shielding layer, the parasitic capacitance between the module's AC output and the grounded heat sink can be almost completely eliminated, achieving capacitive decoupling of the power-heat transfer loop, significantly reducing the common-mode current under high-speed switching of SiC devices, and effectively reducing the electromagnetic interference of high-frequency switching circuits on drive circuits and control systems. At the same time, decoupling capacitors are integrated nearby in the module to form a three-dimensional commutation structure on the Z axis with the laminated structure, significantly reducing the module's parasitic inductance and achieving spatial orthogonal decoupling of the signal-power loop magnetic flux.

[0020] Compared with the prior art, the present invention has the following advantages:

[0021] (1) The parasitic inductance optimization of the present invention is not limited to the plane of the XY axis, and has a higher degree of freedom, which can achieve better optimization effects;

[0022] (2) The present invention optimizes the parasitic capacitance of the module to the ground while optimizing the parasitic inductance of the module;

[0023] (3) The present invention is not limited by the chip area and separates the AC copper layer from the bottom DBC ceramic substrate, which can completely eliminate the parasitic capacitance between the module AC output terminal and the ground;

[0024] (4) The present invention does not substantially change the heat dissipation copper layer under the chip, resulting in better heat dissipation of the chip;

[0025] (5) The present invention does not require an additional DBC ceramic substrate, which is lower in cost. At the same time, it can maintain the symmetry of the parasitic capacitance between the positive and negative ends of the module and the ground, thereby eliminating the influence of differential mode EMI on common mode EMI.

[0026] The technical solution of the present invention solves the technical problem of how to reduce the parasitic capacitance between the AC terminal of the power module and the ground to zero without being limited by the area of ​​the power chip.

[0027] The technical solution of the present invention overcomes the technical prejudice that the AC copper layer of a single-sided power module can only be on the bottom DBC ceramic substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 This is the current loop modeling of the silicon carbide power module provided by the embodiment of the present invention;

[0029] Figure 2 Two packaging structures of the silicon carbide power module provided by the embodiments of the present invention are: (a) a traditional planar structure, and (b) a flip-chip stacked structure proposed by the present invention;

[0030] Figure 3 This is a three-dimensional model of the novel power module provided by an embodiment of the present invention: (a) bottom DBC substrate part, (b) top copper substrate part, (c) assembled complete module;

[0031] Figure 4 This is a physical picture of a laboratory sample of a new power module provided by an embodiment of the present invention;

[0032] Figure 5 This is a physical picture of the power module switch performance test platform provided by an embodiment of the present invention;

[0033] Figure 6 This is a circuit diagram of a power module switch performance test platform provided by an embodiment of the present invention;

[0034] Figure 7 This is a comparison diagram of the double pulse test waveforms of the module proposed in the present invention and the traditional module provided by the embodiment of the present invention: (a) shutdown transient, (b) turn-on transient;

[0035] Figure 8 This is a comparison diagram of continuous test waveforms of the module proposed in the present invention and a traditional module provided in an embodiment of the present invention;

[0036] Figure 9 This is a test common-mode current spectrum diagram of the module proposed by the present invention and a traditional module provided by an embodiment of the present invention;

[0037] In the figure: 1, oscilloscope; 2, DSP; 3, DC power supply; 4, LISN; 5, driving power supply; 6, C DC ; 7. SSCB; 8. Driver board; 9. Power module; 10. Load inductor. DETAILED DESCRIPTION

[0038] In order to make the purpose, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0039] Traditional SiC half-bridge power modules mostly mount two transistors side by side on the same DBC substrate. The AC node is then routed across the two chips via long wires or busbars. This creates a horizontally distributed commutation loop, forcing the current to bypass each other's source / drain. This passively amplifies the equivalent loop area and results in parasitic inductances as high as tens of nanowatts. When the device hard switches, the combined effects of di / dt and high parasitics cause a sharp increase in commutation overshoot, voltage spikes, and dv / dt-coupled noise. This slow drive ramp-up, in turn, creates a vicious cycle of switching losses and thermal mismatch. While engineers have attempted to compress the loop using methods like double-layer busbars and copper-clad ceramic laminates, two-dimensional planar topologies struggle to avoid the additional self- and mutual inductance introduced by the "bends" of the traces, a core bottleneck for existing solutions.

[0040] The proposed multi-loop decoupled package changes this approach: the top-half-bridge transistor remains mounted facing upward, while the bottom-half-bridge transistor is flipped and mounted face-down. The drains of the two are directly shorted vertically with a copper-molybdenum-copper (CMC) metal pad. The drain potential then flows upward along a vertical channel to the copper substrate, which in turn serves as the AC output terminal. The rectifier current is thus compressed into a three-dimensional "column" stream running along the z-axis, rather than a laterally meandering "frame" loop. The rotationally symmetric layout also makes the two branches mirror each other, canceling transient currents in the plane and significantly reducing inter-turn coupling inductance.

[0041] A sandbox-like "common-mode capacitor" (CAC) is formed between the DBC ceramic and the copper substrate above. Its lower node is isolated from the module ground, while its upper node directly withstands dv / dt stress. Because the commutation differential-mode loop is compressed, the dv / dt-induced displacement current is mostly confined within the copper substrate-DBC, shortening the common-mode current path to the heat sink and external shield. Compared to the heatsink-to-case coupling common in traditional packaging, this solution confines the electromagnetic field within the device, reducing the equivalent capacitance to ground by approximately 40–60%. In mid- and high-frequency PWM scenarios, radiated EMI spikes can be measured to be reduced by 6–8dBμV.

[0042] In addition to carrying high current, the CMC pad also serves as a thermal path and mechanical buffer. The Mo interlayer has a thermal expansion coefficient between SiC and Cu. The temperature differential between the chip and the copper substrate at the moment of shutdown is absorbed through the plastic deformation of the Mo, effectively reducing solder fatigue caused by power cycling. This shortens the vertical heat conduction path and improves chip junction temperature uniformity. Under 100kHz switching stress at a junction temperature of 175°C, power cycle life tests show a nearly doubled lifespan compared to a planar package of the same specification, meeting the automotive-grade ten-year lifespan specification.

[0043] In terms of dynamic operating principle, at the moment of commutation, the drain current of the SH and SL devices is directed into the copper substrate via the CMC vertical interconnect. Its return path is then short-circuited back through the PCB and external busbars, reducing the equivalent Lσ to 3–5 nH. At this point, the dv / dt can be safely increased to 50–60 kV / μs without overshoot. Residual current to ground is slowly discharged along the minimum capacitance path created by the package's inner wall and the heat sink, preventing loop oscillation on the PCB plane. This shortens the drive waveform, reducing switching losses by approximately 20%, making high-frequency nitride gate drive strategies more feasible.

[0044] The multi-loop decoupled three-dimensional topology "folds" and integrates electrical, magnetic, and thermal paths within the package: the differential-mode commutation loop is compressed, the common-mode discharge loop is interrupted, and thermal-mechanical matching is buffered by the CMC. This structure essentially upgrades the power module from a passive suppression mode of "plane-routing-external compensation" to an active reconfiguration mode of "vertical-symmetrical-internal clamping." This provides a packaging paradigm that balances efficiency, reliability, and electromagnetic compatibility for high-power density scenarios such as next-generation SiC automotive OBCs and traction inverters.

[0045] In order to analyze the influence of parasitic parameters in power modules and optimize the packaging structure, it is first necessary to consider the various parasitic parameters in the module and establish a current loop model of the system. Taking a single-phase half-bridge inverter as an example, when the bridge arm composed of the power module switches, the current conduction path is as follows: Figure 1 The DC+, DC- and AC copper layers of the power module will form a parasitic capacitance C to the ground with the heat sink. + 、C - and C AC , the common mode current will flow to the ground through these parasitic capacitors. Since the voltage change mainly occurs at the AC output end of the power module, the parasitic capacitance of the AC copper layer to the ground plays a decisive role in the common mode EMI of the power module. AC It is the primary goal to optimize the power module packaging structure. In addition, there is also a parasitic inductance L in the main power circuit. + and L - When the differential mode current oscillates, they will cause the voltage on the DC+ and DC- terminals of the power module to oscillate. This will additionally introduce a voltage from the capacitor C + and C - The total common mode current from the power module to the ground is i cm The calculation formula is:

[0046]

[0047] Among them, i dm is the differential mode current of the power module, v ac is the AC output voltage of the power module, vdc is the DC bus voltage at the positive and negative terminals of the power module. This shows the conversion relationship between differential-mode current and common-mode current. Therefore, optimizing the module packaging structure also requires maintaining the symmetry of the parasitic inductance and capacitance at the positive and negative terminals so that the common-mode currents from the positive and negative terminals to ground can cancel each other out.

[0048] The embodiment of the present invention provides a novel SiC power semiconductor module using a flip chip and a laminated AC copper substrate. Figure 2 (b) and Figure 3 The packaging structure and three-dimensional model of the new module are shown respectively. Figure 2 (a) is different from the traditional planar module. The proposed new module uses a separate copper substrate as the AC copper layer stacked on the DBC ceramic substrate. In order not to affect the heat dissipation of the chip, the lower tube chip is flipped over and soldered on the DBC substrate below that is disconnected from the heat sink, which has almost the same heat dissipation conditions as the upper tube chip. Then the upper and lower tube chips are connected to the upper copper substrate through copper-molybdenum-copper pads, and the AC output end of the module is suspended above the DBC substrate through the chip and the pad. This structure increases the distance between the module's AC output end and the ground, and at the same time, the DC+ and DC- copper layers below can act as a shielding layer, so the module's C AC This reduces the capacitance to zero, thereby blocking the common-mode current's path to ground and effectively suppressing EMI from the power module. Furthermore, to prevent the ground capacitance of the gate-source driver copper layers on the DBC substrate from affecting EMI, the corresponding copper layers beneath these layers are removed. These copper layers are relatively small and have little impact on the module's heat dissipation.

[0049] The main power circuit of the power module no longer requires bonding wires, which can improve the reliability of the power module. In addition, the decoupling capacitor is soldered to the DBC substrate near the chip, forming a three-dimensional commutation circuit with a smaller loop area, which can reduce the parasitic inductance of the module to less than 2nH (based on Q3D simulation results). When soldering a flip chip, it is necessary to cut grooves in the lower copper layer to separate the gate and source of the chip. At the same time, it is necessary to add a solder mask and insulating glue around the chip to facilitate soldering of the flip chip and strengthen the insulation.

[0050] This power module is based on a flip-chip soldering process. By flipping the lower tube chip and placing it directly on a DBC ceramic substrate in contact with the heat sink, the path length from the device to the heat source is significantly shortened. The upper and lower tubes are no longer connected by traditional wire bonding. Instead, copper-molybdenum-copper (CMC) metal pads are used to achieve vertical electrical connection, and the AC output end is vertically led out between the upper and lower chips, thereby effectively optimizing the electromagnetic compatibility path structure inside the package.

[0051] By symmetrically placing the high-side transistor (SH) and the low-side transistor (SL) with a common source and using a copper substrate stack to create the AC-side conduction path, this structure significantly reduces the effective area of ​​the differential-mode current loop (S_H-S_L-AC). Since EMI is primarily proportional to the area and path length of high-frequency current loops, this design mitigates EMI spikes caused by current di / dt at the source through structurally organized routing.

[0052] Unlike traditional SiC modules that rely heavily on bond wires to connect the chip to external pins, this structure completely eliminates wire bonds in the main power path (wire-bond-less). Instead, a thick copper layer and metal pads form a low-inductance, low-impedance vertical current path. This path exhibits minimal loop self-inductance at high switching frequencies, significantly suppressing common-mode interference coupling caused by dv / dt and reducing overvoltage oscillations.

[0053] The module's AC output is designed to be suspended above the DBC ceramic substrate via CMC pads, eliminating interference paths that could directly couple with the DC+ and DC- copper planes. This three-dimensional structure physically strengthens the electromagnetic isolation between the AC and DC supply sides, preventing high-frequency common-mode currents from coupling through the ceramic substrate to the DC copper foil, which could cause electromagnetic backflow, thereby suppressing the propagation of common-mode noise.

[0054] To further reduce the induction of drive signal disturbances, the package features a copper layer cut below the gate drive signal layer (GE) on the DBC substrate. This section of copper is removed to prevent the formation of a high-frequency closed-loop coupling path. This structure suppresses parasitic capacitive coupling between the gate drive signal and the main current path, effectively mitigating the risk of common-mode interference contamination of the gate control signal during high-speed switching.

[0055] Because the bottom tube chip is directly attached to the bottom of the DBC and thermally connected to the heat sink, its thermal resistance path is greatly shortened, thermally isolated from the simultaneously suspended AC terminal, ensuring maximum heat dissipation efficiency. In terms of structural integration, this package supports multi-module splicing layout and can be directly integrated into high-frequency drivers and motor controllers. It exhibits excellent electro-thermal coupling performance and is suitable for high-density power conversion modules in the aviation, rail transit, and new energy vehicle fields.

[0056] Based on Rohm's commercial SiCMOSFET chip S4661MFFDZC, the following Figure 4The new module sample is shown. The performance of the proposed new module and the traditional module is compared through double pulse test and continuous test. To ensure the fairness of the comparison, the traditional power module is made using the same size DBC substrate as the proposed module, with decoupling capacitors integrated in the same position and the DC+ and DC- copper layers adjusted to make their areas symmetrical. The test platform and the corresponding circuit schematic are shown in the figure. Figure 5 and Figure 6 The test platform is a single-phase half-bridge inverter built based on the fabricated power module. The common-mode and differential-mode EMI currents of the power module are measured using a commercial LISN device.

[0057] First, a double-pulse test was performed to compare the transient EMI currents of the two power modules during switching. During the test, the load inductor was connected in parallel with the SiC chip in the high-side bridge. The double-pulse test was conducted at a bus voltage of 600V and a load current of 50A. Figure 7 The experimental waveforms of the AC terminal voltage and common-mode current to ground during the turn-off and turn-on transients of the two modules were compared. The turn-on and turn-off voltage waveforms of the two modules are similar, but there are significant differences in the common-mode current waveforms. Compared with the traditional module, the proposed module reduces the common-mode current peak from 1.7A to 0.3A during the turn-off transient and from -1.5A to -0.2A during the turn-on transient. At the same time, the oscillation of the common-mode current is also much smaller. This verifies that the proposed new power module with a flip-chip and stacked packaging structure can effectively reduce the module's stray capacitance to ground, thereby achieving capacitive decoupling of the power-heat transfer loop, significantly reducing the common-mode current under high-speed switching of SiC devices, and effectively reducing the electromagnetic interference of high-frequency switching circuits on drive circuits and control systems.

[0058] Finally, a DSP board was used to perform SPWM control on the single-phase half-bridge inverter and conduct a continuous comparative test. In the continuous test, the test bus voltage was 600V, the load sinusoidal current peak was 25A, the base frequency was 500Hz, the switching frequency was 20kHz, and air cooling was used. After the load current entered the steady state, the waveform of the continuous experiment was as follows: Figure 8 As shown in Figure 2. When using these two modules, the system's AC terminal voltage and load current waveforms are almost identical. However, there is still a significant difference in the common-mode current. Compared with the traditional module, the common-mode current peak of the proposed module is reduced from 2A to 0.46A. In addition, the common-mode current waveform in the continuous experiment is Fourier transformed to obtain the common-mode current spectrum, as shown in Figure 2. Figure 9 As shown in Figure 2, within the high-frequency range corresponding to the switching process, the proposed module can reduce the amplitude of the common-mode current by 40 dB. Continuous experimental results further demonstrate the effectiveness and reliability of the new power module proposed in this paper.

[0059] Example A

[0060] Four 650V / 40mΩ third-generation SiC MOSFETs are selected and connected in parallel to form a 200A-rated half-bridge. A top-mount SH and flip-chip SL are mounted on an AlN-DBC (0.32mm thick, 0.3mm Cu). Their drains are vertically interconnected using a 6mm×6mm×2mm CMC pad. A 22mm×26mm×2mm solid copper plate is welded atop the pad as the AC terminal. The double-layer stacked DC+ / DC- busbars are partially interlocked with the DBC copper layer, reducing the equivalent differential-mode loop area to 28mm. 2 The stray inductance is measured at 3.1nH. The back of the DBC is vacuum brazed to a 3mm oxygen-free copper heat sink, then screwed to the water cooling plate via a graphite sheet and phase change pad composite for thermal conductivity. The CAC is approximately 130pF, and the inter-chip capacitance to ground is 45% lower than that of traditional planar packages.

[0061] Double-pulse tests at 400V and 55kHz PWM conditions show that at 100A, Eon / Eoff are 2.8 / 2.4mJ, respectively, a 21% decrease compared to the same chip planar package; dv / dt can be increased to 60kVμs -1 The voltage overshoot is less than 5%. Based on the CISPR-25 Class 5 radiated EMI test, the average reduction in the 30–300MHz range is 7dBμV. Power cycle (25–125A, ΔTj55K, 100kHz) 3.5×10 5 After the test, the resistance drift of the solder layer is less than 5mΩ, and the estimated service life meets the 10-year OBC requirement of the automotive standard.

[0062] Example B

[0063] For 800V traction inverters, two 1200V / 25mΩ SiC MOSFETs (10mm×10mm) are used to form a 300A half-bridge. The DBC is replaced with Si3N4-based ceramic (0.40mm thick, Cu0.4mm) to improve mechanical strength. The CMC spacer is increased in size to 10mm×10mm×2.5mm, and four 47nF / 630VC0G ceramic decoupling capacitors are directly embedded on top of it to achieve vertical drain-to-copper substrate bypass. The AC terminals utilize 3mm-thick nickel-plated copper with M6 through-holes to withstand a peak of 1.5kA. The busbar is modified to a three-layer coupled structure (Cu0.6 / PI0.1 / Cu0.6 / PI0.1 / Cu0.6mm), reducing stray inductance to 2.4nH. A copper shield is embedded in the module housing to control CAC to 110pF.

[0064] Under 800V busbar and 40kHz modulation, Eon / Eoff are 4.5 / 4.0mJ respectively at 200A current; dv / dt is 72kVμs -1The shutdown overshoot is 4%. Thermal imaging shows a maximum chip junction temperature of 154°C (cold plate 65°C) with a temperature difference of <9K when the 150kVA three-phase inverter is running at full load. Conducted EMI (150kHz–10MHz) is, on average, 5–6dBμV lower than competing modules. After 1000 cycles of 125°C / -40°C temperature cycling and 10kV ESD shock testing, the housing-to-copper substrate insulation resistance remains above 1GΩ, validating the electromagnetic compatibility and reliability advantages of this 3D decoupled package in high-voltage, high-current scenarios.

[0065] The above description is only a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any modifications, equivalent substitutions and improvements made by any technician familiar with this technical field within the technical scope disclosed by the present invention and within the spirit and principles of the present invention should be covered by the scope of protection of the present invention.

Claims

1. A low electromagnetic parasitic parameter SiC power semiconductor module based on multi-loop decoupling, characterized in that: include: A DBC ceramic substrate, a copper substrate on the DBC ceramic substrate, an upper tube chip on the DBC ceramic substrate, and a lower tube chip flipped on the DBC ceramic substrate. The upper tube chip and the lower tube chip are electrically connected via a copper-molybdenum-copper metal pad. The copper substrate forms the AC output end of the module, and the AC output end is arranged above the DBC ceramic substrate.

2. The power module according to claim 1, wherein: The upper tube chip and the lower tube chip form a common source topology and are arranged on opposite sides of the DBC ceramic substrate to form a symmetrical current path.

3. The power module according to claim 1, wherein: The copper-molybdenum-copper metal pad in the packaging structure connects the drain of the upper tube chip and the drain of the lower tube chip in the vertical direction, and is connected to the copper substrate to form a vertical current path.

4. The power module according to claim 1, wherein: The lower tube chip is directly arranged on the DBC ceramic substrate in contact with the radiator, and is thermally connected through a brazing process.

5. The power module according to claim 1, wherein: The packaging structure does not include bonding wires on the main power path, and the electrical connection between the power devices is achieved through metal pads and thick copper structures.

6. The power module according to claim 1, wherein: In the copper foil layer arranged on the DBC ceramic substrate, the copper layer located directly below the gate drive lead is partially cut away to reduce parasitic capacitance coupling.

7. The power module according to claim 1, wherein: The copper substrate is suspended above the DBC ceramic substrate as an AC terminal through a metal column or a copper block to avoid direct electromagnetic coupling with the DC input end.

8. The power module according to claim 1, wherein: The AC terminal is connected to the output end of the upper tube chip through a metal pad, and the metal pads are symmetrically arranged on both sides of the chip to maintain the symmetry of the AC current path.

9. The power module according to claim 1, wherein: A thermal interface material is provided between the packaging structure and the heat sink, the heat conduction path is conducted only downward from the lower tube chip, and the AC output end is insulated to avoid thermal coupling interference.

10. The power module according to claim 1, wherein: The packaging structure supports the parallel installation of multiple modules, with the DC input and AC output of each module being led out separately, and is suitable for high-density integration of three-level or multi-phase inverter systems.

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