Preparation method of through silicon via interconnection structure

Abstract

The invention discloses a preparation method of a silicon through hole interconnection structure, and the preparation method of the silicon through hole interconnection structure comprises the steps: providing a silicon wafer which is provided with a through hole, and the through hole is filled with conductive metal; temporarily bonding the upper surface of the silicon wafer and the upper slide; thinning one side, far away from the upper slide glass, of the silicon wafer based on a first thinning mode so as to enable the thinned silicon wafer to reach a preset thickness; the side, away from the upper slide, of the silicon wafer reaching the preset thickness is thinned on the basis of a second thinning mode, so that the thinned silicon wafer reaches the target thickness, and the thinning speed of the first thinning mode is larger than that of the second thinning mode; and performing temporary bonding on the surface, far away from the upper slide glass, of the silicon wafer reaching the target thickness and the lower slide glass, and performing de-bonding on the thinned silicon wafer and the upper slide glass to obtain the through silicon via interconnection structure. According to the method, a thin silicon wafer can be obtained, so that a vertical heat dissipation path is shortened.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor technology, and particularly relates to a preparation method of a through silicon via interconnection structure. BACKGROUND

[0002] In the related art, a relatively thick silicon wafer (thickness greater than 100 pm) is usually used in the through silicon via technology, which may provide mechanical stability in some scenarios, but the relatively thick substrate increases the distance of heat transfer from the inside of the stacked chip to the heat dissipation structure due to the elongation of the vertical heat dissipation path, resulting in an increase in thermal resistance and exacerbating the risk of local hot spots. SUMMARY

[0003] The present application aims to at least partially solve one of the technical problems in the related art. To this end, one object of the present application is to provide a preparation method of a through silicon via interconnection structure, which uses two thinning methods to thin the silicon wafer to obtain a relatively thin silicon wafer, thereby shortening the vertical heat dissipation path and reducing the risk of local hot spots.

[0004] To achieve the above object, according to an embodiment of the present application, a preparation method of a through silicon via interconnection structure is provided, which comprises: providing a silicon wafer, wherein the silicon wafer has a through hole filled with a conductive metal; temporarily bonding an upper surface of the silicon wafer and an upper carrier; thinning one side of the silicon wafer away from the upper carrier based on a first thinning method to make the thinned silicon wafer reach a preset thickness; thinning the one side of the silicon wafer reaching the preset thickness away from the upper carrier based on a second thinning method to make the thinned silicon wafer reach a target thickness, wherein the thinning speed of the first thinning method is greater than the thinning speed of the second thinning method; temporarily bonding a surface of the silicon wafer reaching the target thickness away from the upper carrier and a lower carrier, and debonding the thinned silicon wafer and the upper carrier to obtain the through silicon via interconnection structure.

[0005] According to the preparation method of the through silicon via interconnection structure provided by the embodiment of the present application, the silicon wafer is provided, wherein the silicon wafer has a through hole filled with a conductive metal; the upper surface of the silicon wafer is temporarily bonded with the upper carrier, and one side of the silicon wafer away from the upper carrier is thinned based on the first thinning method to make the thinned silicon wafer reach a preset thickness, and one side of the silicon wafer reaching the preset thickness away from the upper carrier is thinned based on the second thinning method to make the thinned silicon wafer reach a target thickness, wherein the thinning speed of the first thinning method is greater than the thinning speed of the second thinning method, and the surface of the silicon wafer reaching the target thickness away from the upper carrier is temporarily bonded with the lower carrier, and the thinned silicon wafer and the upper carrier are debonded to obtain the through silicon via interconnection structure. Thus, the silicon wafer is thinned by using two thinning methods to obtain a relatively thin silicon wafer, thereby shortening the vertical heat dissipation path and reducing the risk of local hot spots.

[0006] According to one embodiment of the present application, the temporary bonding of the upper surface of the silicon wafer and the upper carrier includes: applying bonding glue on the upper surface of the silicon wafer or the surface of the upper carrier; bonding the upper surface of the silicon wafer and the surface of the upper carrier, and pressing the bonded silicon wafer and the upper carrier; and irradiating the pressed silicon wafer and the upper carrier with an ultraviolet light source to make the bonding glue photocured.

[0007] According to one embodiment of the present application, the wavelength range of the ultraviolet light source is 300-400 nm, and the intensity of the ultraviolet light source is 100-10000 mW / cm 2 .

[0008] According to one embodiment of the present application, the thickness of the bonding glue after curing is 1-50 μm.

[0009] According to one embodiment of the present application, the thinning speed of the first thinning method is 60-300 μm / min, and the thinning speed of the second thinning method is 1-60 μm / min.

[0010] According to one embodiment of the present application, the target thickness is 5-100 μm.

[0011] According to one embodiment of the present application, the thickness difference between the preset thickness and the target thickness is 10-30 μm.

[0012] According to one embodiment of the present application, before the temporary bonding of the surface of the silicon wafer away from the upper carrier and the lower carrier after reaching the target thickness, the method further includes: forming a redistribution layer on the surface of the silicon wafer away from the upper carrier after reaching the target thickness, wherein the redistribution layer is connected with the through hole; and depositing solder on the surface of the redistribution layer away from the silicon wafer to form a micro-bump.

[0013] According to one embodiment of the present application, the forming of the redistribution layer on the surface of the silicon wafer away from the upper carrier after reaching the target thickness includes: depositing a first insulating medium layer on the surface of the silicon wafer away from the upper carrier after reaching the target thickness; etching the first insulating medium layer to form a circuit pattern, wherein the circuit pattern exposes the through hole; and filling metal in the circuit pattern to obtain the redistribution layer.

[0014] According to one embodiment of the present application, a silicon wafer is provided, including: etching a patterned initial silicon wafer to form a through hole; depositing a second insulating medium layer on the surface of the initial silicon wafer and in the through hole; depositing a barrier layer on the surface of the second insulating medium layer away from the initial silicon wafer, the inner wall of the through hole and the bottom of the through hole, and depositing a seed layer on the surface of the barrier layer away from the second insulating medium layer; filling a conductive metal on the surface of the seed layer away from the barrier layer; and removing the barrier layer, the seed layer and the conductive metal on the surface of the initial silicon wafer to obtain the silicon wafer.

[0015] Additional aspects and advantages of the present application will be made apparent from the following description. BRIEF DESCRIPTION OF DRAWINGS

[0016] Figure 1 is a flowchart of a method for manufacturing a through-silicon via interconnect structure according to an embodiment of the present application;

[0017] Figures 2 to 11 is a structural diagram of a method for manufacturing a through-silicon via interconnect structure according to an embodiment of the present application;

[0018] Figure 12 is a flowchart of a method for manufacturing a through-silicon via interconnect structure according to a specific embodiment of the present application. DETAILED DESCRIPTION

[0019] Embodiments of the present application are described in detail below with reference to the accompanying drawings, in which like or similar elements are denoted by the same or similar reference signs, and examples of the embodiments are shown in the drawings. The embodiments described below by reference to the drawings are exemplary and are intended to explain the present application, and are not to be understood as limiting the present application.

[0020] It should be noted that the present application is made by the inventors' understanding and research on the following problems:

[0021] As the transistor size approaches the physical limit, the traditional planar expansion method faces challenges, and vertical interconnection technologies such as TSV (Through-Silicon Via) provide a new three-dimensional integration scheme. TSV realizes electrical connection in chip stacking by making micro-holes in the silicon wafer and filling them with conductive materials. The typical TSV manufacturing process mainly includes etching, insulating dielectric layer, diffusion barrier layer, seed layer deposition, metal filling, wafer bonding, wafer thinning, etc. Modern electronic devices are developing towards high performance, low power consumption, lightweight and miniaturization, which puts forward new requirements for the performance and integration of TSV.

[0022] In the related art, a relatively thick silicon wafer (thickness greater than 100 μm) is used in the through-silicon via technology, which may provide mechanical stability in some scenarios, but the relatively thick silicon wafer has an impact on performance, process feasibility and application flexibility. Specifically, a thicker substrate requires more time for deep hole etching, increasing the process cost; the deposition of the insulating layer / barrier layer is difficult, resulting in poor coverage in the deep hole, which may cause leakage or breakdown problems; the vertical heat dissipation path is lengthened, and the thicker substrate increases the distance for heat to transfer from the inside of the stacked chips to the heat dissipation structure, resulting in increased thermal resistance and exacerbating the risk of local hot spots.

[0023] Based on this, the embodiment of the present application provides a preparation method of a through silicon via interconnection structure, which adopts two thinning methods to thin the silicon wafer to obtain a thinner silicon wafer, thereby shortening the vertical heat dissipation path and reducing the risk of local hot spots.

[0024] The preparation method of the through silicon via interconnection structure of the embodiment of the present application is described below with reference to the accompanying drawings.

[0025] Figure 1 is a flowchart of the preparation method of the through silicon via interconnection structure according to an embodiment of the present application. As shown in Figure 1 , the preparation method of the through silicon via interconnection structure comprises:

[0026] S101, providing a silicon wafer 201 as shown in Figure 2 , wherein the silicon wafer 201 has a through hole 202, and the through hole 202 is filled with a conductive metal.

[0027] Specifically, the silicon wafer 201 comprises the through hole 202, wherein the depth of the through hole 202 ranges from 2 to 200 μm, the diameter ranges from 1 to 50 μm, and the conductive metal can be Cu (copper), Ti (titanium), W (tungsten), etc. Therefore, the depth of the through hole 202 is short, which reduces the overall thickness after stacking, effectively improves the signal transmission speed, reduces the power consumption, and can shorten the etching time, reduce the etching process cost, further reduce the deposition difficulty of the insulating layer / barrier layer, and improve the coverage rate in the hole.

[0028] S102, temporarily bonding the upper surface of the silicon wafer 201 and the upper carrier 203.

[0029] Specifically, the upper surface of the silicon wafer 201 and the upper carrier 203 are temporarily bonded to form a bonded wafer as shown in Figure 3 , and the upper carrier 203 can provide support for the subsequent thinning process to avoid damage to the silicon wafer 201, wherein the upper carrier 203 can be a transparent carrier, and the material of the transparent carrier includes quartz, silicate, borosilicate, sapphire, glass, plastic, etc.

[0030] S103, thinning the side of the silicon wafer 201 away from the upper carrier 203 based on a first thinning method, so that the thinned silicon wafer 201 reaches a preset thickness.

[0031] S104, thinning the side of the silicon wafer 201 away from the upper carrier 203 based on a second thinning method, so that the thinned silicon wafer 201 reaches a target thickness, wherein the thinning speed of the first thinning method is greater than the thinning speed of the second thinning method.

[0032] Optionally, in some embodiments, the first thinning method has a thinning speed of 60-300 μm / min, and the second thinning method has a thinning speed of 1-60 μm / min.

[0033] Specifically, the first thinning method has a fast thinning speed and is difficult to control, so that the thickness of the silicon wafer 201 may be too large or too small when the first thinning method is used for thinning. The second thinning method has a slow thinning speed and can accurately control the thickness of the silicon wafer 201, but the thinning speed is too slow, which requires more thinning time and increases the process cost. Therefore, the two thinning methods are combined to thin the silicon wafer 201. First, the first thinning method is used to thin the side of the silicon wafer 201 away from the upper carrier 203 to a preset thickness, and then the second thinning method is used to continue to thin the silicon wafer 201 to a target thickness to expose the conductive metal in the through hole 202, so as to obtain a structure as shown in Figure 4

[0034] For example, in some embodiments, the target thickness is 5-100 μm.

[0035] That is, the silicon wafer 201 can be thinned to 5-100 μm by using the above two thinning methods in combination, so as to greatly reduce the thickness of the silicon wafer 201 and greatly shorten the vertical heat dissipation path.

[0036] In an alternative embodiment, the surface of the silicon wafer 201 away from the upper carrier 203 reaching the target thickness also needs to be planarized to obtain a flat silicon wafer 201, thereby improving the performance of the silicon wafer 201.

[0037] S105, temporarily bonding the surface of the silicon wafer 201 away from the upper carrier 203 reaching the target thickness to the lower carrier 204, and debonding the thinned silicon wafer 201 from the upper carrier 203 to obtain a through-silicon via interconnection structure.

[0038] Specifically, because the silicon wafer 201 with the target thickness is too thin, the lower carrier 204 is needed to support the subsequent preparation of the chip, as shown in Figure 5 The surface of the silicon wafer 201 with the target thickness away from the upper carrier 203 is temporarily bonded to the lower carrier 204 through the adhesive layer 214. The silicon wafer 201 with the target thickness and the lower carrier 204 can be temporarily bonded by ultraviolet light curing bonding, thermal bonding, laser bonding, etc. The material of the lower carrier 204 includes silicon, silicon carbide, silicon nitride, quartz, silicate, borosilicate, sapphire, glass, plastic, etc. Then the silicon wafer 201 with the target thickness and the upper carrier 203 can be debonded by pyrolysis bonding, hydrolysis bonding, chemical solvent debonding, laser debonding, etc. to obtain a structure as shown in​Figure 6 The super-thin through-silicon via 202 interconnection structure is shown.

[0039] In the above embodiment, by adopting the first thinning mode and the second thinning mode in combination, the silicon wafer can be thinned to below 100 μm to obtain a super-thin silicon wafer, the vertical heat dissipation path is shortened, the local hot spot risk is reduced, and the process cost is reduced without increasing the thinning time.

[0040] In some embodiments, as shown, the upper surface of the silicon wafer 201 is temporarily bonded with the upper carrier 203, including: coating a bonding glue 205 on the upper surface of the silicon wafer 201 or the surface of the upper carrier 203; bonding the upper surface of the silicon wafer 201 with the surface of the upper carrier 203, and pressing the bonded silicon wafer 201 and the upper carrier 203; and irradiating the pressed silicon wafer 201 and the upper carrier 203 with an ultraviolet light source to make the bonding glue 205 photocured. Figure 3

[0041] Specifically, the bonding glue 205 can be uniformly coated on the upper surface of the silicon wafer 201 or the single-sided surface of the upper carrier 203, and the bonding glue 205 can be UV (ultraviolet) curing glue, including: acrylic, epoxy, etc. The bonding glue 205 is a debondable bonding glue 205, which can be removed by debonding subsequently. The upper surface of the silicon wafer 201 is bonded with the surface of the upper carrier 203, so that the bonding glue 205 is located between the two, and then the silicon wafer 201 and the upper carrier 203 are pressed to make them tightly bonded. Further, the air bubbles in the bonding glue 205 can be extracted to make the bonding glue 205 more dense. Then the silicon wafer 201 and the upper carrier 203 are irradiated with an ultraviolet light source to make the bonding glue 205 photocured to complete the bonding.

[0042] Optionally, the pressure range of the pressing is 10-1000 g / cm 2 , the pressing time is 10-600 s. The wavelength range of the ultraviolet light source is 300-400 nm, the intensity of the ultraviolet light source is 100-10000 mW / cm 2 , and the irradiation time of the ultraviolet light source is 10-1000 s. The thickness of the cured bonding glue 205 is 1-50 μm.

[0043] In the above embodiment, by adopting the temporary bonding method of the ultraviolet light source for the silicon wafer and the upper carrier, a bonded wafer with good flatness and bonding stability can be obtained, thereby providing good support for the subsequent thinning of the silicon wafer.

[0044] In some embodiments, the thickness difference between the preset thickness and the target thickness is 10-30 μm.

[0045] ​It can be understood that the first thinning method is used for thinning, which may cause uneven thickness due to device vibration, temperature change or stress release, so the preset thickness needs to be reserved with a certain margin from the target thickness, and then the second thinning method is used for fine thinning to thin the silicon wafer 201 to the target thickness, so as to obtain the ultra-thin silicon wafer 201.

[0046] In some embodiments, before the silicon wafer 201 reaching the target thickness is temporarily bonded away from the surface of the upper carrier 203 to the lower carrier 204, the method further comprises: forming a redistribution layer 206 on the surface of the silicon wafer 201 reaching the target thickness away from the upper carrier 203, wherein the redistribution layer 206 is connected with the through hole 202; and depositing solder on the surface of the redistribution layer 206 away from the silicon wafer 201 to form micro-bumps 207.

[0047] Specifically, because the silicon wafer 201 reaching the target thickness is too thin, a redistribution layer 206 as shown in Figure 7 may also be prepared on the surface of the silicon wafer 201 away from the upper carrier 203 before temporarily bonding with the lower carrier 204, so as to provide better support for the silicon wafer 201. As shown in Figure 7 , after the preparation of the redistribution layer 206 is completed, solder can be deposited on the surface of the redistribution layer 206 away from the silicon wafer 201 by electroplating, sputtering or jet printing technology, and the solder is heated above the melting point in an inert gas to melt into a ball to form micro-bumps 207 as shown in Figure 7 . Therefore, one side of the redistribution layer 206 is connected with the conductive metal in the through hole 202, and the other side of the redistribution layer 206 is connected with the micro-bumps 207.

[0048] In some embodiments, the redistribution layer 206 is formed on the surface of the silicon wafer 201 reaching the target thickness away from the upper carrier 203, comprising: depositing a first insulating medium layer 208 on the surface of the silicon wafer 201 reaching the target thickness away from the upper carrier 203; etching the first insulating medium layer 208 to form a circuit pattern, wherein the circuit pattern exposes the through hole 202; and metal filling in the circuit pattern to obtain the redistribution layer 206.

[0049] Specifically, as shown in Figure 7 , the first insulating medium layer 208 is deposited on the surface of the silicon wafer 201 reaching the target thickness away from the upper carrier 203, wherein the forming method of the first insulating medium layer 208 includes thermal oxidation, atomic layer deposition, plasma enhanced chemical vapor deposition, etc., the material of the first insulating medium layer 208 includes SiO2(silicon dioxide), etc., and the thickness of the first insulating medium layer 208 ranges from 10 nm to 10 μm. Then the first insulating medium layer 208 is etched to expose the through hole 202, so as to form a circuit image, and then the circuit pattern is filled with metal by electroplating to form the redistribution layer 206.

[0050] In some embodiments, a silicon wafer 201 is provided by: etching a patterned initial silicon wafer 209 to form a via 202; depositing a second insulating medium layer 211 on the surface of the initial silicon wafer 209 and inside the via 202; depositing a barrier layer 212 on the surface of the second insulating medium layer 211 away from the initial silicon wafer 209, the inner wall of the via 202 and the bottom of the via 202, and depositing a seed layer 213 on the surface of the barrier layer 212 away from the second insulating medium layer 211; filling a conductive metal on the surface of the seed layer 213 away from the barrier layer 212; and removing the barrier layer 212, the seed layer 213 and the conductive metal on the surface of the initial silicon wafer 209 to obtain the silicon wafer 201.

[0051] Specifically, the patterned initial silicon wafer 209 as shown in FIG. 1 is etched by an etching process to form a via 202 as shown in FIG. 2, wherein the patterned initial silicon wafer 209 is formed by photolithography of a spin-on photoresist 210 on the upper surface of the initial silicon wafer 209, and the thickness of the photoresist 210 is 10 nm-1 μm. Figure 8 Figure 9 Figure 10 Figure 11 Figure 11 Figure 2

[0052] ​​​​​​The technical solutions of the present application are further described in detail below in combination with specific embodiments.

[0053] As shown in Figure 12 , the preparation method of the through-silicon via interconnection structure comprises the following steps:

[0054] S301, etching the patterned initial silicon wafer 209 as shown in Figure 8 to form the through hole 202 as shown in Figure 9 .

[0055] S302, as shown in Figure 10 , depositing the second insulating medium layer 211, the barrier layer 212 and the seed layer 213 in the surface of the initial silicon wafer 209 and the through hole 202 in sequence.

[0056] S303, as shown in Figure 11 , filling the conductive metal in the through hole 202.

[0057] S304, removing the barrier layer 212, the seed layer 213 and the conductive metal on the surface of the initial silicon wafer 209 to obtain the silicon wafer 201 as shown in Figure 2 .

[0058] S305, as shown in Figure 3 , temporarily bonding the upper surface of the silicon wafer 201 and the upper carrier 203 by using an ultraviolet light source.

[0059] S306, as shown in Figure 4 , thinning the side of the silicon wafer 201 away from the upper carrier 203 by using a first thinning method to make the thinned silicon wafer 201 reach a preset thickness, and thinning the side of the silicon wafer 201 reaching the preset thickness away from the upper carrier 203 by using a second thinning method to make the thinned silicon wafer 201 reach a target thickness.

[0060] S307, as shown in Figure 7 , forming a redistribution layer 206 on the surface of the silicon wafer 201 reaching the target thickness away from the upper carrier 203, and depositing solder on the surface of the redistribution layer 206 away from the silicon wafer 201 to form a micro-bump 207.

[0061] S308, as shown in Figure 5 , temporarily bonding the surface of the silicon wafer 201 reaching the target thickness away from the upper carrier 203 to the lower carrier 204.

[0062] S309, debonding the thinned silicon wafer 201 and the upper carrier 203 to obtain the through-silicon via interconnection structure as shown in Figure 6 .

[0063] Based on the above embodiments, the application provides a specific embodiment one:

[0064] Step 1: etching the patterned initial silicon wafer 209 to form a through hole 202. A clean 4-inch initial silicon wafer 209 with a thickness of 500 μm is uniformly coated with a layer of photoresist 210 with a thickness of 500 nm, and the pattern on the mask is transferred to the photoresist 210 by exposure and development photolithography process. Then, deep silicon etching process is used to etch the patterned initial silicon wafer 209 to form a through hole 202 with a depth of 60 μm and a diameter of 10 μm. After etching, the photoresist 210 is removed using an organic solvent and the initial silicon wafer 209 is cleaned.

[0065] Step 2: depositing a second insulating medium layer 211. A layer of SiO2 insulating layer is grown on the initial silicon wafer 209 by wet oxygen oxidation process. The clean initial silicon wafer 209 is placed in an oxidation diffusion furnace for wet oxygen oxidation, the furnace temperature is raised to 1100℃, the reaction time is 3h, and the sample is taken out when the temperature drops below 80℃, obtaining a SiO2 insulating layer with a thickness of 1 μm.

[0066] Step 3: depositing a barrier layer 212. TiN barrier layer 212 is deposited on the SiO2 insulating layer formed in the second step by atomic layer deposition process. The clean sample is placed in the reaction cavity of the atomic layer deposition equipment for TiN deposition, using TiCl4 (titanium chloride) and NH3 (ammonia) as the reaction precursors, the deposition temperature is 350℃, the deposition time is 2.5h, and a TiN barrier layer 212 with a thickness of 15 nm is obtained.

[0067] Step 4: depositing a seed layer 213. Cu seed layer 213 is deposited on the barrier layer 212 obtained in the third step by atomic layer deposition process. The clean sample is placed in the reaction cavity of the atomic layer deposition equipment for Cu deposition, using Cu(hfac)TMVS and HCOOH (formic acid) as the precursors, the deposition temperature is 200℃, the deposition time is 3h, and a Cu seed layer 213 with a thickness of 30 nm is obtained, wherein hfac represents hexafluoroacetylacetone and TMVS represents trimethylsilyl ethylene.

[0068] Step 5: conductive metal filling. Cu is filled in the through hole 202 by electroplating process. The clean sample is placed on the clamp of the electroplating tank for electroplating, the reaction temperature is 25℃, the reaction time is 1.5h, and Cu filling in the through hole 202 is realized.

[0069] Step 6: Planarization treatment. The upper surface of the initial silicon wafer 209 is subjected to planarization treatment using a method such as chemical mechanical polishing, to remove the insulating layer, diffusion barrier layer 212, seed layer 213 and metal on the upper surface of the initial silicon wafer 209, to obtain a silicon wafer 201.

[0070] Step 7: Ultraviolet light curing temporary bonding. The planarized surface of the silicon wafer 201 is uniformly covered with acrylic bonding glue 205; the planarized surface of the silicon wafer 201 is attached to the surface of the upper carrier 203, with the bonding glue 205 between them; the two are tightly attached by applying pressure (pressure 100 g / cm 2 , pressure time 60 s) and vacuum removal of air bubbles in the bonding glue 205; a 365 nm wavelength ultraviolet light source is used for irradiation to complete the bonding of the bonding glue 205 through a photo-curing reaction; the thickness of the cured bonding glue 205 is 10 μm; thus a bonded wafer with good flatness and bonding stability is obtained.

[0071] Step 8: Ultra-thin thinning of the silicon wafer 201. The silicon wafer 201 is thinned using a first thinning method (speed 100 μm / min) to a thickness of 70 μm, and then thinned further using a second thinning method (speed 10 μm / min) to a thickness of 50 μm; the surface of the silicon wafer 201 is then subjected to planarization treatment using chemical mechanical polishing.

[0072] Step 9: Preparation of the redistribution layer 206 and micro-bumps 207. A first insulating medium layer 208 of SiO2 with a thickness of 100 nm is prepared on the thinned wafer surface using atomic layer deposition, and then etched to form a line pattern; the redistribution layer 206 is then formed by filling the line pattern with metal through electroplating; the micro-bumps 207 are then formed by depositing solder Cu through electroplating and heating to above the melting point of the solder in a N2 atmosphere to melt into balls.

[0073] Step 10: Temporary bonding of the download wafer 204 and debonding of the upper carrier 203. The side with the micro-bumps 207 is temporarily bonded to the silicon wafer 204 using ultraviolet light curing; the upper carrier 203 is debonded to obtain an ultra-thin through-silicon via interconnection structure.

[0074] Based on the above embodiment one, the application further provides a specific embodiment two. The difference between the embodiment two and the embodiment one is as follows:

[0075] Step 1: Etching of the patterned initial silicon wafer 209 using an etching process to form through-holes 202 with a depth of 40 μm and a diameter of 5 μm.

[0076] Step 2: A second insulating medium layer 211 of SiO2 is grown on the initial silicon wafer 209 by a plasma enhanced chemical vapor deposition process. The clean initial silicon wafer 209 is placed in the reaction chamber of the plasma enhanced chemical vapor deposition equipment for SiO2 deposition, using SiH4 (silane) and N2O (nitrous oxide) as the reaction gas, a deposition temperature of 250°C, and a deposition time of 20 min, to obtain a SiO2 insulating medium layer with a thickness of 0.5 μm.

[0077] Step 5: The metal Cu is filled in the via hole 202 by a chemical plating process. The clean sample is placed on the clamp of the chemical tank for chemical plating, with a reaction temperature of 50°C and a reaction time of 2 h, to achieve Cu filling in the via hole 202.

[0078] Step 7: Pressure (pressure 50 g / cm 2 , pressure time 30 s), the thickness of the bonding glue 205 after curing is 15 μm.

[0079] Step 8: The silicon wafer 201 is thinned by a first thinning method (speed 150 μm / min) using a bonder, to reduce the thickness of the silicon wafer 201 to 50 μm, and then thinned by a second thinning method (speed 2 μm / min) to reduce the thickness to 30 μm.

[0080] Step 10: Temporary bonding of the download piece 204 and debonding of the upload piece 203. The side with the micro-bumps 207 is temporarily thermally bonded to the glass of the download piece 204.

[0081] Based on the above embodiment one, the application further provides a specific embodiment three. The embodiment three is different from the embodiment one in the following steps:

[0082] Step 1: The patterned initial silicon wafer 209 is etched by an etching process to form a via hole 202 with a depth of 80 μm and a diameter of 10 μm.

[0083] Step 3: The Ti barrier layer 212 is deposited on the SiO2 insulating medium layer formed in the second step by a magnetron sputtering process. The clean sample is placed in the chamber of the magnetron sputtering equipment for Ti deposition, using a high-purity titanium target as the target material, a deposition temperature of 100°C, and a deposition time of 5 min, to obtain a Ti diffusion barrier layer 212 with a thickness of 30 nm.

[0084] Step 8: The silicon wafer 201 is thinned by a first thinning method (speed 200 μm / min) using a bonder, to reduce the thickness of the silicon wafer 201 to 90 μm, and then thinned by a second thinning method (speed 5 μm / min) to reduce the thickness to 70 μm.

[0085] Step 9: preparing the redistribution layer 206 and the micro-bump 207. A first insulating medium layer 208 of SiO2 with a thickness of 500 nm is prepared on the thinned wafer surface by thermal oxidation.

[0086] In summary, according to the preparation method of the through-silicon via interconnection structure provided by the embodiments of the present application, the silicon wafer has a through hole filled with a conductive metal; the upper surface of the silicon wafer is temporarily bonded to an upper carrier, and the side of the silicon wafer away from the upper carrier is thinned based on a first thinning method to make the thinned silicon wafer reach a preset thickness, and the side of the silicon wafer away from the upper carrier and reaching the preset thickness is thinned based on a second thinning method to make the thinned silicon wafer reach a target thickness, wherein the thinning speed of the first thinning method is greater than the thinning speed of the second thinning method, the surface of the silicon wafer away from the upper carrier and reaching the target thickness is temporarily bonded to a lower carrier, and the thinned silicon wafer and the upper carrier are unbonded to obtain the through-silicon via interconnection structure. Thus, the silicon wafer is thinned by using two thinning methods to obtain a thinner silicon wafer, thereby shortening the vertical heat dissipation path and reducing the risk of local hot spots.

[0087] In the description of the present application, the description of the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" means that the specific features, structures, materials or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present application. In the description of the present application, the illustrative description of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner.

[0088] In the description of the present application, it should be understood that the terms "center", "longitudinal", "transverse", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential" and the like indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the devices or elements referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the present application.

[0089] In addition, the terms "first", "second", and the like used in the embodiments of the present application are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance, or implicitly indicating the number of technical features indicated in the embodiments. Therefore, the features defined with the terms "first", "second", and the like in the embodiments of the present application can explicitly or implicitly indicate that at least one of the features is included in the embodiments. In the description of the present application, the meaning of the word "plurality" is at least two or two or more, such as two, three, four, etc., unless otherwise specified and limited in the embodiments.

[0090] In the present application, unless otherwise specified and limited in the embodiments, the terms "mounting", "connecting", "connecting" and "fixing" and the like appearing in the embodiments should be understood in a broad sense, for example, the connection can be a fixed connection, or a detachable connection, or integrated, which can be understood, or can be a mechanical connection, an electrical connection, etc. Of course, it can also be directly connected, or indirectly connected through an intermediate medium, or it can be the internal communication of two elements, or the interaction relationship between two elements. For those skilled in the art, the specific meaning of the above terms in the present application can be understood according to the specific implementation situation.

[0091] In the present application, unless otherwise specified and limited, the first feature is "on" or "under" the second feature can be that the first and second features are in direct contact, or the first and second features are indirectly in contact through an intermediate medium. Moreover, the first feature "above", "above" and "above" the second feature can be that the first feature is directly above or obliquely above the second feature, or only indicates that the horizontal height of the first feature is higher than that of the second feature. The first feature "below", "below" and "below" the second feature can be that the first feature is directly below or obliquely below the second feature, or only indicates that the horizontal height of the first feature is less than that of the second feature.

[0092] Although the embodiments of the present application have been shown and described above, it can be understood that the above embodiments are exemplary and cannot be understood as limiting the present application, and those skilled in the art can make changes, modifications, replacements and variations to the above embodiments within the scope of the present application.

Claims

1. A method for preparing a through silicon via interconnect structure, characterized in that: include: Providing a silicon wafer, wherein the silicon wafer has a through hole, and the through hole is filled with a conductive metal; Temporarily bonding the upper surface of the silicon wafer to an upper carrier wafer; Thinning the side of the silicon wafer away from the upper wafer based on a first thinning method, so that the thinned silicon wafer reaches a preset thickness; thinning the side of the silicon wafer that has reached the preset thickness away from the upper wafer based on a second thinning method, so that the thinned silicon wafer reaches a target thickness, wherein the thinning speed of the first thinning method is greater than the thinning speed of the second thinning method; The surface of the silicon wafer reaching the target thickness away from the upper carrier is temporarily bonded to the lower carrier, and the thinned silicon wafer is debonded from the upper carrier to obtain the through silicon via interconnection structure.

2. The method according to claim 1, characterized in that Temporarily bonding the upper surface of the silicon wafer to an upper carrier wafer, comprising: Coating bonding glue on the upper surface of the silicon wafer or the surface of the upper carrier; Laminating the upper surface of the silicon wafer to the surface of the upper carrier, and pressurizing the laminated silicon wafer and the upper carrier; An ultraviolet light source is used to irradiate the pressurized silicon wafer and the upper carrier to photo-cure the bonding adhesive.

3. The method according to claim 2, characterized in that The wavelength range of the ultraviolet light source is 300-400nm, and the intensity of the ultraviolet light source is 100-10000mW / cm 2 .

4. The method according to claim 2, characterized in that The thickness of the bonding adhesive after curing is 1-50 μm.

5. The method according to any one of claims 1 to 4, characterized in that The thinning speed of the first thinning method is 60-300 μm / min, and the thinning speed of the second thinning method is 1-60 μm / min.

6. The method according to any one of claims 1 to 4, characterized in that The target thickness is 5-100 μm.

7. The method according to any one of claims 1 to 4, characterized in that The thickness difference between the preset thickness and the target thickness is 10-30 μm.

8. The method according to any one of claims 1 to 4, characterized in that Before temporarily bonding the surface of the silicon wafer reaching the target thickness away from the upper carrier wafer to the lower carrier wafer, the method further comprises: forming a redistribution layer on a surface of the silicon wafer reaching the target thickness and away from the upper carrier, wherein the redistribution layer is connected to the through hole; Solder is deposited on the surface of the redistribution layer away from the silicon wafer to form micro bumps.

9. The method according to claim 8, characterized in that Forming a redistribution layer on a surface of the silicon wafer reaching the target thickness and away from the upper carrier, comprising: Depositing a first insulating dielectric layer on the surface of the silicon wafer that reaches the target thickness and is away from the upper carrier; etching the first insulating dielectric layer to form a circuit pattern, wherein the circuit pattern exposes the through hole; Metal filling is performed in the circuit pattern to obtain the redistribution layer.

10. The method according to claim 1, characterized in that Provide silicon wafers, including: Etching the patterned initial silicon wafer to form the through hole; depositing a second insulating dielectric layer on the surface of the initial silicon wafer and in the through hole; Depositing a barrier layer on a surface of the second insulating dielectric layer away from the initial silicon wafer, the inner wall of the through hole, and the bottom of the through hole, and depositing a seed layer on a surface of the barrier layer away from the second insulating dielectric layer; Filling a conductive metal on a surface of the seed layer away from the barrier layer; The barrier layer, the seed layer and the conductive metal on the surface of the initial silicon wafer are removed to obtain the silicon wafer.

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