A high-performance low-power radiation-hardened latch tolerant to three-node flipping

Abstract

The application relates to a high-performance low-power anti-radiation latch tolerating three-node upset, which retains the original high-performance low-power anti-radiation latch structure tolerating double-node upset and inherits the capability of tolerating single-node and double-node upset of the original circuit. Two additional redundant nodes are introduced, and interlocking monitoring networks are formed by three-input C cells and original nodes; in addition to the original DNU feedback loop, a TNU detection and recovery module formed by two three-input C cells is newly added, the module continuously monitors the state consistency of the key node group, when three or more node errors are detected, the redundant node is enabled to perform state reconstruction, and the correct value is output through a voting mechanism. The fault-tolerant capability of the latch is comprehensively improved from DNU to TNU with a small additional cost, while the excellent characteristics of low power consumption and high performance are maintained, so that the ultimate requirement of integrated circuit reliability in modern aerospace and other harsh radiation environments is met.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of integrated circuits, and relates to a high-performance low-power anti-radiation latch tolerating three-node flipping. BACKGROUND

[0002] With the continuous evolution of semiconductor manufacturing processes to deep submicron and nanometer scales, the feature size of integrated circuits is continuously reduced, the operating voltage is gradually reduced, and the node capacitance and critical charge are significantly reduced. This makes modern electronic systems, especially those used in harsh radiation environments such as aerospace, nuclear industry, and high-energy physics experiments, have unprecedentedly high standards for the anti-radiation ability of their internal storage units. High-energy particles (such as neutrons, protons, alpha particles, and heavy ions) hitting the sensitive regions of integrated circuits can generate a large number of electron-hole pairs, which in turn cause transient current pulses, leading to unintended changes in the logic state of the circuit nodes. This phenomenon is called soft error. Among them, the transient pulse is called single event transient (SET), and if the error data is captured by the storage unit, it is called single event upset (SEU).

[0003] To alleviate soft errors, the industry has proposed various technical routes. One is to use error correction coding (ECC) at the system level, but this method introduces unacceptable area, power, and delay overhead when used for widely distributed and large number of latches, and has low practicability. The second is to use process and layout hardening, but this method is severely bound to specific processes, lacks universality, and has high design cost. Currently, the mainstream solution is circuit-level hardening design (RHBD), which fundamentally immunizes or recovers soft errors by designing new circuit structures, providing the best balance between performance, power, area, and reliability. In circuit-level RHBD design, the latch, as the most basic storage unit in digital systems, has always been a hot research topic. According to its tolerance ability, the development of anti-radiation latches has gone through three stages: single-node upset (SNU) tolerant latch, double-node upset (DNU) tolerant latch, and double-node upset (DNU) elastic / self-recovery latch.

[0004] In recent years, the probability of three-node upset (TNU) has become non-negligible, becoming a challenge that must be faced by the next generation of anti-radiation circuit design. However, the existing mainstream latch designs all focus on solving the SNU and DNU problems, and lack effective solutions to TNU. A few attempts to solve TNU are usually based on triple modular redundancy (TMR), which has an area, power, and performance overhead of more than 200%, which is unacceptable.

[0005] Therefore, there is an urgent need in the field for a novel latch circuit design that can provide full self-recovery capabilities, including three-node switching, while maintaining low power consumption, high performance, and small area overhead, to meet the stringent reliability requirements of future aerospace, medical, and military electronic systems. This invention is proposed based on this need. Summary of the Invention

[0006] To address the problems existing in the above-mentioned traditional methods, this invention proposes a high-performance, low-power radiation-hardened latch that tolerates three-node flip-flops. It can provide full self-recovery capability, including three-node flip-flops, while maintaining low power consumption, high performance, and small area overhead, in order to meet the stringent high reliability requirements of future aerospace, medical, and military electronic systems.

[0007] To achieve the above objectives, embodiments of the present invention employ the following technical solution to provide a high-performance, low-power, radiation-resistant latch that tolerates three-node flipping, comprising:

[0008] The clock input terminal is used to receive the clock signal and transmit the clock signal to the enable terminal of the clock control transmission module and the clock gating C unit in the main interlock feedback loop.

[0009] The data input terminal is used to receive input signals and transmit them to the input terminal of the clock control transmission module.

[0010] The clock control transmission module is used to transmit the input signal to sensitive nodes N1, N3, and N5 through multiple transmission gates.

[0011] The main interlock feedback loop is a dual-node flip feedback loop consisting of three dual-input clock-gated C units CE2, CE4, and CE6 and three dual-input C units CE1, CE3, and CE5. The outputs of CE6, CE1, CE2, CE3, CE4, and CE5 are connected to sensitive nodes N1 to N5 and output node Q, respectively. The other input of each of the three C units is connected to control node A, and the other input of each of the three clock-gated C units is connected to control node B.

[0012] A redundant feedback loop is used to introduce two redundant nodes RN_C and RN_D, which together form an interlocked monitoring network with the two redundant nodes, five sensitive nodes N1 to N5, output node Q, and control nodes A and B through four C units.

[0013] In one embodiment, in the main interlocking feedback loop, one input terminal of CE1 and the output terminal of CE6 are connected with the sensitive node N1, the output terminal of CE1 and one input terminal of CE2 are connected with the sensitive node N2, the output terminal of CE2 and one input terminal of CE3 are connected with the sensitive node N3, the output terminal of CE3 and one input terminal of CE4 are connected with the sensitive node N4, the output terminal of CE4 and one input terminal of CE5 are connected with the sensitive node N5, and the output terminal of CE5 and one input terminal of CE6 are connected with the output node Q; the other input terminal of CE1, CE3 and CE5 are connected with the control node A, the other input terminal of CE2, CE4 and CE6 are connected with the control node B, and the enable terminals of CE2, CE4 and CE6 are connected with the clock input terminal.

[0014] In one embodiment, the redundant feedback loop comprises two three-input C cells CE9 and CE10, and two four-input C cells CE7 and CE8.

[0015] The control node A, the control node B and the output node Q are connected with the three input terminals of CE9 respectively, the output terminal of CE9 is connected with the first redundant node, the sensitive nodes N1, N3 and N5 are connected with the three input terminals of CE10 respectively, the output terminal of CE10 is connected with the second redundant node, the second redundant node RN_D, the sensitive nodes N1, N3 and N5 are connected with the four input terminals of CE7 respectively, the output terminal of CE7 is connected with the control node A, the sensitive nodes N2 and N4, the output node Q and the first redundant node RN_C are connected with the four input terminals of CE8 respectively, and the output terminal of CE8 is connected with the control node B.

[0016] In one embodiment, the clock control transmission module comprises three transmission gates TG1, TG2 and TG3; the transmission gate comprises one NMOS transistor and one PMOS transistor, the drain of the NMOS transistor and the source of the PMOS transistor are connected to serve as the input terminal of the transmission gate, and the drain of the NMOS transistor and the source of the PMOS transistor are connected to serve as the output terminal of the transmission gate.

[0017] The clock input terminal is connected with the gate of the NMOS transistor of TG1, TG2 and TG3, and the clock input terminal is connected with the gate of the PMOS transistor of TG1, TG2 and TG3 through an inverter; the input terminal of TG1, TG2 and TG3 is connected with the data input terminal, and the output terminal of TG1, TG2 and TG3 is connected with the sensitive nodes N1, N3 and N5 respectively.

[0018] In one embodiment, when the clock signal CLK = 1, the latch is in transparent mode. The transmission gates TG1, TG2, TG3 are turned on, the input data D is directly transmitted to the sensitive nodes N1, N3, N5, the clock gating C units CE2, CE4, CE6 are disabled, the sensitive nodes N1, N3, N5 are precharged according to the input data, and other nodes remain unchanged.

[0019] In one embodiment, when CLK = 0, the latch is in hold mode, the transmission gates TG1, TG2, TG3 are turned off, the direct current path is cut off, the clock gating C units CE2, CE4, CE6 are enabled, the interlocking feedback network composed of the main interlocking feedback loop, the redundant feedback loop and the redundant nodes is activated, and the data state is maintained together, and the error detection and recovery function is performed.

[0020] One of the above technical solutions has the following advantages and beneficial effects:

[0021] The above-mentioned high-performance low-power anti-radiation latch tolerant to three-node upset retains the original high-performance low-power anti-radiation latch structure tolerant to double-node upset, and inherits the ability of the original circuit to tolerate single-node and double-node upset. Meanwhile, two additional redundant nodes are introduced, and an interlocking monitoring network is formed with the original nodes through three-input C units. In addition to the original DNU feedback loop, a TNU detection and recovery module composed of two three-input C units is added, which continuously monitors the state consistency of the key node group. When three or more node errors are detected, the redundant nodes are enabled for state reconstruction, and the correct value is output through the voting mechanism. The fault tolerance of the latch is comprehensively improved from DNU to TNU with minimal additional cost, while maintaining its excellent characteristics of low power consumption and high performance, to meet the ultimate requirements of integrated circuit reliability in modern aerospace and other harsh radiation environments. BRIEF DESCRIPTION OF DRAWINGS

[0022] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the drawings needed in the embodiment or the prior art description will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.

[0023] Figure 1 A schematic diagram of a high-performance low-power anti-radiation latch tolerant to three-node upset in one embodiment;

[0024] Figure 2 A schematic diagram of the internal connection circuit of the transmission gate in one embodiment;

[0025] Figure 3A schematic diagram of a high performance low power radiation hardened latch (HLDRL) circuit tolerating double-node upset in the prior art;

[0026] Figure 4 A timing waveform diagram of a high performance low power radiation hardened latch circuit tolerating triple-node upset in one embodiment;

[0027] Figure 5 A transient recovery waveform simulation diagram of a high performance low power radiation hardened latch circuit tolerating triple-node upset in one embodiment under triple-node upset (TNU) injection at N1, N2, N3;

[0028] Figure 6 A transient recovery waveform simulation diagram of a high performance low power radiation hardened latch circuit tolerating triple-node upset in one embodiment under triple-node upset (TNU) injection at A, B, Q. DETAILED DESCRIPTION

[0029] In order to make the objects, technical solutions and advantages of the present application clearer, the present application will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and not intended to limit the present application.

[0030] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in the description of the application herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0031] It should be noted that a reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the application. The appearances of the phrase in various places in the specification are not necessarily all referring to the same embodiment, nor are they necessarily mutually exclusive of one another. One skilled in the art can understand that the embodiments described herein can be combined with other embodiments. The term "and / or" as used herein refers to any combination of associated terms, including all possible combinations, and includes terms that are conjunctively or disjunctively associated with one another.

[0032] The embodiments of the present application will be described in detail below with reference to the accompanying drawings.

[0033] In one embodiment, as shown in Figure 1 a high performance low power radiation hardened latch tolerating triple-node upset is provided, comprising:

[0034] A clock input terminal CLK is configured to receive a clock signal CLK and transmit the clock signal CLK to an enable terminal of a clock gate C unit in the clock-controlled transmission module and the main interlocking feedback loop.

[0035] Specifically, the clock input terminal CLK is connected to the enable terminals of the transmission gates TG1, TG2, TG3 and the clock gate C units CE2, CE4 and CE6.

[0036] A data input terminal D is configured to receive an input signal and transmit the input signal to the input terminals of the clock-controlled transmission module TG1, TG2 and TG3.

[0037] The clock-controlled transmission module is configured to transmit the input signal to the sensitive nodes N1, N3 and N5 through the transmission gates.

[0038] Specifically, the clock-controlled transmission module includes the transmission gates TG1, TG2 and TG3, and the data input terminal D is connected to the input terminals of the transmission gates TG1, TG2 and TG3. The output terminal of TG1 drives the node N1, the output terminal of TG2 drives the node N3, and the output terminal of TG3 drives the data output terminal N5.

[0039] The main interlocking feedback loop is a double-node flip-flop feedback loop composed of three double-input clock gate C units CE2, CE4 and CE6 and three double-input C units CE1, CE3 and CE5. The output terminals of the C units CE6, CE1, CE2, CE3, CE4 and CE5 are connected to the sensitive nodes N1 to N5 and the output node Q, respectively. The other input terminals of the three C units are connected to the control node A, and the other input terminals of the three clock gate C units are connected to the control node B.

[0040] Specifically, CE1 is a double-input C unit, the input terminals of which are connected to the control node A and the sensitive node N1, and the output terminal of which drives the sensitive node N2. CE2 is a clock gate type double-input C unit, the input terminals of which are connected to the node B and N2, and the output terminal of which drives the sensitive node N3. CE3 is a double-input C unit, the input terminals of which are connected to the control node A and the sensitive node N3, and the output terminal of which drives the node N4. CE4 is a clock gate type double-input C unit, the input terminals of which are connected to the control node B and the sensitive node N4, and the output terminal of which drives the sensitive node N5. CE5 is a double-input C unit, the input terminals of which are connected to the control node A and the sensitive node N5, and the output terminal of which drives the output node Q. CE6 is a clock gate type double-input C unit, the input terminals of which are connected to the control node B and Q, and the output terminal of which drives the sensitive node N1.

[0041] The redundant feedback loop is configured to introduce two redundant nodes RN_C and RN_D, and to form an interlocking monitoring network through four C units by connecting the two redundant nodes, the five sensitive nodes N1 to N5, the output node Q, the control nodes A and B.

[0042] Specifically, the redundant feedback loop includes two four-input C cells and two three-input C cells.

[0043] CE7 is a four-input C cell, whose four inputs are connected to sensitive nodes N1, N3, N5 and the second redundant node RN_D respectively. Its output drives the control node A. CE8 is a four-input C cell, whose four inputs are connected to sensitive nodes N2 and N4, the output node Q and the first redundant node RN_C respectively. Its output drives the control node B. CE9 is a three-input C cell, whose three inputs are connected to control nodes A and B, the output node Q respectively. Its output drives the first redundant node RN_C. CE10 is a three-input C cell, whose three inputs are connected to sensitive nodes N1, N3, N5 respectively. Its output drives the second redundant node RN_D.

[0044] The high-performance low-power anti-radiation latch tolerant to triple-node flipping proposed in the application can provide complete self-recovery capability including triple-node flipping while maintaining low power consumption, high performance and small area overhead, to meet the stringent requirements of future aerospace and medical electronic systems for high reliability.

[0045] The high-performance low-power anti-radiation latch tolerant to triple-node flipping described above retains the original structure of the high-performance low-power anti-radiation latch tolerant to double-node flipping, inheriting the ability of the original circuit to tolerate single-node and double-node flipping. Two additional redundant nodes are introduced, which form an interlocking monitoring network with the original nodes through three-input C cells. In addition to the original DNU feedback loop, a TNU detection and recovery module composed of two three-input C cells is added, which continuously monitors the state consistency of the key node group. When three or more node errors are detected, the redundant nodes are enabled for state reconstruction, and the correct value is output through a voting mechanism. This realizes the comprehensive improvement of the fault-tolerant capability of the latch from DNU to TNU with minimal additional overhead, while maintaining its excellent characteristics of low power consumption and high performance, to meet the ultimate requirements of modern aerospace and other harsh radiation environments for integrated circuit reliability.

[0046] In one embodiment, in the main interlocking feedback loop, one input terminal of CE1 and the output terminal of CE6 are connected with the sensitive node N1, the output terminal of CE1 and one input terminal of CE2 are connected with the sensitive node N2, the output terminal of CE2 and one input terminal of CE3 are connected with the sensitive node N3, the output terminal of CE3 and one input terminal of CE4 are connected with the sensitive node N4, the output terminal of CE4 and one input terminal of CE5 are connected with the sensitive node N5, and the output terminal of CE5 and one input terminal of CE6 are connected with the output node Q; the other input terminal of CE1, CE3 and CE5 are connected with the control node A, the other input terminal of CE2, CE4 and CE6 are connected with the control node B, and the enable terminal of CE2, CE4 and CE6 are connected with the clock input terminal CLK.

[0047] In one embodiment, the redundant feedback loop comprises two three-input C cells CE9 and CE10 and two four-input C cells CE7 and CE8.

[0048] The control node A, the control node B and the output node Q are connected with the three input terminals of CE9 respectively, the output terminal of CE9 is connected with the first redundant node RN_C, the sensitive nodes N1, N3 and N5 are connected with the three input terminals of CE10 respectively, the output terminal of CE10 is connected with the second redundant node RN_D, the second redundant node RN_D, the sensitive nodes N1, N3 and N5 are connected with the four input terminals of CE7 respectively, the output terminal of CE7 is connected with the control node A, the sensitive nodes N1 and N4, the output node Q and the second redundant node RN_D are connected with the four input terminals of CE8 respectively, and the output terminal of CE8 is connected with the control node B.

[0049] In one embodiment, the clock control transmission module comprises three transmission gates TG1, TG2 and TG3, and each transmission gate comprises one NMOS transistor and one PMOS transistor, the drain of the NMOS transistor and the source of the PMOS transistor are connected to serve as the input terminal of the transmission gate, and the drain of the NMOS transistor and the source of the PMOS transistor are connected to serve as the output terminal of the transmission gate.

[0050] The clock input terminal is connected with the gate of the NMOS transistor of TG1, TG2 and TG3, and the clock input terminal 10 is connected with the gate of the PMOS transistor of TG1, TG2 and TG3 through an inverter; the input terminal of TG1, TG2 and TG3 is connected with the data input terminal D, and the output terminal of TG1, TG2 and TG3 is connected with the sensitive nodes N1, N3 and N5 respectively.

[0051] The internal connection circuit diagram of the transmission gate is shown in Figure 2 .

[0052] In one embodiment, when the clock signal CLK=1, the latch is in transparent operating mode; transmission gates TG1, TG2, and TG3 are turned on, and the input data D is directly transmitted to sensitive nodes N1, N3, and N5; clock gate C units CE1, CE3, and CE5 are disabled, and the internal nodes of the circuit are pre-charged and stabilized according to the input data.

[0053] In one embodiment, when CLK=0, the latch maintains its operating mode, the transmission gates TG1, TG2, and TG3 are turned off, the DC path is cut off, the clock gate C units CE1, CE3, and CE5 are enabled, and the interlock feedback network consisting of the main interlock feedback loop, the redundant feedback loop, and the redundant nodes is activated to jointly maintain the data state and perform error detection and recovery functions.

[0054] Analysis of the working process and working principle of the high-performance, low-power radiation-resistant latch that tolerates three-node switching proposed in this application:

[0055] Because this latch circuit is in Figure 3 This circuit is an improvement upon the high-performance, low-power radiation-hardened latch (HLDRL latch) circuit shown, which tolerates two-node switching. To further improve its performance in tolerating three-node switching, the circuit is modified as follows: Figure 1 As shown, a redundancy recovery module is added, which includes two three-input C units (CE9, CE10), a first redundant storage node RN_C, and a second redundant storage node RN_D. At the same time, the two three-input C units CE7 and CE8 are upgraded to four-input C units to access the feedback signals of the redundant nodes.

[0056] Figure 3The high-performance low-power radiation-hardened latch shown has good ability to tolerate single-node upset and double-node upset by itself. For example, when a single-node upset occurs in node N1, CE1 detects that its inputs A, N1 are inconsistent, enters the hold state, and prevents the error from propagating to N2, while the input B, Q of CE6 is not affected, and it continues to work normally, with its output driving the sensitive node N1. At the same time, nodes B and Q are kept stable through units such as CE7 and CE8. Finally, the output of CE6 forces the erroneous node N1 to return to the correct value. When a double-node upset occurs in control nodes A and B, the inputs of CEs 1, 2, 6, and 8 are inconsistent, and the outputs remain unchanged, so although A and B are both wrong, the internal nodes N1, N2, N3, N4, N5, and Q are not immediately affected because the C units they drive enter the hold state. The values of nodes N1, N3, and N5 are maintained through feedback and input to CE7. CE7 calculates based on the three stable and correct inputs N1, N3, and N5, and drives node A to return to the correct value. When A returns, CEs 1, 3, and 5 exit the hold state in turn. Subsequently, the system cooperates through the loop to gradually restore node B to the correct value.

[0057] The timing waveform diagram of the high-performance low-power radiation-hardened latch circuit that tolerates triple-node upset is shown in Figure 4

[0058] ​When the latch is in the hold mode (CLK=0), if a particle strike causes the logic state of nodes N1, N2, N3 to flip simultaneously, the circuit will implement self-recovery as follows: The application assumes that all the nodes store data 0 in the initial state. Therefore, when an error occurs, the faulty nodes N1, N2, N3 all become 1, and the other nodes remain correct, i.e., N4=0, N5=0, A=1, B=1, Q=0, RN_C=1, RN_D=1. At this time, the two inputs of CE2 are B=1, N2=1, and the inputs are the same, so the output of the function is 0, i.e., trying to pull N3 from the error value 1 back to 0 for correction. For the two inputs of CE1, A=1, N1=1, the inputs are the same, so the output of the function is 0, i.e., trying to pull N2 from the error value 1 back to 0 for correction. For the two inputs of CE3, A=1, N3=1, the inputs are the same, so the output of the function is 0, i.e., trying to pull N4 from the correct value 0 back to 0 to maintain correctness. CE10 is a three-input C element, and the three inputs are N1=1, N3=1, N5=0. Since the inputs are inconsistent, it enters a high-impedance hold state, so that the second redundant node RN_D output successfully maintains the correct value 1. At the same time, for the three-input C element CE9, the three inputs are A=1, B=1, Q=0. Since the inputs are inconsistent, it enters a high-impedance hold state, so that the first redundant node RN_C output successfully maintains the correct value 1. Since CE7 and CE8 are four-input C elements, the four-input ports of the two are N1=1, N3=1, N5=0, RN_D=1 and N2=1, N4=0, Q=0, RN_C=1, respectively, and the inputs are inconsistent, both enter the hold state, and maintain the outputs A and B at the correct value 1. At this time, the error is successfully limited in <N1, N2, N3>. N4, N5, A, B, Q, RN_C, RN_D all remain correct, and CE1 and CE2 have already begun to output correction signals. Finally, step-by-step correction is performed, CE1 continuously outputs 0, forcibly driving node N2, CE2 continuously outputs 0, forcibly driving node N3, and since the error sources of N2 and N3 are transient pulses, their ability to maintain error state is weak. Under the strong driving of CE1 and CE2, nodes N2 and N3 are quickly corrected from the error value 1 to the correct value 0. At this time, N2 and N3 have been corrected, and then N1 needs to be corrected. When N3=0 is corrected, the input of CE10 becomes N1=1, N3=0, N5=0, and the input is still inconsistent, so RN_D continues to remain 1, so the anchor point RN_D=1 continues to provide correct input for CE7. The input of CE7 is N1=1, N3=0, N5=0, RN_D=1, and the signal RN_D=1 will force the output of CE7 to tend to the inverse code of 0, i.e., 1. Since the error state of N1 is isolated, and its driving source CE6 is in the hold state (high-impedance state), the parasitic capacitance on the N1 node will gradually drift through leakage current and other ways.Once N1 deviates from the correct value 1, the "voting" mechanism of CE7 will capture this change, rapidly pulling N1 back to the correct value 0 through positive feedback, and eventually the node N1 is corrected. When all the faulty nodes are recovered, the whole circuit goes through a short stabilization and returns to the correct state before the TNU occurs. The transient recovery waveform simulation diagram of the high-performance low-power anti-radiation latch circuit tolerating three-node upset under the three-particle upset (TNU) injection of N1, N2, and N3 three nodes is as shown in the following figure. Figure 5 As shown in the figure.

[0059] The nodes A, B, Q are the most core control nodes and output nodes of the latch, and can be restored after the occurrence of TNU, so as to embody the superiority of the circuit, and the restoration process perfectly shows the core value of the redundancy restoration module. The application assumes that the initial state is that all nodes store data 0. Therefore, in the stable state, A = 1, B = 1, Q = 0. Once TNU, the nodes A, B, Q are flipped to 0, 0, 1 at the same time. When a fault occurs, the error nodes are A = 0, B = 0, Q = 1, and other nodes: N1 = 0, N2 = 0, N3 = 0, N4 = 0, N5 = 0, N6 = 0, RN_C = 1, RN_D = 1 all remain correct. CE9 monitors A, B, Q, and because the inputs of the three nodes are inconsistent, CE9 immediately enters the high resistance state, so that its output is isolated from the internal nodes. The first redundant node RN_C thus maintains its original, unaffected correct value 1. This is the first and most important turning point in the entire restoration process. RN_C becomes the 'trust anchor' of the system. CE8 enters the holding state because the inputs N2 = 0, N4 = 0, Q = 1, RN_C = 1 are inconsistent, and its output B maintains the error value 0. The input B = 0, Q = 1 of CE6 is different, enters the holding state, and its output N1 maintains the correct value 0. CE10 and CE9 have the same function, monitor N1 = 0, N3 = 0, N5 = 0, the inputs are the same, and the output is 1, that is, the second redundant node RN_D also maintains the correct value 1. The four inputs of the last four-input C unit CE7 are N1 = 0, N3 = 0, N5 = 0, RN_D = 1, the inputs are inconsistent, and it enters the holding state, and its output A maintains the error value 0. At this time, the error is successfully isolated. All internal nodes (N1-N5) are not directly affected and remain correct. Most importantly, the two redundant nodes RN_C and RN_D both hold the correct value 1. At this time, the correct value RN_C = 1 as an anchor point exerts force, continuously inputting into CE8. Next, step-by-step error correction is performed, among the four inputs of CE8, N2 = 0, N4 = 0, RN_C = 1 are stable and correct signals. Q = 1 is incorrect. The strong correct signal RN_C = 1 will force the 'voting' mechanism of CE8 to tend to output the inverse of 1, that is, 0 (because the C unit output is the opposite of the input). CE8 drives its output to pull node B from the error value 0 back to the correct value 1. Node B is corrected. When B is corrected, it is connected to CE4, CE6, CE8, and the outputs of the C units are not changed. CE9 A = 0, B = 1, Q = 1, the inputs are still inconsistent, and continues to maintain state, RN_C still stabilizes at 1. At this time, the input of CE5 is A = 0, N5 = 0, the inputs are the same, and the output is 1, trying to maintain Q = 1. However, CE8 is also continuously working, and one of its inputs Q = 1 is incorrect. Now the inputs of CE8 are N2 = 0, N4 = 0, Q = 1, RN_C = 1.RN_C=1 as the correct signal will continue to try to pull the output B to 1, and indirectly affect the entire loop. Eventually, through the interaction of units such as CE5 and CE6, and the correct driving force that B has recovered, node Q will be forced to be pulled back from the wrong value 1 to the correct value 0, and node Q is corrected. When Q=0 is corrected, the input of CE9 becomes A=0, B=1, Q=0, the input is still inconsistent, and continues to remain. At this time, the second "anchor point" RN_D=1 begins to play a major role. It continues to provide a correct signal as the input of CE7. The input of CE7 is N1=0, N3=0, N5=0, RN_D=1. This signal RN_D=1 will force the output of CE7 to be 1. CE7 drives its output to pull node A from the wrong value 0 back to the correct value 1. Node A is corrected. After A=1 is corrected, it is connected to CE1, CE3, CE5, CE7, CE9. The input of CE9 is A=1, B=1, Q=0, which is still inconsistent, and it will continue to remain until all nodes are stable. The recovered A and B will work together through the main feedback loop to ensure that all intermediate nodes are also completely stable in the correct state. Eventually, all nodes are pulled back to the correct logic state, and the system completes recovery. The transient recovery waveform simulation diagram of the high-performance low-power anti-radiation latch circuit tolerant to three-node flipping under the three-particle flipping (TNU) injection of the A, B, and Q three nodes is shown. Figure 6 as shown.

[0060] Compared with the traditional TMR scheme with an area and power consumption overhead of more than 200%, the present application only increases two three-input C cells and two redundant nodes through ingenious circuit structure innovation, that is, a qualitative leap in fault tolerance ability is achieved at a very small additional cost. Due to the adoption of a distributed redundancy and cross interlocking recovery strategy, the present application exhibits strong robustness to process, voltage, and temperature changes, ensuring its reliability under various working conditions.

[0061] The technical features of the above embodiments can be combined in any manner. To make the description concise, not all possible combinations of the technical features in the above embodiments are described, but as long as the combinations of the technical features do not contradict, they should be considered within the scope of the present application.

[0062] The above embodiments only express several implementation manners of the present application, and the description is relatively specific and detailed, but it should not be understood as a limitation on the protection scope of the present application. It should be noted that for ordinary skilled persons in the art, some modifications and improvements can be made without departing from the concept of the present application, and all belong to the protection scope of the present application.

Claims

1. A high performance low power radiation-hardened latch tolerant to three-node flipping, comprising: The clock input end is used for receiving a clock signal and transmitting the clock signal to an enable end of a clock gate C unit in a main interlocking feedback loop and a clock control transmission module. The data input end is used for receiving an input signal and transmitting the input signal to an input end of the clock control transmission module. The clock control transmission module is used for transmitting the input signal to sensitive nodes N1, N3 and N5 through a plurality of transmission gates. The main interlocking feedback loop is a double-node flip feedback loop composed of three double-input clock gate C units CE2, CE4 and CE6 and three double-input C units CE1, CE3 and CE5, the output ends of the C units CE6, CE1, CE2, CE3, CE4 and CE5 are connected with the sensitive nodes N1 to N5 and an output node Q, the other input ends of the three C units are connected with a control node A, the other input ends of the three clock gate C units are connected with a control node B. The redundant feedback loop is used for introducing two redundant nodes, and the two redundant nodes, the five sensitive nodes N1 to N5, the output node Q, the control nodes A and B form an interlocking monitoring network through the four C units. In the main interlocking feedback loop, one input end of the C unit CE1 and the output end of the C unit CE6 are connected with the sensitive node N1, the output end of the C unit CE1 and one input end of the C unit CE2 are connected with the sensitive node N2, the output end of the C unit CE2 and one input end of the C unit CE3 are connected with the sensitive node N3, the output end of the C unit CE3 and one input end of the C unit CE4 are connected with the sensitive node N4, the output end of the C unit CE4 and one input end of the C unit CE5 are connected with the sensitive node N5, the output end of the C unit CE5 and one input end of the C unit CE6 are connected with the output node Q, the other input ends of the C units CE1, CE3 and CE5 are connected with the control node A, the other input ends of the C units CE2, CE4 and CE6 are connected with the control node B, and the enable ends of the C units CE2, CE4 and CE6 are connected with the clock input end.

2. The high-performance low-power radiation-hardened latch tolerant to three-node flipping of claim 1, wherein, The redundant feedback loop includes two three-input C units CE9 and CE10 and two four-input C units CE7 and CE8.

3. The high-performance low-power radiation-hardened latch tolerant to three-node flipping of claim 1, wherein, The control node A, the control node B and the output node Q are connected with the three input ends of the C unit CE9, the output end of the C unit CE9 is connected with a first redundant node, the sensitive nodes N1, N3 and N5 are connected with the three input ends of the C unit CE10, the output end of the C unit CE10 is connected with a second redundant node, the second redundant node, the sensitive nodes N1, N3 and N5 are connected with the four input ends of the C unit CE7, the output end of the C unit CE7 is connected with the control node A, the sensitive nodes N2 and N4, the output node Q and the first redundant node are connected with the four input ends of the C unit CE8, and the output end of the C unit CE8 is connected with the control node B. The clock control transmission module includes three transmission gates TG1 to TG3, and each transmission gate includes an NMOS tube and a PMOS tube, the drain of the NMOS tube and the source of the PMOS tube are connected to serve as an input end of the transmission gate, and the drain of the NMOS tube and the source of the PMOS tube are connected to serve as an output end of the transmission gate.

4. The high-performance low-power radiation-hardened latch tolerant to three-node flipping of claim 1, wherein, ​ The clock input end is connected with the gate of the NMOS transistor of TG1-TG3, and is connected with the gate of the PMOS transistor of TG1-TG3 through an inverter; the input ends of TG1, TG2 and TG3 are connected with the data input end, and the output ends of TG1, TG2 and TG3 are connected with the sensitive nodes N1, N3 and N5 respectively.

5. The high-performance low-power radiation-hardened latch tolerant to three-node flipping of claim 4, wherein, When the clock signal CLK=1, the latch is in transparent operation mode; the transmission gates TG1, TG2 and TG3 are turned on, the input data D is directly transmitted to the sensitive nodes N1, N3 and N5; the clock gating C units CE2, CE4 and CE6 are disabled, the sensitive nodes N1, N3 and N5 are pre-charged according to the input data, and other nodes remain unchanged.

6. The high-performance low-power radiation-hardened latch tolerant to three-node flipping of claim 4, wherein, When CLK=0, the latch is in transparent operation mode, the transmission gates TG1, TG2 and TG3 are turned off, the direct current path is cut off, the clock gating C units CE2, CE4 and CE6 are enabled, the interlocking feedback network composed of the main interlocking feedback loop, the redundant feedback loop and the redundant nodes is activated, the data state is maintained together, and the error detection and recovery function is executed.

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