Switching device admittance value online modification method in real-time simulation modeling

Abstract

The invention is suitable for the technical field of power electronic simulation, and provides a switching device admittance value online modification method in real-time simulation modeling. The method comprises the following steps: loading a circuit topology through an upper computer, and selecting a switching device of which the admittance value needs to be dynamically switched in a circuit model to be simulated; presetting an admittance parameter list in an upper computer interface, and calculating and generating a circuit admittance matrix corresponding to a plurality of to-be-tested working conditions; the circuit admittance matrixes are sent to a real-time simulator FPGA to serve as simulation data, corresponding switching is conducted in real-time simulation operation, and circuit solving is executed. When different to-be-tested working conditions are simulated, the switch admittance value can be modified on line, simulation errors introduced by switch equivalent parasitic parameters are reduced, and therefore switch admittance parameter setting optimization under different test working conditions is achieved.

Description

Technical Field

[0001] This invention belongs to the field of power electronics simulation technology, and in particular relates to a method for online modification of the admittance value of switching devices in real-time simulation modeling. Background Technology

[0002] In existing real-time electromagnetic transient simulation methods with small step sizes (1 microsecond level), constant admittance models are typically used to model switches in order to complete model calculations within the simulation step size. The switch is treated as an inductor when on and a capacitor when off, and the admittance values ​​are made equal when the switch is on and off. This ensures that the admittance values ​​remain equal when the switch switches between on and off states, eliminating the need for dynamic calculation of the circuit admittance matrix.

[0003] Existing technologies have certain limitations when simulation models operate under different conditions. For example, to enhance the switching blocking effect, the circuit breaker's Gs (a parameter characterizing the admittance value, which can be solved by the simulation step size and Gs) needs to be set to a small value. However, when the switch changes from open to closed, the equivalent inductance increases as Gs decreases, introducing a larger inductance that affects the accuracy of the circuit simulation. Using a constant switch admittance value is insufficient to handle the different operating conditions of different simulation models. Summary of the Invention

[0004] The purpose of this invention is to provide a method for online modification of the admittance value of switching devices in real-time simulation modeling, aiming to solve the technical problems existing in the prior art mentioned in the background.

[0005] The embodiments of the present invention are implemented as follows: A method for online modification of the admittance value of switching devices in real-time simulation modeling, the method specifically includes the following steps: The host computer loads the circuit topology and selects the switching devices that need to dynamically switch the admittance value in the circuit model to be simulated. In the host computer interface, a list of admittance parameters is preset, and the circuit admittance matrices corresponding to multiple test conditions are calculated and generated. Multiple circuit admittance matrices are sent to the real-time simulator FPGA as simulation data, and corresponding switching is performed during real-time simulation to solve the circuit.

[0006] As a further limitation of the technical solution of the present invention, the host computer loads the circuit topology and selects the switching devices that need to dynamically switch the admittance value in the circuit model to be simulated. The switching devices include fully controlled devices, semi-controlled devices and uncontrolled devices. The fully controlled devices are IGBTs, IGBTs with anti-parallel diodes, MOSFETs, circuit breakers or ideal switches; the semi-controlled devices are thyristors; and the uncontrolled devices are diodes.

[0007] As a further limitation of the technical solution of this embodiment of the invention, the step of presetting the admittance parameter list in the host computer interface and calculating and generating circuit admittance matrices corresponding to multiple test conditions specifically includes the following steps: A list of admittance parameters is preset in the host computer interface, and the admittance values ​​of multiple switching devices under multiple test conditions are configured in the admittance parameter list. Based on the multiple admittance values ​​in the admittance parameter list, calculate and generate multiple circuit admittance matrices corresponding to the test conditions.

[0008] As a further limitation of the technical solution of this embodiment of the invention, the step of presetting an admittance parameter list in the host computer interface, wherein the admittance parameter list is configured with admittance values ​​of multiple switching devices under multiple test conditions, specifically includes the following steps: Multiple switching devices in the circuit are modeled using LC equivalents. When the switching device is on, it is equivalent to an inductor; when the switching device is off, it is equivalent to a capacitor. The switching device is discretized using the backward Euler method and is equivalent to a current source injected in parallel with conductance. Construct multiple admittance parameter tables containing default operating conditions, and configure the admittance values ​​of multiple switching devices under multiple operating conditions to be tested; when the switch admittance is not specified in the operating condition to be tested, the default admittance value is used.

[0009] As a further limitation of the technical solution of the present invention, in the step of calculating and generating multiple circuit admittance matrices corresponding to the test conditions based on multiple admittance values ​​in the admittance parameter list, each test condition corresponds to a set of coefficient equations.

[0010] As a further limitation of the technical solution of this embodiment of the invention, the step of sending multiple circuit admittance matrices to the real-time simulator FPGA as simulation data, and switching them accordingly during real-time simulation to perform circuit solving specifically includes the following steps: Multiple circuit admittance matrices are sent to the real-time simulator FPGA as simulation data. During real-time simulation, the corresponding circuit admittance matrix is ​​switched in real time according to different operating conditions under test. The FPGA simulator performs circuit solving based on the circuit admittance matrix.

[0011] As a further limitation of the technical solution of the present invention, in the real-time simulation operation, the simulation program can be manually switched to execute the current test condition through the host computer control, or the current test condition can be automatically selected and switched through the conditions calculated and output by the software program.

[0012] Compared with the prior art, the beneficial effects of the present invention are: (1) The present invention can modify the switch admittance value online when simulating different test conditions, reduce the simulation error introduced by the equivalent parasitic parameters of the switch, and thus achieve the optimal setting of switch admittance parameters for different test conditions; (2) The present invention can select different switch Gs values ​​according to different working states of the circuit, thereby adjusting the inductor and capacitor parameters introduced by the simulation modeling method, reducing the non-real switching loss and equivalent parameters caused by this, and improving the accuracy of circuit simulation. Attached Figure Description

[0013] Figure 1 The flowchart illustrates a method for online modification of the admittance value of switching devices in real-time simulation modeling provided by an embodiment of the present invention. Figure 2 A circuit diagram of the circuit model to be simulated provided in an embodiment of the present invention is shown; Figure 3 A schematic diagram of the actual settings Gs provided in an embodiment of the present invention is shown; Figure 4 A schematic diagram of the computational simulation efficiency method provided in an embodiment of the present invention is shown; Figure 5 The simulation efficiency graphs for different admittance parameters provided in the embodiments of the present invention are shown. Figure 6 Simulation waveforms of different admittance parameters provided in embodiments of the present invention are shown. Detailed Implementation

[0014] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

[0015] Understandably, existing technologies have certain limitations when simulation models operate under different conditions. For example, to enhance the switching blocking effect, the circuit breaker's Gs (a parameter characterizing the admittance value, which can be solved by the simulation step size and Gs) needs to be set to a small value. However, when the switch changes from open to closed, the equivalent inductance increases as Gs decreases, introducing a larger inductance that affects the accuracy of the circuit simulation. Using a constant switch admittance value is insufficient to handle the different operating conditions of different simulation models.

[0016] To address the aforementioned issues, this invention discloses a method for online modification of the admittance values ​​of switching devices in real-time simulation modeling. This method loads the circuit topology into a host computer, selects the switching devices whose admittance values ​​need dynamic switching in the circuit model to be simulated, presets an admittance parameter list in the host computer interface, calculates and generates multiple circuit admittance matrices corresponding to the test conditions, and sends these multiple circuit admittance matrices to the real-time simulator FPGA as simulation data. During real-time simulation, corresponding switching is performed to solve the circuit. This method enables online modification of switch admittance values ​​when simulating different test conditions, reducing simulation errors introduced by equivalent parasitic parameters of the switches, thereby optimizing the switch admittance parameter settings for different test conditions.

[0017] Specifically, Figure 1 A flowchart of the method for online modification of the admittance value of switching devices in real-time simulation modeling provided by an embodiment of the present invention is shown.

[0018] In a preferred embodiment of the present invention, a method for online modification of the admittance value of a switching device in real-time simulation modeling specifically includes the following steps: Step 1: Load the circuit topology into the host computer and select the switching devices whose admittance values ​​need to be dynamically switched in the circuit model to be simulated.

[0019] In embodiments of the present invention, such as Figure 2 The diagram illustrates a circuit model of the circuit to be simulated provided in this embodiment of the invention. The switching devices in the simulated circuit model include a grid-side circuit breaker and a two-level six-transistor inverter bridge. In the simulated circuit model, the inverter grid-side inductance is 10uH, the inverter's rated output current RMS value is 650A, and the DC voltage is 650V. The switching devices selected for dynamically switching admittance values ​​are: the two-level six-transistor inverter bridge and the circuit breaker. It can be understood that the switching devices include fully controlled devices, semi-controlled devices, and uncontrolled devices. Specifically: fully controlled devices are IGBTs, IGBTs with anti-parallel diodes, MOSFETs, circuit breakers, or ideal switches; semi-controlled devices are thyristors; and uncontrolled devices are diodes.

[0020] Step 2: In the host computer interface, preset the admittance parameter list, calculate and generate the circuit admittance matrix corresponding to multiple test conditions.

[0021] In this embodiment of the invention, the power electronic switch in the circuit is modeled using LC equivalents. When the switch is on, it is equivalent to an inductor, and when it is off, it is equivalent to a capacitor. The back Euler method is used to discretize the switch into conductance and connect it to a current injection source. The Gs values ​​of the switch under different states are preset. Before the simulation starts, the Gs parameters of the switch under each state are set according to the operating conditions to be tested and the switching state of the device, such as... Figure 3The diagram illustrates the actual settings Gs provided in this embodiment of the invention. From left to right, they correspond to circuit breaker opening test scenario one; circuit breaker opening test scenario two; circuit breaker closing test scenario three – setting the inverter output active power to 0; and circuit breaker closing test scenario four – setting the inverter output active current RMS value to 650A. Based on the admittance parameter list data, the admittance matrix of the circuit corresponding to each operating condition is calculated and generated. Each of the four operating conditions corresponds to a set of coefficient equations, which can yield four sets of circuit admittance matrices.

[0022] Step 3: Send multiple circuit admittance matrices to the real-time simulator FPGA as simulation data, and switch them accordingly during real-time simulation to perform circuit solving.

[0023] In this embodiment of the invention, the host computer compresses the admittance matrix of the circuit under each pre-generated operating condition in CSR format and preloads it into the operating condition parameter storage area of ​​the real-time simulator FPGA through the PCIe interface. Before the circuit simulation starts, the real-time simulator loads the admittance matrix corresponding to the default operating condition and starts solving the circuit. During the simulation, the user selects the operating condition in real time through the interface control or external program instructions, and the real-time simulator dynamically loads the corresponding simulation data according to the user instructions.

[0024] In the specific implementation process, the real-time simulation results of the grid-connected inverter dynamically switching Gs under different operating modes are analyzed as follows: Real-time simulation tests were conducted to compare the inverter's phase voltage under different operating modes with varying measured data for Gs settings. The grid-side circuit breaker was disconnected, and the phase voltage of the inverter capacitor was compared between the two sets of circuit breaker Gs parameters. A stronger switching blocking effect results in a lower amplitude of the inverter capacitor phase voltage. When the circuit breaker switch was set to Gs = 1, the simulation step size was 1µs, and the equivalent capacitance value when the switch was disconnected was... Similarly, when Gs is set to 0.1, the equivalent capacitance is 0.1uF. At a 50Hz mains frequency, the capacitive reactance of a 1uF capacitor is... The 0.1uF capacitive reactance is 10 times that of 1uF. Therefore, when the circuit breaker is open, setting Gs to a smaller value will result in better blocking effect. When the grid-side circuit breaker is closed, the switch is equivalent to an inductor. The inductance value is set to 1. When Gs is 0.1, the inductance value is 10uH. The original circuit parameter grid-side inverter inductance is 10uH. At this time, the equivalent inductance of the switch doubles the equivalent inductance value in the actual simulation, which has a significant impact on the circuit parameters. Therefore, for the Gs setting of a circuit breaker, the blocking effect and the on-state inductance are contradictory. A smaller Gs can enhance the blocking effect of the switch, but it will increase the conducting inductance value; a larger Gs will result in a smaller conducting inductance value, but the blocking effect will decrease. Using a method of dynamically modifying the circuit breaker's Gs allows for the selection of an appropriate value for different switching states. For example, setting a large Gs value when the switch is on reduces the conducting inductance, while setting a small Gs value when the switch is off reduces the off-state capacitance and enhances the blocking effect.

[0025] like Figure 4 The diagram shows a calculation simulation efficiency method provided by an embodiment of the present invention. When the circuit breaker is open, the voltage waveforms of capacitor AB line are set for operating conditions 0 and 1. It can be seen that when Gs0.1 is set in operating condition 0, the actual test switch blocking effect is better and conforms to the theoretical judgment.

[0026] By setting the circuit breaker to close and the inverter to output different active currents, the DC-side power values ​​under different inverter Gs settings are compared to quantitatively evaluate the impact of different Gs settings on simulation losses. The simulation losses are determined by setting a fixed active power output from the inverter to the grid and measuring the average value of the DC-side current. When the inverter output power is constant, a higher DC-side current indicates higher losses.

[0027] Set the inverter output active power to 0, and set the Gs parameter to operating conditions 2 and 3 respectively. For example... Figure 5 The simulation efficiency graphs for different admittance parameters provided in this embodiment of the invention are shown. When the inverter bridge Gs is set to 0.1, the average DC-side current is approximately 2A; when the inverter bridge Gs is set to 1, the average DC-side current is approximately 18.8A. It can be seen that when the inverter output power is relatively low, setting a smaller Gs value is beneficial for reducing losses.

[0028] Set the inverter output AC current RMS value to 650A, and set the Gs parameter to operating conditions 3 and 2 respectively. Figure 6 The simulation waveforms of different admittance parameters provided in this embodiment of the invention are shown. When the inverter bridge Gs is set to 1, the average DC-side current is approximately 568.8A; when the inverter bridge Gs is set to 0.1, the average DC-side current is approximately 611A. It can be seen that when the inverter output power is high, setting a larger Gs value is beneficial to reducing losses. Therefore, by modifying the switch admittance value online during simulation of different operating conditions, the simulation error introduced by the equivalent parasitic parameters of the switch can be reduced, thereby achieving optimal setting of the switch admittance parameters for different test conditions.

[0029] It should be understood that although the steps in the flowcharts of the various embodiments of the present invention are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the various embodiments may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these sub-steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least a portion of the sub-steps or stages of other steps.

[0030] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The program can be stored in a non-volatile computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. Any references to memory, storage, databases, or other media used in the embodiments provided in this application can include non-volatile and / or volatile memory. Non-volatile memory can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), or flash memory. Volatile memory can include random access memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in various forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), dual data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous link DRAM (SLDRAM), Rambus direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM), etc.

[0031] The embodiments described above are merely illustrative of several implementations of the present invention, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of the present invention. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these modifications and improvements all fall within the scope of protection of the present invention. Therefore, the scope of protection of this patent should be determined by the appended claims.

Claims

1. A method for online modification of the admittance value of switching devices in real-time simulation modeling, characterized in that, The method specifically includes the following steps: The host computer loads the circuit topology and selects the switching devices that need to dynamically switch the admittance value in the circuit model to be simulated. In the host computer interface, a list of admittance parameters is preset, and the circuit admittance matrices corresponding to multiple test conditions are calculated and generated. Multiple circuit admittance matrices are sent to the real-time simulator FPGA as simulation data, and corresponding switching is performed during real-time simulation to solve the circuit.

2. The method for online modification of the admittance value of switching devices in real-time simulation modeling according to claim 1, characterized in that, The host computer loads the circuit topology and selects the switching devices that need to dynamically switch admittance values ​​in the circuit model to be simulated. The switching devices include fully controlled devices, semi-controlled devices, and uncontrolled devices. The fully controlled devices are IGBTs, IGBTs with anti-parallel diodes, MOSFETs, circuit breakers, or ideal switches; the semi-controlled devices are thyristors; and the uncontrolled devices are diodes.

3. The method for online modification of the admittance value of switching devices in real-time simulation modeling according to claim 1, characterized in that, The step of presetting the admittance parameter list in the host computer interface and calculating and generating circuit admittance matrices corresponding to multiple test conditions specifically includes the following steps: A list of admittance parameters is preset in the host computer interface, and the admittance values ​​of multiple switching devices under multiple test conditions are configured in the admittance parameter list. Based on the multiple admittance values ​​in the admittance parameter list, calculate and generate multiple circuit admittance matrices corresponding to the test conditions.

4. The method for online modification of the admittance value of switching devices in real-time simulation modeling according to claim 3, characterized in that, The step of presetting an admittance parameter list in the host computer interface, wherein the admittance parameter list is configured with admittance values ​​of multiple switching devices under multiple test conditions, specifically includes the following steps: Multiple switching devices in the circuit are modeled using LC equivalents. When the switching device is on, it is equivalent to an inductor; when the switching device is off, it is equivalent to a capacitor. The switching device is discretized using the backward Euler method and is equivalent to a current source injected in parallel with conductance. Construct multiple admittance parameter tables containing default operating conditions, and configure the admittance values ​​of multiple switching devices under multiple operating conditions to be tested; when the switch admittance is not specified in the operating condition to be tested, the default admittance value is used.

5. The method for online modification of the admittance value of switching devices in real-time simulation modeling according to claim 3, characterized in that, In the step of calculating and generating multiple circuit admittance matrices corresponding to the test conditions based on multiple admittance values ​​in the admittance parameter list, each test condition corresponds to a set of coefficient equations.

6. The method for online modification of the admittance value of switching devices in real-time simulation modeling according to claim 1, characterized in that, The step of sending multiple circuit admittance matrices to the real-time simulator FPGA as simulation data and switching them accordingly during real-time simulation to perform circuit solving specifically includes the following steps: Multiple circuit admittance matrices are sent to the real-time simulator FPGA as simulation data. During real-time simulation, the corresponding circuit admittance matrix is ​​switched in real time according to different operating conditions under test. The FPGA simulator performs circuit solving based on the circuit admittance matrix.

7. The method for online modification of the admittance value of switching devices in real-time simulation modeling according to claim 6, characterized in that, During the real-time simulation, the current test condition can be manually switched via the host computer control, or the current test condition can be automatically selected and switched via the conditions calculated and output by the software program.

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