Three-dimensional flash memory array system with vertically stacked multi-layer charge traps

Abstract

The present application relates to the technical field of three-dimensional flash memory, and discloses a three-dimensional flash memory array system with vertically stacked multi-layer charge traps. The vertically stacked storage array module of the system determines an array structure configuration parameter set according to memory cell physical layout information; a gate voltage regulation module generates a gate voltage regulation parameter set based on the parameter set to optimize charge capture efficiency; a charge trap layer management module adjusts trap layer material and distribution accordingly to generate a dynamic regulation result; a data read-write optimization module adjusts voltage pulse parameters based on the result to generate read-write optimization data; and an error detection and correction module optimizes the error correction mechanism accordingly to generate a control table. Through the cooperation of multiple modules, the system realizes integrated optimization of charge storage, regulation, read-write and error correction under a multi-layer stacked structure, and adapts to performance improvement under high-density storage requirements.

Description

Technical Field

[0001] This invention relates to the field of three-dimensional flash memory technology, specifically a three-dimensional flash memory array system with vertically stacked multilayer charge traps. Background Technology

[0002] With the rapid development of digital technology, the demand for data storage has exploded. 3D flash memory, with its high storage density and small size, has become one of the core technologies to meet this demand. Among them, vertically stacked multilayer structures are a key means to improve storage density. By increasing the number of stacking layers, storage capacity can be significantly expanded. However, this process is also accompanied by many technical bottlenecks.

[0003] Existing 3D flash memory often faces the problem of mismatch between the cell array structure and charge storage capacity when stacked in multiple layers. In traditional designs, increasing the number of stacked layers often relies simply on physical space stacking, without fully considering the correlation between charge trap layer thickness, vertical channel diameter, and charge storage capacity at different stacking numbers. This leads to charge saturation or insufficiency in some layers, affecting overall storage efficiency. Meanwhile, gate voltage regulation is a core factor affecting charge capture efficiency. In existing technologies, the control of gate voltage value and rate of change is mostly based on empirical values, lacking dynamic adjustment for voltage distribution uniformity at different stacking numbers. When the number of layers exceeds a certain threshold, the voltage difference between edge layers and middle layers becomes significant, directly resulting in inconsistent charge capture efficiency. Some memory cells fail to effectively capture charge due to insufficient voltage, or experience charge overflow due to excessive voltage.

[0004] The performance stability of the charge trap layer is also a crucial factor restricting the development of 3D NAND flash memory. Existing trap layer materials mostly use single or fixed-ratio components, and their thickness distribution is relatively uniform, making them unsuitable for the charge storage requirements of different locations in multi-layer stacks. During long-term use, the dynamic imbalance between charge capture and release in the trap layer leads to decreased charge retention capacity in some areas due to insufficient trap density, while in other areas, charge leakage occurs due to unreasonable trap energy level parameters, severely impacting the persistence of data storage.

[0005] In the data read / write process, existing technologies are insufficient to handle fluctuations in real-time charge retention rate and data transmission rate. During read / write operations, the voltage pulse width to amplitude ratio is often fixed. When the charge retention rate fluctuates due to environmental changes or usage time, it is difficult to dynamically adjust the parameters, leading to decreased read / write accuracy and even data misreading or writing errors. Furthermore, error detection and correction mechanisms in existing 3D flash memory also have limitations. The parity bit length and error correction algorithm parameters are mostly preset and cannot be adaptively adjusted according to the actual distribution and frequency of error bits. When the error rate increases due to the complexity of multi-layer stacking, the error correction capability is insufficient, further exacerbating data reliability issues. Summary of the Invention

[0006] The purpose of this invention is to provide a three-dimensional flash memory array system with vertically stacked multilayer charge traps to solve the problems mentioned in the background art.

[0007] To achieve the above objectives, the present invention provides a three-dimensional flash memory array system with vertically stacked multilayer charge traps, the system comprising:

[0008] The vertical stacked storage array module uses the physical layout information of the memory cells to call up the number of stacking layers, charge trap layer thickness and vertical channel diameter data of the memory cells, analyzes the degree of matching between the stacking structure and charge storage capacity, determines the arrangement of the memory cell array and the interlayer isolation parameters, and generates an array structure configuration parameter set.

[0009] The gate voltage regulation module configures the parameter set based on the array structure, extracts the voltage value and voltage change rate of the control gate, analyzes the influence of the gate voltage output on the charge capture efficiency, adjusts the voltage distribution uniformity of the control gate, and generates the gate voltage regulation parameter set.

[0010] Based on the gate voltage regulation parameter set, the charge trapping layer management module analyzes the dynamics of charge trapping and release in the trapping layer, adjusts the composition ratio and thickness distribution of the trapping layer material, redistributes the spatial distribution of charge trapping density and trapping energy level parameters, and generates dynamic regulation results of the charge trapping layer.

[0011] Based on the dynamic control results of the charge trap layer, the data read / write optimization module extracts the real-time charge retention rate and data transmission rate during the memory read / write process, analyzes the impact of fluctuation range on the accuracy of data read / write, dynamically adjusts the voltage pulse width and amplitude ratio of the target memory cell, and generates a read / write optimization adjustment dataset.

[0012] The error detection and correction module, based on the read / write optimization adjustment dataset, analyzes the error bit distribution and frequency of the stored data, adjusts the check bit length of the error correction code and the error correction algorithm parameters, and generates a data error detection and correction control table.

[0013] Preferably, the step of obtaining the matching degree between the stacked structure and the charge storage capacity specifically includes:

[0014] Based on the physical layout information of the memory cells, the stacking layer number, trap layer thickness data and vertical channel diameter data of the memory cells are extracted. A spatial region is defined, and matching data within the region is selected. By comparing the data correlation and filtering the data, the stacking layer number and trap layer thickness data are obtained.

[0015] Based on the data on the number of stacked layers and the thickness of the trap layer, the vertical channel is matched and verified. The difference between the number of stacked layers and the thickness of the trap layer is calculated. The stacking structure and the distribution of the trap layer are corrected by combining the channel diameter change. The structural parameters are adjusted by the influence of the channel diameter on the data to obtain the matching situation of the number of stacked layers and the thickness of the trap layer.

[0016] Based on the matching of the number of stacked layers and the thickness of the trap layer, charge storage capacity analysis is performed, capacity analysis standards are set, and the charge storage density under different channel diameter conditions is evaluated in combination with the dynamic changes of memory operation. The capacity indicators are compared and the channel diameter conditions are optimized to obtain the degree of matching between the stacked structure and the charge storage capacity.

[0017] Preferably, the steps for obtaining the array structure configuration parameter set are as follows:

[0018] Based on the degree of matching between the stacked structure and the charge storage capacity, the structural stability and capacity change of the memory under different operating conditions are analyzed, and the stacking distribution of the array is weighted to obtain the preliminary structural configuration requirements of the memory.

[0019] Based on the initial structural configuration requirements of the memory, the charge isolation between layers is analyzed, the relationship between the charge leakage rate between layers and the spacing between memory cells is identified, the array structure configuration parameters are corrected, and the interlayer structure control dataset is obtained by adjusting the dielectric constant and thickness of the interlayer isolation material.

[0020] By combining the interlayer structure control dataset with the charge storage capacity matching results, the interlayer isolation of the array is optimized to match the required isolation effect and capacity requirements, thus obtaining the array structure configuration parameter set.

[0021] Preferably, the steps for obtaining the voltage value and voltage change rate of the control gate specifically include:

[0022] Based on the array structure configuration parameter set, the initial voltage data of the control gate is extracted, the voltage sampling points in each working cycle are screened, and the voltage fluctuation is analyzed by combining the voltage change trend of different regions of the gate to obtain the voltage data of the control gate.

[0023] Based on the voltage data of the control gate, calculations are performed on each voltage sampling point and its corresponding timestamp. By analyzing the relationship between voltage and time, the voltage change at each measurement point is identified. Combined with the gate material characteristic parameters, the voltage changes in different regions are compared to obtain voltage distribution and rate of change data.

[0024] Based on the voltage distribution and rate of change data, the overall voltage stability of the control gate is analyzed, the voltage rate of change is optimized by combining array structure parameters, the impact of voltage fluctuations on charge capture efficiency is analyzed, and the stable voltage configuration under differentiated operating conditions is determined, thereby obtaining the voltage value and voltage rate of change of the control gate.

[0025] Preferably, the step of obtaining the gate voltage regulation parameter set specifically includes:

[0026] Based on the voltage value and voltage change rate of the control gate, the time series of voltage change is determined, the current voltage value is compared with the reference voltage data, the voltage gradient at each moment is analyzed, and corresponding thresholds are defined according to the gate region division to generate a preliminary voltage change parameter set.

[0027] The preliminary voltage variation parameter set is analyzed to analyze the influence of gate voltage on the stability of charge capture efficiency, identify the correlation between voltage and capture efficiency, and calculate the regional voltage stability influence coefficient by adjusting the rise and fall times of the voltage pulse.

[0028] By analyzing the influence coefficient of voltage stability in the region and combining it with the gate voltage variation parameters, the voltage distribution balance is adjusted, the voltage regulation data is optimized, and a set of gate voltage regulation parameters is generated.

[0029] Preferably, the steps for obtaining the dynamic control results of the charge trap layer are as follows:

[0030] Based on the gate voltage regulation parameter set, charge capture data of the trap layer is extracted, the charge capture rate in the differentiated material layer is monitored, and the charge migration characteristics are inferred by combining external environmental factors such as temperature and voltage. The capture and migration rate coefficients are defined, and a dynamic parameter set for capture and migration is generated.

[0031] The influence of the trap migration dynamic parameter set on the charge distribution of the trap layer is analyzed. Based on the requirements of the charge density distribution of the memory cell, the ratio of the trap layer material composition and thickness is optimized. By adjusting the concentration of doping elements in the material, the adjustment coefficient of the charge density distribution trend is calculated, and the charge density regulation result is generated.

[0032] By analyzing the charge density control results, adjusting the ratio of the trap layer material composition to its thickness, allocating the spatial distribution of charge trap density, and combining the capture migration parameters and adjustment coefficients, the dynamic control results of the charge trap layer are obtained.

[0033] Preferably, the step of obtaining the read / write optimization adjustment dataset specifically includes:

[0034] Based on the dynamic control results of the charge trap layer, the charge retention rate and data transmission rate during the real-time read and write process of the memory are monitored, the fluctuation range is identified, hardware noise anomalies are eliminated, and the average fluctuation amplitude of the data is analyzed to obtain the charge retention rate and data transmission rate fluctuation data.

[0035] The impact of the fluctuation range of charge retention rate and transmission rate on the accuracy of data reading and writing is analyzed. Using the known data error rate, the relationship between charge retention rate and transmission rate is analyzed, and the error rate change under the differentiated fluctuation range is calculated to obtain the data affecting the accuracy of reading and writing.

[0036] Based on the data affecting read / write accuracy, the voltage pulse width and amplitude ratio of the target storage unit are dynamically adjusted. Adjustments are made based on the relationship between the data affecting read / write accuracy and the charge retention rate and transmission rate fluctuation range. Voltage pulse parameters and time control ranges are allocated, and a read / write optimization adjustment dataset is generated.

[0037] Preferably, the steps for obtaining the data error detection and correction control table are as follows: based on the read-write optimization adjustment dataset, perform analysis on the distribution and frequency of stored data errors, collect error bit data under differentiated read-write counts, organize the error time distribution, analyze the error rate change trend and classify the data to obtain data error distribution data;

[0038] Based on the error distribution data, the error correction parameters are adjusted, the optimal check bit length and error correction algorithm of the error correction code are analyzed, and the correction effect under the condition of different error rates is compared. The operation conditions of adjusting the check bit length and algorithm complexity are adjusted to obtain the error correction parameters.

[0039] Based on the error correction parameters, the error detection and correction mechanism is adjusted according to the current operating parameters, controlling the variable relationship between check bit length, algorithm complexity and data redundancy, and performing real-time error processing according to the adjusted parameters to obtain a data error detection and correction control table.

[0040] Preferably, the system further includes a heat dissipation dynamic management module, which extracts temperature distribution data and heat dissipation rate during memory operation based on the array structure configuration parameter set and gate voltage control parameter set, analyzes the influence of temperature on the stability of the charge trap layer, adjusts the layout of the heat sink and the speed of the cooling fan, and generates a heat dissipation control parameter set.

[0041] Preferably, the step of obtaining the heat dissipation control parameter set specifically includes:

[0042] Based on the array structure configuration parameter set and gate voltage control parameter set, temperature data and heat flux density of each region of the memory are extracted, temperature sampling points in high-temperature regions are screened, and temperature field distribution is analyzed in combination with the thermal conduction characteristics of the memory structure to obtain temperature distribution and heat dissipation data.

[0043] Based on the temperature distribution and heat dissipation data, the heat dissipation requirements of high-temperature areas are calculated. By analyzing the relationship between temperature and heat dissipation, weak heat dissipation areas are identified. Combined with the thermal conductivity of heat dissipation materials, the effects of different heat dissipation schemes are compared to obtain heat dissipation scheme evaluation data.

[0044] Based on the evaluation data of the heat dissipation scheme, the number and installation position of the heat sink are adjusted, the speed regulation curve of the cooling fan is optimized, the heat dissipation requirements of the high-temperature area are matched with the system energy consumption limit, and a set of heat dissipation control parameters is generated.

[0045] Compared with the prior art, the beneficial effects of the present invention are:

[0046] This vertically stacked multi-layer charge trap 3D flash memory array system achieves breakthroughs over traditional 3D flash memory technology in multiple dimensions through the collaborative operation of multiple modules. Based on the physical layout information of the memory cells, the vertically stacked storage array module deeply analyzes the matching degree between the stacking structure and the charge storage capacity, generating a targeted set of array structure configuration parameters. This process changes the traditional design model that relies solely on experience to set stacking parameters, enabling memory cells of different layers to adapt to their corresponding charge storage requirements according to their own physical characteristics, avoiding capacity waste or overload problems caused by structural mismatch.

[0047] The gate voltage regulation module, based on array structure configuration parameters, focuses on controlling the gate voltage value and rate of change. By analyzing its impact on charge capture efficiency, it adjusts the uniformity of voltage distribution to generate an optimized set of gate voltage regulation parameters. This improvement addresses the pain point of uneven voltage distribution in multilayer stacking, enabling memory cells in edge and middle layers to receive appropriate voltage supplies, ensuring consistent charge capture efficiency across layers, and reducing memory cell failures caused by voltage issues.

[0048] To address the limitations of trap layer materials and distribution, the charge trap layer management module dynamically adjusts the material composition ratio, thickness distribution, trap density, and energy level parameters based on gate voltage control parameters, achieving a dynamic balance between charge capture and release. This dynamic control allows the trap layer to adapt to actual charge storage needs, forming differentiated trap characteristics at different stacking locations. This improves the stability of charge capture, reduces charge leakage during long-term use, and extends the effective lifespan of data storage.

[0049] The data read / write optimization module, based on the dynamic control results of the charge trap layer, extracts real-time fluctuation information of charge retention rate and transmission rate. It then dynamically adjusts the voltage pulse width-to-amplitude ratio accordingly, generating a read / write optimization adjustment dataset. This mechanism allows read / write parameters to adjust in close accordance with changes in charge state. When the charge retention rate decreases or the transmission rate fluctuates, parameter optimization offsets the negative impact of these fluctuations, improving the accuracy of data read / write and reducing read / write errors caused by fixed parameters.

[0050] The error detection and correction module analyzes the distribution and frequency of error bits based on optimized read / write data, adjusts the parity bit length and error correction algorithm parameters, and generates an adaptive control table. This dynamic adjustment enables the error correction mechanism to accurately match the actual error situation. When multi-layer stacking leads to an increase in the error rate or a change in the error distribution, the error correction capability is enhanced, effectively reducing the impact of data errors and improving the overall data reliability of the system. Attached Figure Description

[0051] Figure 1 This is a schematic diagram illustrating the working principle of the three-dimensional flash memory array system with vertically stacked multilayer charge traps described in this invention.

[0052] Figure 2 A flowchart illustrating the matching degree between the stacked structure and the charge storage capacity;

[0053] Figure 3 A flowchart for controlling the gate voltage value and voltage change rate;

[0054] Figure 4 This is a schematic diagram illustrating the working principle of the dynamic heat dissipation management module. Detailed Implementation

[0055] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0056] Please see Figure 1 This invention provides a three-dimensional flash memory array system with vertically stacked multilayer charge traps. The system includes: a vertically stacked memory array module, a gate voltage regulation module, a charge trap layer management module, a data read / write optimization module, and an error detection and correction module. These modules work together to achieve efficient operation of the three-dimensional flash memory. The specific implementation process is as follows:

[0057] The vertical stacked storage array module uses the physical layout information of the memory cells to call up the number of stacking layers, charge trap layer thickness and vertical channel diameter data of the memory cells, analyzes the degree of matching between the stacking structure and charge storage capacity, determines the arrangement of the memory cell array and the interlayer isolation parameters, and generates an array structure configuration parameter set.

[0058] The gate voltage regulation module configures the parameter set based on the array structure, extracts the voltage value and voltage change rate of the control gate, analyzes the influence of the gate voltage output on the charge capture efficiency, adjusts the voltage distribution uniformity of the control gate, and generates the gate voltage regulation parameter set.

[0059] Based on the gate voltage regulation parameter set, the charge trapping layer management module analyzes the dynamics of charge trapping and release in the trapping layer, adjusts the composition ratio and thickness distribution of the trapping layer material, redistributes the spatial distribution of charge trapping density and trapping energy level parameters, and generates dynamic regulation results of the charge trapping layer.

[0060] Based on the dynamic control results of the charge trap layer, the data read / write optimization module extracts the real-time charge retention rate and data transmission rate during the memory read / write process, analyzes the impact of fluctuation range on the accuracy of data read / write, dynamically adjusts the voltage pulse width and amplitude ratio of the target memory cell, and generates a read / write optimization adjustment dataset.

[0061] The error detection and correction module, based on the read / write optimization adjustment dataset, analyzes the error bit distribution and frequency of the stored data, adjusts the check bit length of the error correction code and the error correction algorithm parameters, and generates a data error detection and correction control table.

[0062] Example 1: See Figure 2When the vertically stacked memory array module is running, the matching degree between the stacking structure and the charge storage capacity is first obtained. Based on the physical layout information of the memory cells, the number of stacking layers, trap layer thickness, and vertical channel diameter are extracted. The physical layout information includes basic information such as the arrangement of memory cells in three-dimensional space and the positional relationship of each layer. By analyzing this information, it can be clarified that the number of stacking layers refers to the number of memory cells stacked in the vertical direction, the trap layer thickness refers to the physical thickness of each charge trap layer, and the vertical channel diameter is the cross-sectional diameter of the vertical channel penetrating each layer. A specific spatial region is defined, which typically covers the entire effective working range of the memory array, ensuring that the data within the selected region comprehensively reflects the overall situation of the memory cells. Matching data related to the stacking structure and charge storage are selected within this region. By comparing the correlation between these data, such as whether the trap layer thickness shows a corresponding change pattern as the number of stacking layers increases, data filtering is performed to remove data points that clearly do not conform to the overall trend, ultimately obtaining the effective stacking layer number and trap layer thickness data.

[0063] Based on the obtained data on the number of stacked layers and the thickness of the trap layer, the vertical channel is matched and verified. As the critical path for charge transport, the matching degree between the parameters of the vertical channel and the number of stacked layers and the thickness of the trap layer directly affects the charge transport efficiency. The difference between the number of stacked layers and the thickness of the trap layer is calculated. If the thickness of a trap layer deviates from the expected thickness for the corresponding number of stacked layers by more than a certain range, it needs to be corrected in conjunction with changes in the channel diameter. Changes in the channel diameter alter the resistance to charge transport within the channel. When the channel diameter is too small, charge transport may be obstructed. In this case, it is necessary to adjust the position or thickness of that layer in the stacked structure, and simultaneously correct the distribution of the trap layers so that the trap layers can better cooperate with the channel. By analyzing the specific impact of the channel diameter on the data, such as how changes in diameter cause fluctuations in charge storage, relevant structural parameters are adjusted, such as appropriately increasing or decreasing the channel diameter, or adjusting the thickness distribution of the trap layers, thereby obtaining the matching status between the number of stacked layers and the thickness of the trap layer.

[0064] Based on the matching of the number of stacked layers and the thickness of the trap layer, a charge storage capacity analysis is performed. Capacity analysis criteria are set, including the amount of charge that can be stored per unit area and capacity retention characteristics under different operating conditions. Considering the dynamic changes during memory operation, such as capacity fluctuations during continuous read / write operations and the impact of temperature changes on capacity, the charge storage density under different channel diameters is evaluated. Different channel diameters lead to different charge distributions around the channels, thus affecting the amount of charge stored per unit volume. Capacity metrics such as maximum storage capacity and capacity stability are compared under different channel diameter conditions. Optimization is performed on channel diameter conditions with poor capacity metrics; for example, adjusting the channel diameter to a value more conducive to improving storage density while ensuring unimpeded charge transport. Ultimately, the degree of matching between the stacked structure and the charge storage capacity is obtained.

[0065] After determining the matching degree between the stacking structure and the charge storage capacity, the array structure configuration parameter set is obtained. Based on this matching degree, the structural stability and capacity variation of the memory under differentiated operating conditions are analyzed. Differentiated operating conditions include different read / write frequencies, different operating temperatures, and different data storage volumes. Changes in these conditions will affect the structural stability of the memory. For example, high-frequency read / write may cause fatigue in the connection structure between layers, and high-temperature environments may change the physical properties of materials. These conditions will also cause capacity fluctuations. The stacking distribution of the array is weighted and calculated, assigning different weights to each layer according to its load and importance during the storage process. For example, layers that are frequently read / written have higher weights, while layers that are used as backups or store infrequently used data have lower weights. Through this weighted calculation, the preliminary structural configuration requirements of the memory are obtained, including the initial setting of the arrangement order of each layer and the interlayer distance.

[0066] Based on the initial structural configuration requirements, the charge isolation between layers was analyzed. Interlayer charge isolation is a crucial factor in ensuring data storage accuracy. Poor isolation can lead to charge leakage between layers, causing data confusion or loss. The relationship between interlayer charge leakage rate and cell spacing was identified. By monitoring charge leakage under different spacings, it was found that when the cell spacing is too small, the charge leakage rate increases significantly, while excessive spacing wastes three-dimensional space and reduces storage density. To address this relationship, the array structure configuration parameters were modified, focusing on adjusting the dielectric constant and thickness of the interlayer isolation material. Selecting an isolation material with a higher dielectric constant enhances the charge binding ability and reduces leakage; simultaneously, appropriately increasing the thickness of the isolation material also lengthens the charge leakage path and reduces the leakage rate. These adjustments resulted in an interlayer structure control dataset, which includes parameters for the isolation material and spacing between different layers.

[0067] By combining the interlayer structure control dataset with the charge storage capacity matching results, the interlayer isolation of the array is optimized. During the optimization process, a balance needs to be found between the interlayer isolation effect and the charge storage capacity. This ensures good isolation to prevent charge leakage, while preventing the sacrifice of storage capacity for excessive isolation. For example, if increasing the thickness of the isolation material between a certain layer reduces the leakage rate but causes an excessive decrease in overall storage capacity, the thickness needs to be readjusted, or a material with a higher dielectric constant needs to be used to achieve the same isolation effect with a thinner thickness. By repeatedly adjusting the isolation parameters between each layer, the optimal match between isolation effect and capacity requirements is achieved, ultimately resulting in a set of array structure configuration parameters. This set includes a series of specific parameters such as the number of stacked layers, the thickness of the trap layer in each layer, the diameter of the vertical channel, the dielectric constant and thickness of the interlayer isolation material, and the spacing between memory cells. This provides a detailed structural configuration basis for the actual manufacturing and operation of the memory.

[0068] Example 2: See Figure 3 Based on the array structure configuration parameter set, initial voltage data of the control gate is extracted. This initial voltage data covers the reference voltage values ​​of the memory in different operating modes, including the programming voltage during data writing, the selection voltage during data reading, and the erase voltage during data erasure. Within each operating cycle of the memory, the voltage of the control gate is sampled at preset time intervals. The operating cycle includes the complete process from data input to data output, and the sampling point distribution within each cycle needs to cover the key stages of voltage change, such as the voltage rise stage, the stabilization stage, and the fall stage. By combining the voltage change trends of different regions of the gate and comparing the voltage values ​​of each region at the same time point, voltage fluctuations are analyzed. If the voltage of a certain region fluctuates beyond the normal range within a short period, the location, fluctuation amplitude, and duration of that region need to be recorded. This information is then integrated to form the voltage data of the control gate.

[0069] Based on the voltage data of the control gate, calculations are performed for each voltage sampling point and its corresponding timestamp. By plotting the voltage change over time, the voltage change at each measurement point is identified, i.e., the voltage difference between two adjacent sampling time points. Combined with gate material properties, such as conductivity and coefficient of thermal expansion, the differences in voltage changes in different regions are analyzed. For example, due to different heat dissipation conditions, the voltage change rate in the gate edge region may differ from that in the central region. By comparing these differences, the voltage distribution characteristics and change rate of each region are determined, thus forming voltage distribution and change rate data.

[0070] Based on voltage distribution and rate of change data, the overall voltage stability of the control gate is analyzed. The overall fluctuation level is assessed by calculating the standard deviation of voltage fluctuations across all regions. If the overall fluctuation exceeds a preset range, optimization is performed using array structure parameters, such as adjusting the gate geometry or changing the material distribution ratio, to reduce voltage fluctuations. The impact of voltage fluctuations on charge trapping efficiency is analyzed; excessive fluctuations can lead to unstable charge trapping in the trap layer. By simulating charge trapping under different fluctuation amplitudes, a stable voltage configuration under differentiated operating conditions is determined. For example, a higher stable voltage is used during data write operations, and a lower stable voltage is used during data read operations, ultimately yielding the control gate voltage value and voltage change rate.

[0071] Based on the control gate voltage value and voltage change rate, a time series of voltage changes is determined. This series records the complete change process from the initial voltage to the target voltage, including the voltage value at each time point. The current voltage value is compared with the reference voltage data, the deviation between the two is calculated, and the voltage gradient at each moment, i.e., the voltage change amplitude per unit time, is analyzed. Corresponding thresholds are defined according to the gate region division. The thresholds for different regions are set according to their sensitivity to voltage fluctuations. For example, the threshold for charge-dense regions is lower, and the threshold for edge regions is higher. These settings generate an initial set of voltage change parameters.

[0072] An analysis of the initial voltage variation parameter set was conducted to investigate the impact of gate voltage on the stability of charge capture efficiency. By monitoring the charge capture amount under different voltage parameters, a correlation curve between voltage and capture efficiency was established. Unstable regions in the curves were identified, i.e., areas where voltage changes cause significant fluctuations in capture efficiency. The rise and fall times of the voltage pulses were adjusted to make voltage changes smoother. For example, extending the rise time can reduce the impact of voltage abrupt changes on capture efficiency. Regional voltage stability influence coefficients were calculated under different adjustment schemes; these coefficients reflect the degree of improvement in voltage stability in each region after adjustment.

[0073] By analyzing the influence coefficients of regional voltage stability and combining them with gate voltage variation parameters, the voltage distribution uniformity is adjusted. Regions with lower influence coefficients are optimized in a focused manner, such as by increasing the number of voltage regulation units in those regions, to make the voltage stability of each region more consistent. Voltage regulation data is optimized, including adjusting the timing logic and amplitude control precision of the voltage output to ensure voltage stability across different operating stages. For example, voltage control precision is increased during the critical charge capture stage, while precision is appropriately reduced during non-critical stages to decrease energy consumption, ultimately generating a set of gate voltage regulation parameters.

[0074] Example 3: Based on the gate voltage regulation parameter set, charge capture data of the trap layer is extracted. This data covers information such as the amount of charge captured by the trap layer in different regions per unit time and the retention location of the charge within the trap layer. The capture rate of charge in the differentiated material layers is continuously monitored. Due to differences in chemical composition and crystal structure, different material layers have different adsorption capacities for charge, resulting in significant differences in capture rates. At the same time, the external environmental factors of temperature and voltage are combined to infer the charge migration characteristics. Increased temperature accelerates the thermal motion of charge, increasing the migration speed, while changes in voltage gradient change the direction of charge migration. When the voltage difference increases, the charge is more likely to move to the high-voltage region. The capture rate coefficient λ and the migration rate coefficient μ are defined. λ reflects the proportion of charge captured by the trap layer per unit time, and μ reflects the proportion of charge migrating in the trap layer per unit time. This generates a dynamic parameter set of capture and migration that includes the time-varying values ​​of λ and μ.

[0075] The influence of the trap migration dynamic parameter set on the charge distribution of the trap layer is analyzed. When the value of λ is high and the value of μ is low, charge tends to accumulate in local areas, forming a high-density charge region; when the value of λ is low and the value of μ is high, the charge distribution is more dispersed. Based on the charge density distribution requirements of the storage cells, such as the need for high-density charge in certain regions to achieve multi-bit storage, the ratio of trap layer material composition to thickness is optimized. By adjusting the concentration of doping elements in the material, for example, increasing the nitrogen doping ratio in regions requiring high trapping rates, the energy level structure of the material is altered, enhancing the charge binding ability. The adjustment coefficient θ of the charge density distribution trend is calculated using the following formula:

[0076]

[0077] Where α is the material composition influence factor, reflecting the weight of dopant concentration on the adjustment effect; β is the thickness influence factor, reflecting the weight of trap layer thickness variation on the adjustment effect; and d is the difference between the trap layer thickness and the reference thickness. The θ values ​​for different regions are obtained through this formula, generating the charge density control results.

[0078] Analyzing the charge density control results, the ratio of trap layer material composition to thickness is further adjusted. If the θ value in a certain region does not reach the expected range, it indicates that the charge density distribution in that region does not meet the requirements. The proportion of high-λ value material needs to be increased, or the thickness adjusted, so that the ratio of λ to μ approaches the target range. The spatial distribution of charge trap density is redistributed, with high-density traps set in areas requiring long-term data storage, and structures with moderate trap density and controllable migration rates set in areas with frequent read / write operations. Combining the λ and μ values ​​in the capture and migration parameters with the adjustment coefficient θ, the charge capture efficiency, migration trend, and density control effect of each region are comprehensively evaluated to ensure that the charge distribution in the trap layer meets both storage capacity requirements and adapts to the dynamic changes in data read / write operations, thus obtaining the dynamic control results of the charge trap layer.

[0079] Based on the dynamic control results of the charge trap layer, the charge retention rate and data transfer rate during real-time read / write operations of the memory are monitored. The charge retention rate refers to the proportion of time that charge remains trapped in the layer without being released, while the data transfer rate refers to the amount of data read / written per unit time through the vertical channel. The fluctuation range of both is identified, and the maximum and minimum values ​​are recorded over multiple consecutive read / write cycles. Hardware noise anomalies are eliminated; these anomalies typically exhibit large, instantaneous fluctuations unrelated to charge movement patterns and are often caused by circuit interference or measurement errors. The average fluctuation amplitude of the remaining valid data is calculated to obtain the charge retention rate and data transfer rate fluctuation data, which reflects the performance fluctuation characteristics of the memory under stable operating conditions.

[0080] This study analyzes the impact of charge retention rate and transmission rate fluctuations on data read / write accuracy. Excessive fluctuations in charge retention rate may lead to loss of stored charge during reading, resulting in data errors. Excessive fluctuations in transmission rate can disrupt data transmission timing, increasing the probability of bit errors. Using known data error rates, a correlation model is established between the error rate and the fluctuation ranges of charge retention rate and transmission rate. The error rate changes within different fluctuation ranges are calculated, yielding data on the impact on read / write accuracy. This data includes the expected error rate range under different fluctuation conditions.

[0081] Based on the impact of read / write accuracy on data, the voltage pulse width and amplitude ratio of the target storage cell are dynamically adjusted. When the expected error rate is high, the voltage pulse width is appropriately increased to extend the charge injection or read time, allowing for more complete charge movement; simultaneously, the amplitude ratio is adjusted to optimize the peak-to-trough relationship of the pulse, enhancing selectivity for the target charge. Based on the quantitative relationship between the impact of read / write accuracy on data and the fluctuation range of charge retention rate and transfer rate, voltage pulse parameters and time control ranges are allocated to different storage cells. For example, finer pulse parameters are set for high-fluctuation regions, generating a read / write optimization adjustment dataset.

[0082] Example 4: See Figure 4Based on read / write optimization and dataset adjustment, we conducted an analysis of the distribution and frequency of errors in stored data. Error bit data was collected at different read / write cycles, for example, after the 100th, 500th, and 1000th read / write operations, recording the bit positions of each erroneous bit in the storage array. The temporal distribution of errors was analyzed, and the changes in the number of error bits after 1 hour, 3 hours, and 5 hours of continuous operation were statistically analyzed to observe whether there was a concentration of errors within specific time periods. The error rate trend was analyzed, and the error data was categorized by the physical location of the storage unit (e.g., upper-level, middle-level, and lower-level storage units) and by data type (e.g., text data and image data), resulting in data error distribution data that clearly presents the spatial and temporal distribution characteristics of errors.

[0083] Based on the error distribution data, error correction parameters are adjusted. The optimal parity bit length and error correction algorithm for error correction coding are analyzed. For example, the correction effects of using 8-bit and 16-bit parity bits at different error rates are compared, and the performance of the Hamming code algorithm and the Reed-Solomon algorithm in handling consecutive and random error bits is compared. By simulating the correction process under different error rate conditions, the number of remaining errors after correction is observed. The operating conditions of adjusting the parity bit length and algorithm complexity are adjusted. When the error rate is low, a shorter parity bit and a lower complexity algorithm are used; when the error rate is high, the parity bit length is increased and a higher complexity algorithm is used, thus obtaining the error correction parameters.

[0084] Based on error correction parameters, the error detection and correction mechanism is adjusted according to the current operating parameters. These parameters include data write speed, read frequency, and operating voltage. Different parameter combinations result in different error patterns; for example, high-speed writes are prone to generating consecutive error bits. In such cases, the detection mechanism is adjusted to focus on identifying consecutive errors. The relationship between the check bit length, algorithm complexity, and data redundancy is controlled. While ensuring effective error correction, excessive data redundancy caused by excessively long check bits is avoided. For example, the check bit length is appropriately reduced when storage capacity is limited, while the algorithm is optimized to maintain basic error correction capability. Real-time error processing is performed based on the adjusted parameters. Check bits are generated and stored synchronously during data writing. Error detection is performed first during data reading, and the correction process is immediately initiated upon error detection. This results in a data error detection and correction control table, which clarifies the detection methods and correction steps for different error types and error rates.

[0085] The system also includes a dynamic heat dissipation management module. This module extracts temperature distribution data and heat dissipation rate during memory operation based on the array structure configuration parameter set and gate voltage control parameter set. Temperature distribution data is collected by temperature sensors distributed throughout the memory, including real-time temperature values ​​in the core area, edge area, and gate control circuit area of ​​the memory array. The heat dissipation rate is calculated by measuring the heat dissipated by the memory to the outside environment per unit time, and corrected for changes in ambient temperature. The system analyzes the impact of temperature on the stability of the charge trap layer. Excessive temperature alters the band structure of the trap layer material, reducing its charge trapping ability and leading to a decrease in charge retention rate; excessively low temperature may reduce the conductivity of the material, affecting charge transport efficiency. Based on these effects, the layout of the heat sinks is adjusted: the number and contact area of ​​heat sinks are increased in the higher-temperature core area, while the number of heat sinks is appropriately reduced in the lower-temperature edge area. The fan speed is also adjusted: the fan speed is increased when the temperature exceeds a set threshold and decreased when the temperature is below the threshold. A heat dissipation control parameter set is generated, which includes the specific location and number of heat sinks and the fan speed adjustment curve as a function of temperature.

[0086] Example 5:

[0087] Based on the array structure configuration parameter set and gate voltage control parameter set, temperature data and heat flux density of each region of the memory are extracted. Temperature data is collected by temperature sensors deployed at different locations inside the memory. These sensors are distributed in the upper, middle, and lower layers of the memory array, as well as the edge and center regions of the control gate, enabling real-time recording of temperature values ​​at each point. Heat flux density data is obtained by calculating the heat transfer rate per unit area and correcting for it by considering the thermal conductivity of the memory casing material. Temperature sampling points in high-temperature regions are selected; typically, the core region of the memory array and regions with frequent gate voltage changes tend to experience high temperatures, and the temperature data of these regions are extracted separately. Combining the thermal conductivity characteristics of the memory structure, such as the thermal conductivity of different material layers and interlayer contact thermal resistance, the temperature field distribution is analyzed through a thermal simulation model to understand the heat transfer path and accumulation within the memory, obtaining temperature distribution and heat dissipation data. This data includes the temperature value, heat flow direction, and heat dissipation rate of each region.

[0088] Based on temperature distribution and heat dissipation data, the heat dissipation requirements of high-temperature areas are calculated. The additional heat that needs to be dissipated is determined by the difference between the temperature value of the high-temperature area and a preset safe temperature threshold; the larger the difference, the higher the heat dissipation requirement. By analyzing the relationship between temperature and heat dissipation, a curve of temperature changing with heat dissipation is plotted to observe the temperature decreasing trend under different heat dissipation conditions. Weak heat dissipation areas are identified, which may have difficulty dissipating heat due to structural design, such as areas blocked by other components or areas with poor material thermal conductivity. By comparing the heat dissipation rates of different areas, the location and extent of weak areas are determined. Combining the thermal conductivity of the heat dissipation materials, the effectiveness of different heat dissipation schemes is compared, such as the difference in heat dissipation efficiency between copper and aluminum heat sinks. The degree to which increasing the number of heat sinks and increasing the heat dissipation area improves the heat dissipation effect is evaluated, resulting in heat dissipation scheme evaluation data, which includes the expected temperature reduction and implementation cost under different schemes.

[0089] Based on the heat dissipation scheme evaluation data, the number and installation position of heat sinks were adjusted. The number of heat sinks was increased in areas with weak heat dissipation and high temperatures to ensure direct contact between the heat sinks and the surfaces of these areas, improving heat transfer efficiency. The number of heat sinks was reduced in areas with lower temperatures or better heat dissipation to reduce overall cost and space occupation. The fan speed adjustment curve was optimized, setting multiple speed levels based on temperature distribution data. When the temperature is within a safe range, the fan operates at the lowest speed; when the temperature approaches a threshold, the fan speed gradually increases; when the temperature exceeds the threshold, the fan operates at the highest speed. Simultaneously, the heat dissipation requirements of high-temperature areas were matched with system energy consumption limitations. While meeting heat dissipation requirements, excessive energy consumption caused by prolonged high-speed fan operation was avoided by dynamically adjusting the fan speed to keep energy consumption within a reasonable range. Based on these adjustments, a heat dissipation control parameter set was generated. This parameter set includes information such as the specific number of heat sinks, installation coordinates, and the correspondence between fan speed and temperature, ensuring that the memory maintains a suitable temperature under various operating conditions, guaranteeing the stability of the charge trap layer and overall performance.

[0090] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article, or apparatus.

[0091] Although embodiments of the invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the appended claims and their equivalents.

Claims

1. A three-dimensional flash memory array system of vertically stacked multi-layer charge traps, characterized in that, The system comprises: The vertically stacked memory array module calls the data of the number of stacked layers, the thickness of the charge trap layer and the diameter of the vertical channel of the memory cell according to the physical layout information of the memory cell, analyzes the matching degree of the stacked structure and the charge storage capacity, determines the arrangement mode and the interlayer isolation parameter of the memory cell array, and generates the array structure configuration parameter set; The gate voltage regulation module extracts the voltage value and voltage change rate of the control gate based on the array structure configuration parameter set, analyzes the influence of the gate voltage output on the charge capture efficiency, adjusts the voltage distribution uniformity of the control gate, and generates the gate voltage regulation parameter set; The charge trap layer management module analyzes the capture and release dynamics of the charge in the trap layer based on the gate voltage regulation parameter set, adjusts the component ratio and thickness distribution of the trap layer material, reallocates the spatial distribution of the charge trap density and the trap energy level parameter, and generates the dynamic regulation result of the charge trap layer; The data read-write optimization module extracts the real-time charge retention rate and data transmission rate in the memory read-write process based on the dynamic regulation result of the charge trap layer, analyzes the influence of the fluctuation range on the data read-write accuracy, dynamically adjusts the voltage pulse width and amplitude ratio of the target memory cell, and generates the read-write optimization adjustment data set; The error detection and correction module analyzes the error bit distribution and occurrence frequency of the stored data based on the read-write optimization adjustment data set, adjusts the check bit length and error correction algorithm parameter of the error correction code, and generates the data error detection and correction control table.

2. The vertical stack of multi-layer charge trap 3D flash memory array system of claim 1, wherein, The obtaining step of the matching degree of the stacked structure and the charge storage capacity is specifically: According to the physical layout information of the memory cell, the data of the number of stacked layers, the thickness of the trap layer and the diameter of the vertical channel of the memory cell are extracted, the space region is set, the matching data in the region is selected, the data correlation is compared and the data is screened to obtain the data of the number of stacked layers and the thickness of the trap layer; Based on the data of the number of stacked layers and the thickness of the trap layer, the vertical channel is matched and verified, the difference between the number of stacked layers and the thickness of the trap layer is calculated, the stacked structure and the trap layer distribution are corrected combined with the channel diameter change, the structure parameters are adjusted through the influence of the channel diameter on the data, and the matching condition of the number of stacked layers and the thickness of the trap layer is obtained; Based on the matching condition of the number of stacked layers and the thickness of the trap layer, the charge storage capacity analysis is performed, the capacity analysis standard is set, the charge storage density under the condition of different channel diameters is evaluated combined with the dynamic change of the memory operation, the capacity index is compared and the channel diameter condition is optimized, and the matching degree of the stacked structure and the charge storage capacity is obtained.

3. The vertical stack of multi-layer charge trap 3D flash memory array system of claim 2, wherein, The obtaining step of the array structure configuration parameter set is specifically: Based on the matching degree of the stacked structure and the charge storage capacity, the structural stability and capacity change of the memory under different operating conditions are analyzed, and the weighted calculation of the stacked distribution of the array is performed to obtain the preliminary structure configuration requirement of the memory; Based on the preliminary structure configuration requirement of the memory, the charge isolation condition between layers is analyzed, the interlayer charge leakage rate and the distance relationship between memory cells are identified, the array structure configuration parameter is corrected, the dielectric constant and thickness of the interlayer isolation material are adjusted to obtain the interlayer structure regulation data set; The interlayer structure regulation data set is matched with the charge storage capacity matching result, interlayer isolation of the array is optimized, a required isolation effect and capacity requirement are matched, and an array structure configuration parameter set is obtained.

4. The vertical stack of multi-layer charge trap 3D flash memory array system of claim 3, wherein, The obtaining of the voltage value and the voltage change rate of the control gate specifically includes: Based on the array structure configuration parameter set, initial voltage data of the control gate are extracted, voltage sampling points in each working cycle are screened, voltage fluctuation is analyzed in combination with voltage change trends of different regions of the gate, and voltage data of the control gate are obtained; Based on the voltage data of the control gate, each voltage sampling point and a corresponding time stamp are calculated, a voltage change amount of each measurement point is identified by analyzing the relationship between voltage and time, voltage change conditions of different regions are compared in combination with gate material characteristic parameters, voltage distribution and change rate data are obtained; Based on the voltage distribution and change rate data, overall voltage stability of the control gate is analyzed, voltage change rate is optimized in combination with array structure parameters, an influence of voltage fluctuation on charge capture efficiency is analyzed, stable voltage configuration under differential operation conditions is determined, and the voltage value and the voltage change rate of the control gate are obtained.

5. The vertical stack of multi-layer charge trap 3D flash memory array system of claim 4, wherein, The obtaining of the gate voltage regulation parameter set specifically includes: Based on the voltage value and the voltage change rate of the control gate, a time sequence of voltage change is determined, a current voltage value is compared with reference voltage data, a voltage gradient at each moment is analyzed, and a preliminary voltage change parameter set is generated according to definition of a corresponding threshold value according to gate region division; The preliminary voltage change parameter set is analyzed, an influence of gate voltage on charge capture efficiency stability is analyzed, relevance between voltage and capture efficiency is identified, and a region voltage stability influence coefficient is calculated by adjusting rising and falling edges of a voltage pulse; By analyzing the region voltage stability influence coefficient, in combination with gate voltage change parameters, voltage distribution uniformity is adjusted, voltage regulation data is optimized, and the gate voltage regulation parameter set is generated.

6. The vertical stack of multi-layer charge trap 3D flash memory array system of claim 5, wherein, The obtaining of the charge trap layer dynamic regulation result specifically includes: Based on the gate voltage regulation parameter set, charge capture data of the trap layer are extracted, a charge capture rate in differential material layers is monitored, charge migration characteristics are inferred in combination with external environmental factors such as temperature and voltage, a capture and migration rate coefficient is defined, a capture and migration dynamic parameter set is generated; An influence of the capture and migration dynamic parameter set on charge distribution of the trap layer is analyzed, a proportion of trap layer material components and thickness is optimized according to a requirement of storage unit charge density distribution, an adjustment coefficient of charge density distribution trend is calculated by adjusting a concentration of a doping element in the material, and a charge density regulation result is generated; The charge density regulation result is analyzed, a proportional relationship of trap layer material components and thickness is adjusted, a spatial distribution of charge trap density is allocated, and a charge trap layer dynamic regulation result is obtained in combination with the capture and migration parameters and the adjustment coefficient.

7. The vertical stack of multi-layer charge trap 3D flash memory array system of claim 6, wherein, The obtaining of the read-write optimization adjustment data set specifically includes: Based on the dynamic regulation result of the charge trap layer, the charge retention rate and data transmission rate in the real-time read-write process of the memory are monitored, the fluctuation range is identified, the hardware noise abnormal value is eliminated, the average fluctuation amplitude of the data is analyzed, and the fluctuation data of the charge retention rate and transmission rate are obtained. The influence of the fluctuation range of the charge retention rate and transmission rate on the data read-write accuracy is analyzed, the relationship between the charge retention rate and transmission rate is analyzed by using the known data error rate, the error rate change under the differential fluctuation range is calculated, and the read-write accuracy influence data are obtained. According to the read-write accuracy influence data, the voltage pulse width and amplitude ratio of the target storage unit are dynamically adjusted, the relationship between the read-write accuracy influence data and the fluctuation range of the charge retention rate and transmission rate is adjusted, the voltage pulse parameter and time control range are distributed, and the read-write optimization adjustment data set is generated.

8. The vertical stack of multi-layer charge trap 3D flash memory array system of claim 7, wherein, The data error detection and correction control table acquisition step is specifically: based on the read-write optimization adjustment data set, the storage data error distribution and occurrence frequency are analyzed, the error bit data under the differential read-write times are collected, the error time distribution is arranged, the error rate change trend is analyzed, and the data is classified, and the data error distribution data are obtained. Based on the data error distribution data, the error correction parameter is adjusted, the optimal check bit length and error correction algorithm of the error correction coding are analyzed, the correction effect under the differential error rate condition is compared, the operation condition of the check bit length and algorithm complexity is adjusted, and the error correction parameter is obtained. Based on the error correction parameter, the error detection and correction mechanism is adjusted according to the current operation parameter, the variable relationship among the check bit length, algorithm complexity and data redundancy is controlled, real-time error processing is performed according to the adjusted parameter, and the data error detection and correction control table is obtained.

9. The vertical stack of multi-layer charge trap 3D flash memory array system of claim 1, wherein, The system further comprises a heat dissipation dynamic management module, which extracts the temperature distribution data and heat dissipation rate of the memory during operation based on the array structure configuration parameter set and gate voltage regulation parameter set, analyzes the influence of temperature on the stability of the charge trap layer, adjusts the layout of the heat sink and the speed of the cooling fan, and generates a heat dissipation control parameter set.

10. The vertical stack of multi-layer charge trap three-dimensional flash memory array system of claim 9, wherein, The acquisition step of the heat dissipation control parameter set is specifically: Based on the array structure configuration parameter set and gate voltage regulation parameter set, the temperature data and heat flow density of each region of the memory are extracted, the temperature sampling points of the high-temperature region are screened, the temperature field distribution is analyzed in combination with the heat conduction characteristics of the memory structure, and the temperature distribution and heat dissipation data are obtained; Based on the temperature distribution and heat dissipation data, the heat dissipation demand of the high-temperature region is calculated, the heat dissipation weak area is identified by analyzing the relationship between temperature and heat dissipation, the heat dissipation effect of different schemes is compared in combination with the thermal conductivity of the heat dissipation material, and the heat dissipation scheme evaluation data are obtained; Based on the heat dissipation scheme evaluation data, the number and installation position of the heat sink are adjusted, the speed regulation curve of the cooling fan is optimized, the heat dissipation demand of the high-temperature region is matched with the system energy consumption limit, and the heat dissipation control parameter set is generated.

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