Circuit board production method and circuit board

Abstract

The invention discloses a circuit board production method and a circuit board. The method comprises the following steps: laminating at least two substrates and at least one prepreg to obtain a first circuit board; performing drilling and copper deposition treatment on the first circuit board to obtain at least one target via hole; performing resin hole plugging on the target via hole to obtain a second circuit board; performing uniform copper deposition electroplating on the target surface with the target via hole on the second circuit board to obtain a third circuit board; grinding and polishing the hole filling copper layer on the third circuit board to obtain a fourth circuit board with a target copper layer; and performing line forming processing on the fourth circuit board to obtain a target circuit board. The generated hole filling copper layer is filled with the first groove generated after the resin is cooled, and the hole filling copper layer is ground and polished to obtain the target copper layer, so that the flatness of the surface of the circuit board can be improved, and the welding quality of the chip is ensured.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of circuit board manufacturing, and in particular to a circuit board production method and a circuit board. BACKGROUND

[0002] In the production process of a circuit board, a resin plug hole method is used to fill and level the via holes on the circuit board with resin. However, resin has the characteristics of thermal expansion and cold contraction, which can easily cause the resin on the via hole to have a groove after the plug hole is completed, affecting the flatness of the surface of the circuit board; and in the chip welding area, the groove can easily affect the welding quality of the chip on the circuit board. SUMMARY

[0003] Therefore, the embodiments of the present application aim to provide a circuit board production method and a circuit board, which can improve the flatness of the surface of the circuit board and ensure the welding quality of the chip.

[0004] In a first aspect, the embodiments of the present application provide a circuit board production method, comprising: obtaining a first circuit board by laminating at least two substrates and at least one prepreg; obtaining at least one target via hole by performing a drilling and copper plating process on the first circuit board; obtaining a second circuit board by performing a resin plug hole on the target via hole, wherein the target via hole on the second circuit board has a first groove after the resin is cooled; obtaining a third circuit board by performing a uniform copper plating on a target surface of the second circuit board having the target via hole, wherein the target surface on the third circuit board is covered with a hole filling copper layer, the hole filling copper layer has a second groove on the target via hole, and the second groove is covered on the first groove; obtaining a fourth circuit board having a target copper layer by performing a polishing process on the hole filling copper layer, wherein the flatness of the target copper layer is greater than or equal to a preset flatness; obtaining a target circuit board by performing a circuit forming process on the fourth circuit board.

[0005] In some optional embodiments, the obtaining at least one target via hole by performing a drilling and copper plating process on the first circuit board comprises: obtaining at least one first via hole by performing a drilling process on the first circuit board; obtaining a second via hole by performing a first roughening process on the first via hole, wherein the second via hole has a first roughness; obtaining a third via hole by performing a copper plating process on the second via hole; The third via hole is subjected to a second roughening treatment to obtain the target via hole, and an inner wall of the target via hole has a second roughness, which is greater than the first roughness.

[0006] In some optional embodiments, the second via hole obtained after the first roughening treatment of the first via hole includes: Obtaining substrate information and prepreg information, the substrate information representing material information of each substrate, and the prepreg information representing material information of each prepreg; Obtaining roughening liquid information, the roughening liquid information representing concentration information, component information and temperature information of the roughening liquid; Generating a first roughening curve of each substrate according to the roughening liquid information and the substrate information, the first roughening curve representing a relationship between substrate roughness and time; Generating a second roughening curve of each prepreg according to the roughening liquid information and the prepreg information, the second roughening curve representing a relationship between prepreg and time; Obtaining a first roughening weight value of each substrate and a second roughening weight value of each prepreg; Multiplying the roughness at each time point on the first roughening curve by the first roughening weight value to obtain a first weight roughening curve; Multiplying the roughness at each time point on the second roughening curve by the second roughening weight value to obtain a second weight roughening curve; Superimposing the first weight roughening curve and the second weight roughening curve to obtain a comprehensive roughening curve; Determining a first roughening time according to the first roughness and the comprehensive roughening curve; Roughening the first via hole by a roughening liquid within the first roughening time to obtain the second via hole.

[0007] In some optional embodiments, the third circuit board obtained after the target surface of the second circuit board having the target via hole is subjected to uniform copper plating includes: The first groove is subjected to copper plating to obtain a copper-plated groove; Obtaining a first depth and a groove curvature of the copper-plated groove; Determining a first copper layer thickness of the hole-filling copper layer according to the first depth and the groove curvature; Placing the target surface of the second circuit board in an electroplating tank, and determining an electroplating time according to an electroplating curve and the first copper layer thickness, the electroplating curve representing a relationship curve between an electroplated copper layer thickness and time of the electroplating tank; The target surface is subjected to electroplating within the electroplating time to obtain the third circuit board.

[0008] In some optional embodiments, the polishing and grinding treatment on the hole-filling copper layer to obtain a fourth circuit board with a target copper layer comprises: ceramic grinding on the hole-filling copper layer to obtain a first ground copper layer, the first ground copper layer being at the same horizontal position as the bottom of the second groove; non-woven fabric grinding on the first ground copper layer to obtain a second ground copper layer; polishing on the second ground copper layer to obtain the target copper layer.

[0009] In some optional embodiments, the ceramic grinding on the hole-filling copper layer to obtain a first ground copper layer comprises: obtaining a second depth of the second groove; configuring the second depth as a copper layer removal depth; ceramic grinding on the hole-filling copper layer according to the copper layer removal depth to obtain the first ground copper layer.

[0010] In some optional embodiments, the ceramic grinding on the hole-filling copper layer according to the copper layer removal depth to obtain the first ground copper layer comprises: controlling a first grinding head to press the hole-filling copper layer with a first pressure, and recording a first grinding thickness per unit time after ceramic grinding on the hole-filling copper layer, the first grinding head being provided with ceramic; obtaining a second pressure by increasing the unit pressure of the first grinding head, and recording a second grinding thickness per unit time after ceramic grinding on the hole-filling copper layer with the second pressure; in the case that the second grinding thickness is greater than the first grinding thickness, obtaining a third pressure by increasing the unit pressure of the second pressure, and controlling the first grinding head to perform ceramic grinding on the hole-filling copper layer with the third pressure, and recording a third grinding thickness per unit time; in the case that the third grinding thickness is greater than the second grinding thickness, configuring the third pressure as a target pressure; in the case that the third grinding thickness is less than or equal to the second grinding thickness, configuring the second pressure as the target pressure; in the case that the second grinding thickness is less than or equal to the first grinding thickness, obtaining a fourth pressure by subtracting the unit pressure from the first pressure, and controlling the first grinding head to perform ceramic grinding on the hole-filling copper layer with the fourth pressure, and recording a fourth grinding thickness per unit time; in the case that the fourth grinding thickness is less than the first grinding thickness, configuring the first pressure as the target pressure; in the case that the fourth grinding thickness is greater than or equal to the first grinding thickness, configuring the fourth pressure as the target pressure; The first polishing head is controlled to polish the hole-filling copper layer at the target pressure, and the polishing is stopped when the polishing depth is equal to the copper layer removal depth, so as to obtain the first polished copper layer.

[0011] In some optional embodiments, the first copper layer is subjected to non-woven fabric polishing by a second polishing head provided with a non-woven fabric, and the second polished copper layer obtained after the first polished copper layer is subjected to non-woven fabric polishing comprises the following steps: The historical polishing information of the second polishing head is obtained, and the historical polishing information represents the historical polishing times, historical polishing time and historical polishing pressure of the second polishing head. The damage coefficient of the second polishing head is determined according to the historical polishing times, historical polishing time and historical polishing pressure. The second flatness of the second polished copper layer and the first flatness of the first polished copper layer are obtained. The target polishing time and target polishing pressure of the second polishing head are determined according to the flatness difference between the second flatness and the first flatness and the damage coefficient. The second polished copper layer is obtained by controlling the second polishing head to polish the first copper layer with the non-woven fabric at the target polishing pressure for the target polishing time.

[0012] In some optional embodiments, the target circuit board obtained after the fourth circuit board is subjected to the circuit forming treatment comprises the following steps: The fifth circuit board is obtained after the outer circuit of the fourth circuit board is manufactured. The sixth circuit board is obtained after the outer circuit of the fifth circuit board is subjected to circuit detection, impedance test and solder mask in sequence. The target circuit board is obtained after the sixth circuit board is subjected to gold plating and cutting forming.

[0013] In the second aspect, the embodiments of the present application provide a circuit board manufactured by the circuit board production method.

[0014] The embodiments of the present application have the following beneficial effects: the embodiments of the present application provide a circuit board production method, comprising: obtaining a first circuit board by laminating at least two substrates and at least one prepreg; obtaining at least one target via hole by performing a copper plating drilling process on the first circuit board; obtaining a second circuit board by performing resin plug processing on the target via hole; performing uniform copper plating on a target surface of the second circuit board having the target via hole to obtain a third circuit board, wherein the target surface of the third circuit board is covered with a hole-filling copper layer, the hole-filling copper layer has a second recess on the target via hole, and the second recess covers the first recess; performing polishing processing on the hole-filling copper layer to obtain a fourth circuit board having a target copper layer, wherein the flatness of the target copper layer is greater than or equal to a preset flatness; and performing circuit forming processing on the fourth circuit board to obtain a target circuit board. By performing copper plating on the target via hole after resin plug processing, the hole-filling copper layer fills the first recess generated after the resin cools, and the target copper layer is obtained after polishing the hole-filling copper layer, so that the first recess is covered by the target copper layer, thereby improving the flatness of the surface of the circuit board and ensuring the welding quality of the chip. BRIEF DESCRIPTION OF DRAWINGS

[0015] Figure 1 is a step flow chart of a circuit board production method provided by the embodiments of the present application; Figure 2 is a schematic diagram of filling the first recess.

[0016] Reference signs: target surface 100, target via hole 110, first recess 120, hole-filling copper layer 130, second recess 131, target copper layer 140. DETAILED DESCRIPTION

[0017] The embodiments of the present application will be described in detail below, and examples of the embodiments are shown in the drawings, wherein the same or similar reference signs represent the same or similar elements or elements having the same or similar functions throughout. The embodiments described below by referring to the drawings are exemplary and are only used to explain the present application, and cannot be understood as a limitation of the present application.

[0018] In the description of the present application, it should be understood that the orientation description, such as the orientation or position relationship indicated by up, down, front, back, left, right, etc., is based on the orientation or position relationship shown in the drawings, and is only for the convenience of describing the present application and simplifying the description, and therefore cannot be understood as a limitation of the present application, which does not indicate or imply that the devices or elements referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation of the present application.

[0019] In the description of the present application, the meaning of one or more is one or more, the meaning of multiple is more than two, greater than, less than, more than, etc. is understood as not including the number, above, below, within, etc. is understood as including the number. If the first, second is described, it is only used for the purpose of distinguishing technical features, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features or implicitly indicating the sequence of indicated technical features.

[0020] In the description of the present application, unless otherwise explicitly limited, the words such as setting, installing, connecting, etc. should be understood in a broad sense, and those skilled in the art can reasonably determine the specific meaning of the above words in the present application in combination with the specific content of the technical scheme.

[0021] The circuit board production method provided by the embodiment of the present application comprises the following steps: The circuit board production method comprises the following steps: The first circuit board is obtained by pressing at least two substrates and at least one prepreg; the target via hole is obtained by drilling and copper plating treatment on the first circuit board; the second circuit board is obtained by resin plug hole treatment on the target via hole, and the target via hole on the second circuit board has a first groove after resin cooling; the third circuit board is obtained by uniform copper plating on the target surface of the second circuit board with the target via hole; the target copper layer is obtained by polishing treatment on the hole filling copper layer on the third circuit board, and the flatness of the target copper layer is greater than or equal to the preset flatness; and the target circuit board is obtained by circuit forming treatment on the fourth circuit board. By copper plating on the target via hole after resin plug hole treatment, the first groove generated after resin cooling is filled with the hole filling copper layer, and the target copper layer is obtained after polishing the hole filling copper layer. By covering the first groove with the target copper layer, the flatness of the circuit board surface can be improved, and the welding quality of the chip can be ensured.

[0022] The circuit board production method of the embodiment of the present application is further described below.

[0023] Referring to Figures 1-2 , Figure 1 A flow chart of a circuit board production method provided by the embodiment of the present application is provided, and the circuit board production method comprises the following steps but is not limited to the following steps: S100, at least two substrates and at least one prepreg are pressed to obtain a first circuit board.

[0024] Specifically, the circuit board of the present application is obtained by pressing at least two substrates and at least one prepreg. The number of substrates and prepregs is determined according to actual needs, and is not limited herein. In some embodiments, the circuit board of the present application is a gold-filled board, and the gold-filled board is specifically an eight-layer board.

[0025] The first surface and the second surface of the substrate are provided with a copper layer; the copper layer can be deposited on the corresponding surface of the substrate by processes such as electroplating, sputtering, etc. The material, size of the substrate, and the characteristics of the copper layer, etc. parameters are selected and customized according to the design requirements of the final product, and are not specifically limited. For example, for some circuits that need to withstand large current, the thickness of the copper layer can be increased to reduce the resistance.

[0026] The prepreg, also known as prepreg, is usually made of reinforced materials such as glass fiber cloth and thermosetting resins such as epoxy resin. In the subsequent manufacturing process, the prepreg plays a dual role of bonding and insulation. It can firmly bond the substrates together while providing good insulation performance to prevent short circuits between different layers of circuits and other problems.

[0027] S200, after the first circuit board is drilled and copperized to obtain at least one target via hole 110.

[0028] Specifically, a through hole that penetrates the multi-layer substrate and the prepreg is drilled at a predetermined position of the first circuit board (according to the interlayer connection requirement of the circuit design) by mechanical or laser method (not specifically limited). After drilling, some drillings, resins and other contaminants are left on the hole wall, which will affect the quality and reliability of the subsequent copper deposition. Therefore, it is necessary to carry out drill cleaning treatment, usually using chemical solutions such as strong alkaline or strong oxidizing solutions to remove these contaminants. For example, using potassium permanganate solution for drill cleaning can oxidize and remove organic contaminants on the hole wall, making the hole wall clean and rough, so that the copper layer can be better attached during subsequent copper plating. After drill cleaning, copper deposition is carried out; copper deposition is a process of forming a thin copper layer on the hole wall by chemical deposition, which serves as the basis for subsequent copper plating; in this process, copper ions in the chemical plating solution are reduced on the surface of the hole wall to deposit copper atoms. After drilling and copper deposition, a copper layer is deposited on the hole wall of the first circuit board, realizing the electrical connection between different layers, and continuing to electroplate a copper layer on the hole wall according to the corresponding design requirements, thereby thickening the copper layer of the hole wall to obtain the target via hole 110.

[0029] In some optional embodiments, the first circuit board is drilled and copperized to obtain at least one target via hole 110, comprising: S210, after the first circuit board is drilled to obtain at least one first via hole; Specifically, a first via hole is formed at a predetermined location on the first circuit board, penetrating the multilayer substrate, through mechanical or laser processing. During drilling, precise drilling is achieved using CCD vision positioning and a CNC drilling machine, based on the interlayer connection coordinates of the circuit design.

[0030] S220, after performing a first roughening process on the first via, a second via is obtained, and the second via has a first roughness. Specifically, the first roughening process involves chemically etching to remove impurities from the walls of the first via and forming a uniform micro-rough surface (with a first roughness), thereby improving the adhesion of the subsequent copper plating layer and preventing it from peeling off. The specific process includes: Pretreatment (drilling and cleaning): Immerse the first circuit board in an alkaline swelling solution at 60-70℃. 5–8 minutes, allowing the resin on the pore walls to swell and soften; Oxidative etching: Treat with an acidic potassium permanganate solution at 70-80℃ for 10-12 minutes to etch away the drill residue and surface resin, exposing the ends of the glass fiber.

[0031] After etching, honeycomb-like micro-depressions (resin area) and slight scratches (copper foil area) are formed on the hole walls. The first roughness is sufficient to ensure adequate adhesion of the copper plating layer without causing damage to the hole wall structure due to excessive roughness.

[0032] Post-treatment: with sodium bisulfite solution After neutralizing the residual oxidant, rinsing with deionized water and drying at 80°C for 5 minutes, a second via is obtained.

[0033] S230, after performing copper plating on the second via, a third via is obtained; Specifically, a conductive layer is formed by chemical copper plating, and then thickened by electroplating copper, so that the second via is transformed from an insulating through-hole into a conductive third via, thereby achieving electrical conduction in the multilayer circuit.

[0034] Chemical copper plating includes: immersing the circuit board in a palladium salt activating solution ( , At a temperature of 40-45℃, palladium particles (catalytic centers) are uniformly adsorbed on the pore walls for 6-8 minutes. After reacting in an alkaline copper precipitation solution for 15-20 minutes, 0.5-1 [units of a specific thickness] are deposited on the first roughened pore walls. A thick, uniform copper layer completely covers the uneven structure of the hole walls, forming a continuous conductive layer. Electroplating includes: electroplating in an acidic copper plating solution for 20-30 minutes; the total copper layer thickness reaches 15-25 mm. Thus, the third via is obtained.

[0035] S240, performing a second roughening treatment on the third via hole to obtain the target via hole 110, an inner wall of the target via hole 110 having a second roughness, the second roughness being greater than the first roughness.

[0036] Specifically, the second roughening is roughening etching on the copper layer surface of the third via hole to form a second roughness higher than the first roughness, to provide a mechanical locking site for the subsequent resin plug hole or filling hole copper layer 130, and to improve the bonding force. The specific process parameters are as follows: through an acidic ammonium persulfate system with a temperature of 25-30℃, processing for 3-5min, etching the copper layer thickness of 0.2-0.3 (only remove the surface of the copper layer, without affecting the conductivity of the via hole); after etching, the surface of the copper layer forms a dense concave-convex structure like a ravine. The second roughness is greater than the first roughness, so that the resin is embedded to form a mechanical occlusion, avoiding the separation of the resin and the copper layer. Finally, the residual roughening liquid is rinsed with deionized water, and weakly acidic passivation treatment is performed for 1-2min to prevent copper layer oxidation, and finally the target via hole 110 is obtained.

[0037] In some optional embodiments, the first roughening treatment on the first via hole to obtain the second via hole comprises: S2201, obtaining substrate information and prepreg information, the substrate information representing material information of each substrate, and the prepreg information representing material information of each prepreg; Specifically, the substrate information is the core material parameter of each substrate, including: base material type (such as the epoxy resin content of FR-4 substrate, glass fiber cloth model, etc.); copper foil type (electrolytic copper / rolled copper, surface treatment state, such as brown or black); etching resistance parameter.

[0038] The prepreg information is the material information of each prepreg, including: resin system (epoxy resin / modified epoxy resin); resin content (such as 40%-60%); glass fiber cloth density (affecting the degree of fiber exposure after etching); curing degree (residual active group content after pressing, affecting the reaction activity with the roughening liquid).

[0039] S2202, obtaining roughening liquid information, the roughening liquid information representing concentration information, component information and temperature information of the roughening liquid; Specifically, the roughening liquid information includes concentration information, component information and temperature information. The concentration information is the concentration of the key components (such as the concentration of potassium permanganate , the concentration of sulfuric acid ); the component information is the component information of the main etchant , the accelerator , the inhibitor (such as organic amine, adjusting the etching selectivity of the resin) constituting the roughening liquid; the temperature information is the working temperature of the roughening liquid (70-80℃).

[0040] S2203, generate a first roughing curve of each substrate according to the roughing liquid information and the substrate information, the first roughing curve representing a relationship between substrate roughness and time; Specifically, according to the substrate information and the roughing liquid parameters, the roughness-time curve of different materials is generated through experiments or database fitting to quantify the etching process. In the roughing liquid, the resin is gradually etched, the glass fiber is exposed, and the copper foil surface is micro-etched, and the roughness-time curve shows a rapid rise first and then a slow rise. The horizontal axis of the first roughing curve is time, and the vertical axis is roughness.

[0041] S2204, generate a second roughing curve of each prepreg according to the roughing liquid information and the prepreg information, the second roughing curve representing a relationship between the prepreg and time; Specifically, the resin content of the prepreg is higher, and the glass fiber is finer, so the roughness growth rate after etching is different from that of the substrate, and the curve slope is steeper. Under the same time, the roughness of the prepreg is usually higher than that of the substrate; in the later stage, the roughness growth slows down due to excessive exposure of the fiber. Therefore, according to the specific prepreg information, the second roughing curve of each prepreg can be generated.

[0042] S2205, obtain the first roughing weight value of each substrate and the second roughing weight value of each prepreg; Specifically, the area proportion of the material on the hole wall and the influence weight of roughness on subsequent copper deposition are comprehensively considered.

[0043] Area proportion: If the substrate accounts for 60% and the prepreg accounts for 40% in the hole wall, the basic weight can be set as 0.6 and 0.4; influence weight: the copper foil area has a greater impact on the bonding force of copper deposition, so if the substrate has a high proportion of copper foil, its weight value can be appropriately increased (such as 0.6→0.65). Thus, by comprehensively considering the area proportion of the substrate and the prepreg on the hole wall and the influence degree of each on the bonding force of copper deposition, the first roughing weight value of each substrate and the second roughing weight value of each prepreg are determined.

[0044] S2206, multiply the roughness at each time point on the first roughing curve by the first roughing weight value to obtain a first weight roughing curve; Specifically, the first weight roughing curve is the product of the first roughing curve of a certain substrate and its first roughing weight value.

[0045] S2207, multiply the roughness at each time point on the second roughing curve by the second roughing weight value to obtain a second weight roughing curve; Specifically, the second weight roughing curve is the product of the second roughing curve of a certain prepreg and its second roughing weight value.

[0046] S2208, superimposing the first weight roughing curve and the second weight roughing curve to obtain a comprehensive roughing curve; Specifically, all the first weight roughing curves and the second weight roughing curves are superimposed at the same time point; the overall roughness of the hole wall with respect to time is comprehensively reflected, the etching difference of different materials is balanced, and the roughness deficiency or excess caused by single consideration is avoided.

[0047] S2209, determining a first roughing time according to the first roughness and the comprehensive roughing curve; Specifically, on the comprehensive roughing curve, the time point corresponding to the roughness equal to the first roughness is found, that is, the first roughing time is obtained.

[0048] S2210, roughing the first via by a roughing liquid to obtain the second via within the first roughing time.

[0049] Specifically, the first circuit board containing the first via is immersed in the roughing liquid, and kept at a preset temperature (such as 75℃) for a first roughing time (such as 8min); the hole wall roughness is monitored in real time by online monitoring (such as a laser roughness sensor), and the time is dynamically adjusted, so as to obtain the second via with a comprehensive roughness equal to the first roughness.

[0050] S300, resin plug hole is performed on the target via 110 to obtain a second circuit board, and the target via 110 on the second circuit board has a first groove 120 after resin cooling.

[0051] Specifically, referring to Figure 2 Before resin plug hole is performed on the target via 110, the target via 110 is pretreated to remove impurities (copper scraps, roughing liquid residues, etc.) in the target via 110. After pretreatment, a resin material matched with the requirements of the substrate material and the circuit design is selected; the resin is injected into the target via 110 and then solidified, and during the resin cooling process, the first groove 120 is formed at the top of the target via 110 due to the combined action of volume shrinkage and hole wall constraint, and finally the second circuit board is obtained.

[0052] S400, uniform copper plating is performed on the target surface 100 having the target via 110 on the second circuit board to obtain a third circuit board, the target surface 100 on the third circuit board is covered with a hole-filling copper layer 130, the hole-filling copper layer 130 has a second groove 131 on the target via 110, and the second groove 131 covers the first groove 120.

[0053] Specifically, the first groove 120 of the target via 110 and the target surface 100 are pretreated, so that the first groove 120 and the target surface 100 can better deposit a copper layer; after the pretreatment, a layer of copper layer is uniformly deposited on the first groove 120 and the target surface 100, thereby providing a conductive basis for electroplating copper and ensuring that the hole-filling copper layer 130 can be uniformly increased from the bottom of the first groove 120 upwards. Taking the copper deposition layer as a conductive substrate, the copper layer is thickened and filled in the first groove 120 by acidic electroplating copper, and the electroplating parameters are controlled to ensure that the second groove 131 covering the first groove 120 is formed (that is, the bottom of the second groove 131 is higher than the end of the first groove 120).

[0054] In some optional embodiments, after the target surface 100 with the target via 110 on the second circuit board is uniformly electroplated with copper deposition, a third circuit board is obtained, comprising: S410, obtaining a copper deposition groove by depositing copper in the first groove 120; Specifically, the bottom of the first groove 120 (formed after the resin plug hole is cooled) is insulating resin, and the sidewall is insulating resin or copper layer without resin covering. A conductive layer needs to be formed by chemical copper deposition to convert the insulating groove into a conductive copper deposition groove. The copper deposition layer completely covers the inner wall of the first groove 120 to form a conductive copper deposition groove. At this time, the groove depth (first depth) is slightly reduced due to the thickness of the copper deposition layer.

[0055] S420, obtaining the first depth and the groove curvature of the copper deposition groove; Specifically, a laser confocal microscope or a step meter is used to measure the depth of multiple points uniformly on the central axis of the copper deposition groove, and the average value is taken as the first depth. A scanning electron microscope (SEM) is used to take a cross-sectional image of the copper deposition groove, and an image analysis software is used to fit the inner wall curve of the groove to calculate the groove curvature, so as to ensure that the curvature data can reflect the bending and flatness of the groove.

[0056] S430, determining the first copper layer thickness of the hole-filling copper layer 130 according to the first depth and the groove curvature; Specifically, the minimum filling thickness is determined based on the first depth to ensure that the copper layer at the bottom of the groove has sufficient thickness to satisfy that the bottom of the second groove 131 is above the top of the first groove 120, so as to completely cover the first groove 120 and make the first groove 120 completely filled and flattened.

[0057] S440, placing the target surface 100 of the second circuit board in an electroplating tank, and determining the electroplating time according to an electroplating curve and the first copper layer thickness, wherein the electroplating curve represents a relationship curve between the thickness of the copper layer electroplated in the electroplating tank and the time; Specifically, the first copper layer thickness is converted into a specific plating time through a copper layer thickness-time relationship curve (plating curve) of the plating bath, so as to ensure the accurate control of the copper layer thickness. The plating curve is calibrated through experiments. Under the same parameters as production, the copper layer thickness at different time points is recorded, and a thickness-time relationship curve is drawn, that is, the plating curve is obtained. According to the first copper layer thickness and the copper deposition layer thickness, the required copper plating layer thickness is calculated; and according to the slope of the plating curve, the plating time is calculated.

[0058] S450, after the target surface 100 is plated for the plating time, the third circuit board is obtained.

[0059] Specifically, the target surface 100 of the second circuit board is placed downward into the plating bath, the copper deposition layer is used as a conductive base, a high-filling acidic copper plating solution is used, and the plating is continuously carried out at a preset current density and temperature until a set time. The plating solution is uniformly distributed through the movement of the cathode during the plating process. The plating forms a second groove 131 with a slightly higher edge and a gentle bottom, which accurately covers the original first groove 120 area and is coaxial with the copper deposition groove. After the plating is completed, cleaning, passivation and drying treatment are performed, and the third circuit board is obtained.

[0060] S500, after the hole-filling copper layer 130 is polished and polished, a fourth circuit board with a target copper layer 140 is obtained, and the flatness of the target copper layer 140 is greater than or equal to a preset flatness.

[0061] Specifically, the preset flatness is the flatness that meets the chip mounting, which is specifically determined according to actual needs and is not limited here. According to the actual state of the hole-filling copper layer 130 of the third circuit board, the total polishing amount is determined. The polishing is specifically divided into coarse grinding and fine grinding; the coarse grinding removes most of the redundant materials on the surface of the hole-filling copper layer 130, eliminates the second groove 131, and makes the target surface 100 preliminarily flat; the fine grinding further trims the surface on the basis of the coarse grinding to reduce scratches caused by the coarse grinding. The polishing further improves the surface flatness through the mechanical action and chemical action of extremely fine abrasives, so that the target copper layer 140 reaches the preset flatness. After the hole-filling copper layer 130 is polished, the hole-filling copper layer 130 is converted into the target copper layer 140 that meets the preset flatness, so that the fourth circuit board can meet the stringent requirements of subsequent component mounting (such as precise welding of projector driving IC) on the surface flatness.

[0062] In some optional embodiments, the fourth circuit board with the target copper layer 140 obtained after the hole-filling copper layer 130 is polished and polished includes: S510, after the hole-filling copper layer 130 is polished, a first polished copper layer is obtained, and the first polished copper layer is at the same horizontal position as the bottom of the second groove 131. Specifically, the ceramic polishing is to remove the redundant part of the filling hole copper layer 130 by high-hardness ceramic abrasive, accurately eliminate the second groove 131, and make the copper layer surface flush with the bottom of the groove. The polishing selects a 600-800 mesh ceramic grinding wheel installed on a numerical control grinding machine; a preset polishing pressure is set (to ensure that the abrasive can effectively cut the copper layer, for example, the polishing pressure is set to 0.04-0.06 MPa), deionized water is used for continuous cooling to prevent the copper layer from being oxidized and discolored due to frictional heating. The surface height of the filling hole copper layer 130 is monitored in real time by an online laser displacement sensor, and the bottom height of the second groove 131 is taken as the reference (a preset target horizontal line). When the surface copper layer is polished to be flush with the reference line, the second groove 131 disappears completely, and the filling hole copper layer 130 is converted into a first polished copper layer.

[0063] S520, polishing the first polished copper layer by non-woven fabric to obtain a second polished copper layer; Specifically, the non-woven fabric polishing removes the rough scratches left by the ceramic polishing by using flexible abrasive, and refines the surface roughness. The polishing uses a non-woven fabric wheel containing silicon carbide abrasive (particle size 1200-1500 mesh, abrasive content 30%-40%), which has the flexibility to adapt to the small undulations on the surface of the copper layer. The polishing pressure is reduced to 0.02-0.03 MPa (to avoid rigid impact that causes surface deformation), and a special polishing liquid (containing lubricant and corrosion inhibitor) is used to reduce abrasive blockage and copper layer oxidation. The three-dimensional network structure of the non-woven fabric can remove the material on the surface of the first polished copper layer (mainly the protruding part of the ceramic scratches) through micro-cutting and friction grinding, and can also gently transition the fine depressions, thereby reducing the surface roughness.

[0064] S530, polishing the second polished copper layer to obtain the target copper layer 140.

[0065] Specifically, the fine polishing further eliminates surface micro-defects, so that the copper layer reaches the preset flatness, and forms the final target copper layer 140. The polishing selects a wool polishing wheel combined with a cerium oxide polishing paste (only for example, not limited specifically), and the polishing pressure is controlled at 0.01-0.02 MPa (to avoid introducing new deformation). The micro-cutting effect of the cerium oxide abrasive removes the material on the surface of the second polished copper layer, and the surfactant in the polishing paste can reduce the surface tension of the copper layer, promoting the smoothing of the micro-protrusions; the flexible contact of the wool wheel ensures the uniformity of the polishing, avoiding local over-polishing; when the copper layer reaches the preset flatness, the polishing is stopped, thereby obtaining the target copper layer 140.

[0066] In some optional embodiments, the ceramic polishing of the filling hole copper layer 130 to obtain a first polished copper layer comprises: S511, obtaining a second depth of the second groove 131; S512, configure the second depth as a copper layer removal depth; S513, perform the ceramic polishing on the via filling copper layer 130 according to the copper layer removal depth to obtain the first polished copper layer.

[0067] Specifically, the second depth refers to the vertical distance from the surface of the via filling copper layer 130 to the bottom of the second groove 131, which is collected by a high-precision detection device (such as a laser confocal microscope). The copper layer removal depth is configured as the second depth to ensure that the surface of the via filling copper layer 130 can be accurately lowered to the plane where the bottom of the second groove 131 is after polishing, and the groove is completely eliminated. The via filling copper layer 130 is polished according to the set copper layer removal depth, and the removal amount is ensured to be consistent with the target through accurate control of the device, and finally the first polished copper layer is formed.

[0068] In some optional embodiments, the ceramic polishing on the via filling copper layer 130 according to the copper layer removal depth to obtain the first polished copper layer comprises: S5130, control the first polishing head to press the via filling copper layer 130 with a first pressure, and then perform ceramic polishing on the via filling copper layer 130 and record the first polishing thickness per unit time, wherein the first polishing head is provided with ceramic; Specifically, when the via filling copper layer 130 is polished according to the preset copper layer removal depth, the optimal target pressure is found by gradually adjusting the polishing pressure, which can ensure the polishing efficiency while avoiding excessive damage to the copper layer, and finally the set removal depth is accurately reached to form the first polished copper layer. When the polishing starts, the first polishing head installed with ceramic abrasive is set to the first pressure (initial polishing pressure) and vertically presses the surface of the via filling copper layer 130, and the polishing device is started to polish at the preset speed. After continuously polishing for 30-60 seconds (unit time, which can be set according to requirements and is not limited here), the copper layer removal amount in this period is measured by a laser thickness gauge, and the first polishing thickness per unit time is calculated as a reference value.

[0069] S5131, control the first polishing head to increase the unit pressure to obtain a second pressure, and then press the via filling copper layer 130 with the second pressure to perform ceramic polishing and record the second polishing thickness per unit time; Specifically, the unit pressure is added to the first pressure to obtain the second pressure. The above polishing operation is repeated with the second pressure, and the second polishing thickness per unit time is also recorded and compared with the first polishing thickness.

[0070] S5132, in the case that the second polishing thickness is greater than the first polishing thickness, a third pressure is obtained by increasing the second pressure by a unit pressure, and the first polishing head is controlled to polish the via-filling copper layer 130 at the third pressure, and a third polishing thickness per unit time is recorded; in the case that the third polishing thickness is greater than the second polishing thickness, the third pressure is configured as the target pressure; in the case that the third polishing thickness is less than or equal to the second polishing thickness, the second pressure is configured as the target pressure; S5133, in the case that the second polishing thickness is less than or equal to the first polishing thickness, a fourth pressure is obtained by decreasing the first pressure by a unit pressure, and the first polishing head is controlled to polish the via-filling copper layer 130 at the fourth pressure, and a fourth polishing thickness per unit time is recorded; in the case that the fourth polishing thickness is less than the first polishing thickness, the first pressure is configured as the target pressure; in the case that the fourth polishing thickness is greater than or equal to the first polishing thickness, the fourth pressure is configured as the target pressure; Specifically, according to the comparison result of the second polishing thickness and the first polishing thickness, the pressure is optimized in two paths: Path 1: the case that the second polishing thickness is greater than the first polishing thickness (the efficiency is improved by increasing the pressure). Continue to increase the unit pressure to the third pressure, test and record the third polishing thickness in the same way. If the third polishing thickness is greater than the second polishing thickness (the efficiency is still improved by increasing the pressure), the third pressure is determined as the target pressure. If the third polishing thickness is less than or equal to the second polishing thickness (the efficiency cannot be improved by increasing the pressure, and even may be decreased due to excessive wear of the abrasive), the second pressure is determined as the target pressure.

[0071] Path 2: the case that the second polishing thickness is less than or equal to the first polishing thickness (the efficiency is not improved by increasing the pressure). Decrease the unit pressure to the fourth pressure, test and record the fourth polishing thickness; if the fourth polishing thickness is less than the first polishing thickness (the efficiency is decreased by decreasing the pressure), the first pressure is determined as the target pressure; if the fourth polishing thickness is greater than or equal to the first polishing thickness (the efficiency is higher at a lower pressure, which may be due to more uniform contact between the abrasive and the copper layer), the fourth pressure is determined as the target pressure.

[0072] S5134, the first polishing head is controlled to polish the via-filling copper layer 130 at the target pressure, and the first polished copper layer is obtained after polishing stops in the case that the polishing depth is equal to the copper layer removal depth.

[0073] Specifically, the first polishing head pressure is fixed as the target pressure, and the hole filling copper layer 130 is continuously polished, and the total polishing depth is monitored in real time through the laser displacement sensor. When the real-time polishing depth reaches the preset copper layer removal depth, the equipment automatically stops polishing. At this time, the copper layer surface is at the same horizontal position as the bottom of the second groove 131, and the ceramic grinding marks are evenly distributed, without local over-grinding or under-grinding phenomenon caused by improper pressure, meeting the process requirements of subsequent non-woven fabric polishing.

[0074] In some optional embodiments, the first copper layer is polished by a second polishing head provided with non-woven fabric; and the second polished copper layer obtained after the first polished copper layer is polished by the second polishing head, comprises: S521, obtaining historical polishing information of the second polishing head, the historical polishing information representing historical polishing times, historical polishing time and historical polishing pressure of the second polishing head; Specifically, the historical polishing information is data reflecting the wear state of the second polishing head, and is extracted from the equipment control system. The information content includes the historical polishing times (cumulative use times, such as 100-500 times) of the second polishing head, the historical polishing time (single batch polishing time, unit: minute) of each polishing, and the historical polishing pressure (pressure value acting on the copper layer, unit: MPa) of each polishing. The historical data is sorted in time sequence, and the cumulative total polishing time (sum of each polishing time) and the average polishing pressure are calculated to form a basic data set. For example: cumulative polishing 300 times, total time 1500 minutes, average pressure 0.025 MPa.

[0075] S522, determining the damage coefficient of the second polishing head according to the historical polishing times, historical polishing time and historical polishing pressure; Specifically, the first damage value corresponding to the historical polishing times is calculated according to the weight value corresponding to the historical polishing times; similarly, the second damage value corresponding to the historical polishing times is calculated according to the weight value corresponding to the historical polishing times, and the third damage value corresponding to the historical polishing pressure is calculated according to the weight value corresponding to the historical polishing pressure; the first damage value, the second damage value and the third damage value are superimposed on each other to obtain the specific damage coefficient. Through the specific damage coefficient corresponding table, the damage degree of the second polishing head, as well as the remaining working time under the damage degree, the polishing pressure and the polishing time required for polishing the same thickness or the same flatness of the copper layer can be determined.

[0076] S523, obtaining the second flatness of the second polished copper layer and the first flatness of the first polished copper layer; Specifically, the surface flatness of the first polished copper layer is detected by a laser flatness tester (first flatness). The second flatness is set according to process requirements, that is, the flatness that the second polished copper layer needs to reach. The flatness difference is the difference between the first flatness and the second flatness, which represents the amount of surface undulation that needs to be eliminated by non-woven cloth polishing.

[0077] S524, determining a target polishing time and a target polishing pressure of the second polishing head according to the flatness difference between the second flatness and the first flatness and the damage coefficient; Specifically, the target polishing pressure corresponding to different polishing damage coefficients is determined according to the polishing table corresponding to the damage coefficient (to ensure that the second polishing head works normally; if the polishing pressure is too small, the polishing effect is poor, and if the polishing pressure is too large, the damage of the second polishing head is accelerated). The target polishing efficiency of the second polishing head, that is, the time required for polishing a unit flatness, can be determined according to the target polishing pressure and the damage coefficient. The target polishing time required can be calculated according to the target polishing efficiency and the flatness difference.

[0078] S525, controlling the second polishing head to polish the first copper layer with non-woven cloth for a target polishing time at a target polishing pressure to obtain the second polished copper layer.

[0079] Specifically, after the target polishing time and the target polishing pressure are determined, the second polishing head is controlled to polish the first copper layer with non-woven cloth for a corresponding target polishing time at a target polishing pressure; that is, the polishing pressure of the second polishing head is adjusted to the target polishing pressure, the second polishing head (non-woven cloth polishing head) is started to polish the first polished copper layer, and the polishing time is controlled to the target polishing time; a special polishing liquid is used for continuous cooling during polishing.

[0080] S600, performing a circuit forming process on the fourth circuit board to obtain a target circuit board.

[0081] Specifically, the fourth circuit board with the target copper layer 140 (flatness up to standard) is subjected to a circuit forming process. Through multiple processes, the pre-set circuit pattern is accurately copied to the surface of the copper layer, redundant copper material is removed, and a circuit with a specific electrical function is formed, finally obtaining a target circuit board that can realize signal transmission and component connection.

[0082] In some optional embodiments, the fourth circuit board is subjected to a circuit forming process to obtain a target circuit board, which comprises: S610, performing an outer layer circuit manufacturing process on the fourth circuit board to obtain a fifth circuit board; Specifically, the outer layer circuit manufacturing process is to form a pre-set circuit pattern on the surface of the target copper layer 140 through pattern transfer and etching, to ensure the accuracy and integrity of the circuit. The line width of the outer layer circuit is 170-180 , line distance is 102-112 .

[0083] S620, the outer side of the fifth circuit board line is sequentially detected, impedance test and solder resist after getting the sixth circuit board; Specifically, the line detection includes appearance detection and conduction detection. The appearance detection adopts AOI (automatic optical detection) equipment to scan the surface of the line, and identifies defects such as disconnection, short circuit, pinhole and the like; the conduction test uses a flying probe tester to detect the conduction resistance of the key line, to ensure that the electrical connection between the target via hole 110 and the line is reliable. The impedance test measures the characteristic impedance of the high-speed signal line through an impedance tester.

[0084] The solder resist adopts screen printing or spraying method to uniformly coat green solder resist ink on the surface of the fifth circuit board, covering the non-welding area; the solder resist layer is cured by ultraviolet light, exposing the solder pad and test point; and the corresponding solder resist detection is carried out.

[0085] S630, the sixth circuit board is cut into the target circuit board after plating gold.

[0086] Specifically, before plating gold, corresponding characters are printed on the sixth circuit board. Before plating gold, the oxidation layer on the surface of the solder pad is removed with micro-etching liquid, and the adhesion of the gold plating layer is enhanced by activation treatment. The gold layer is deposited in the gold plating tank to ensure that the solder pad surface is uniformly covered without plating leakage and pinholes; after plating gold, the residual liquid is washed with deionized water, dried, and the oxidation resistance and welding reliability of the solder pad are improved.

[0087] Cutting forming is to cut the circuit board according to the design size with a numerical control laser cutting machine or a milling machine to remove the excess substrate; an 800-1200 mesh grinding wheel is used to polish the edge to remove burrs and avoid scratching the elements during assembly; after cutting, the overall flatness, line conduction and solder resist integrity are detected, and all indicators meet the requirements to be the target circuit board.

[0088] The implementation of the embodiment of the present application includes the following beneficial effects: the embodiment of the present application provides a circuit board production method, which comprises: obtaining a first circuit board by laminating at least two substrates and at least one prepreg; obtaining at least one target via hole 110 by performing a copper plating drilling process on the first circuit board; obtaining a second circuit board by performing a resin hole plugging process on the target via hole 110, wherein the target via hole 110 on the second circuit board has a first groove 120 after resin cooling; obtaining a third circuit board by performing a uniform copper electroplating process on a target surface 100 of the second circuit board having the target via hole 110, wherein the target surface 100 on the third circuit board is covered with a hole-filling copper layer 130, the hole-filling copper layer 130 has a second groove 131 on the target via hole 110, and the second groove 131 covers the first groove 120; obtaining a fourth circuit board having a target copper layer 140 by performing a polishing process on the hole-filling copper layer 130, wherein the flatness of the target copper layer 140 is greater than or equal to a preset flatness; and obtaining a target circuit board by performing a circuit forming process on the fourth circuit board. By performing copper electroplating on the target via hole 110 after resin hole plugging, the hole-filling copper layer 130 is obtained to fill the first groove 120 generated after resin cooling, and the target copper layer 140 is obtained by polishing the hole-filling copper layer 130, and the first groove 120 is covered by the target copper layer 140, which can improve the flatness of the circuit board surface and ensure the welding quality of the chip. Moreover, the hole-filling copper layer is polished to avoid damage to the substrate and thinning of the copper layer caused by polishing the copper layer on the first substrate or the second substrate.

[0089] In a second aspect, the embodiment of the present application further provides a circuit board, which is made by the above-mentioned circuit board production method.

[0090] It can be seen that the contents in the above-mentioned method embodiments are all applicable to the present circuit board embodiment, the present circuit board embodiment specifically realizes the same functions as the above-mentioned method embodiments, and achieves the same beneficial effects as the above-mentioned method embodiments.

[0091] In another aspect, the embodiments of the present application further provide an electronic device, comprising: a memory, configured to store program instructions; and a processor, configured to invoke the program instructions stored in the memory, and perform the circuit board production method according to the obtained program instructions. The processor can be implemented in a general-purpose central processing unit (CPU), a microprocessor, an application specific integrated circuit (ASIC), or one or more integrated circuits, and is configured to execute related programs to implement the technical solutions provided by the embodiments of the present application; and the memory can be implemented in a read only memory (ROM), a static storage device, a dynamic storage device, or a random access memory (RAM). The memory can store an operating system and other application programs, and when the technical solutions provided by the embodiments of the present application are implemented by software or firmware, the related program codes are stored in the memory and executed by the processor to perform the circuit board production method according to the embodiments of the present application; and the memory and the processor can be connected through a bus or the like.

[0092] In another aspect, the embodiments of the present application further provide a storage medium, which is a computer readable storage medium, and stores a computer program. The computer program is executed by a processor to implement the circuit board production method. The memory is a non-transitory computer readable storage medium, and can be used to store non-transitory software programs and non-transitory computer executable programs. In addition, the memory can include a high-speed random access memory, and can also include a non-transitory memory, such as at least one magnetic disk storage device, a flash memory device, or other non-transitory solid-state memory device. In some embodiments, the memory includes a memory remotely arranged relative to the processor, and the remote memory can be connected to the processor through a network. Examples of the network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and a combination thereof. The device embodiments described above are only schematic, and the units described as separate components can or can not be physically separated, and can be implemented in one place or distributed on multiple network units. Part or all of the modules can be selected according to actual needs to achieve the purpose of the embodiments.

[0093] In some alternative embodiments, the functions / operations described in the block diagrams can not occur in the order described in the operational illustrations. For example, two blocks shown in succession can in fact be executed substantially concurrently or the blocks can sometimes be executed in the reverse order, depending upon the functionality / operations involved. Also, although the embodiments presented in the flow diagrams are shown as a sequence of operations, it is to be understood that the logical flow is merely illustrative of alternative embodiments, and the order of the operations can be changed, and various operations can be performed in parallel, depending on the implementation. Embodiments of the application are not limited to the operational flow presented in the figures.

[0094] Further, although the present application has been described in the context of functional modules, it is to be understood that one or more of the functions and / or features can be integrated in a single physical device and / or software module, or one or more functions and / or features can be implemented in separate physical devices or software modules. It is also to be understood that detailed discussion of the actual implementation of each module is unnecessary to an understanding of the present application. Rather, the actual implementation is within the routine skill of engineers familiar with the property, function and internal relationships of the various functional modules disclosed herein. Accordingly, the present application is not limited to the embodiments illustrated in the figures. Rather, one of ordinary skill in the art having the benefit of this disclosure will be able to make modifications and variations in light of the concepts disclosed without departing from the scope of the application as set forth in the claims. It is also to be understood that the specific concepts disclosed are illustrative in nature and not intended to limit the scope of the application which is to be determined by the appended claims and their equivalents.

[0095] In the above description of the present specification, reference has been made to descriptive terms such as "one embodiment," "another embodiment," or "some embodiments," etc. It is understood that such descriptive terms are not intended to limit the scope of the application to the described embodiments. Rather, such terms are used to connect a feature described before with a feature described after. It is further understood that the scope of the application is not limited to the features of any or all embodiments.

[0096] While the embodiments of the present application have been shown and described, it is to be understood that the scope of the present application is not to be limited to what has been particularly shown and described, and what has been described and directed is understood merely to be illustrative of the present application and not in a limiting sense. The above describes the preferred embodiments of the present application, but the present application is not limited to the embodiments, and those skilled in the art can make various equivalent modifications or replacements without departing from the spirit of the present application, and these equivalent modifications or replacements are all included in the scope defined by the claims of the present application.

Claims

1. A method of producing a circuit board, characterized by, The method comprises the following steps: pressing at least two substrates and at least one prepreg to obtain a first circuit board; drilling and copper plating the first circuit board to obtain at least one target via hole; resin plugging the target via hole to obtain a second circuit board, wherein the target via hole on the second circuit board has a first groove after resin cooling; uniform copper plating on a target surface of the second circuit board with the target via hole to obtain a third circuit board, wherein the target surface on the third circuit board is covered with a hole-filling copper layer, the hole-filling copper layer has a second groove on the target via hole, and the second groove covers the first groove; polishing the hole-filling copper layer to obtain a fourth circuit board with a target copper layer, wherein the flatness of the target copper layer is greater than or equal to a preset flatness; circuit forming on the fourth circuit board to obtain a target circuit board.

2. The method of claim 1, wherein, The method comprises the following steps: drilling and copper plating the first circuit board to obtain at least one target via hole; drilling the first circuit board to obtain at least one first via hole; first roughening the first via hole to obtain a second via hole, wherein the second via hole has a first roughness; copper plating the second via hole to obtain a third via hole; 3. The method of claim 2, wherein, second roughening the third via hole to obtain the target via hole, wherein the inner wall of the target via hole has a second roughness, and the second roughness is greater than the first roughness. The method comprises the following steps: obtaining substrate information and prepreg information, wherein the substrate information represents the material information of each substrate, and the prepreg information represents the material information of each prepreg; obtaining roughening liquid information, wherein the roughening liquid information represents the concentration information, composition information and temperature information of the roughening liquid; generating a first roughening curve of each substrate according to the roughening liquid information and the substrate information, wherein the first roughening curve represents the relationship between the substrate roughness and time; generating a second roughening curve of each prepreg according to the roughening liquid information and the prepreg information, wherein the second roughening curve represents the relationship between the prepreg and time; obtaining a first roughening weight value of each substrate and a second roughening weight value of each prepreg; multiplying the roughness at each time point on the first roughening curve by the first roughening weight value to obtain a first weight roughening curve; multiplying the roughness at each time point on the second roughening curve by the second roughening weight value to obtain a second weight roughening curve; superimposing the first weight roughening curve and the second weight roughening curve to obtain a comprehensive roughening curve; determining a first roughening time according to the first roughness and the comprehensive roughening curve; 4. The method of claim 1, wherein, roughening the first via hole by the roughening liquid within the first roughening time to obtain the second via hole. The method comprises the following steps: copper plating the first groove to obtain a copper-plated groove; obtaining the first depth and groove curvature of the copper-plated groove; determine a first copper layer thickness of the filling hole copper layer according to the first depth and the groove curvature; place the target surface of the second circuit board in an electroplating tank, and determine an electroplating time according to an electroplating curve and the first copper layer thickness, the electroplating curve representing a relationship curve between an electroplated copper layer thickness of the electroplating tank and time; obtain the third circuit board after electroplating the target surface for the electroplating time.

5. The method of claim 1, wherein, obtain a fourth circuit board with a target copper layer after polishing the filling hole copper layer, comprising: obtain a first polished copper layer after ceramic polishing the filling hole copper layer, the first polished copper layer being at the same horizontal position as the bottom of the second groove; obtain a second polished copper layer after non-woven fabric polishing the first polished copper layer; obtain the target copper layer after polishing the second polished copper layer.

6. The method of claim 5, wherein, obtain a first polished copper layer after ceramic polishing the filling hole copper layer, comprising: obtain a second depth of the second groove; configure the second depth as a copper layer removal depth; obtain the first polished copper layer after ceramic polishing the filling hole copper layer according to the copper layer removal depth.

7. The method of claim 6, wherein, obtain the first polished copper layer after ceramic polishing the filling hole copper layer according to the copper layer removal depth, comprising: control a first polishing head to press the filling hole copper layer with a first pressure, and record a first polishing thickness per unit time after ceramic polishing the filling hole copper layer, the first polishing head being provided with ceramic; control the first polishing head to increase a unit pressure to obtain a second pressure, and record a second polishing thickness per unit time after ceramic polishing the filling hole copper layer with the second pressure; in a case where the second polishing thickness is greater than the first polishing thickness, control the first polishing head to increase the unit pressure to obtain a third pressure, and record a third polishing thickness per unit time after ceramic polishing the filling hole copper layer with the third pressure; in a case where the third polishing thickness is greater than the second polishing thickness, configure the third pressure as a target pressure; in a case where the third polishing thickness is less than or equal to the second polishing thickness, configure the second pressure as the target pressure; in a case where the second polishing thickness is less than or equal to the first polishing thickness, control the first polishing head to subtract the unit pressure from the first pressure to obtain a fourth pressure, and record a fourth polishing thickness per unit time after ceramic polishing the filling hole copper layer with the fourth pressure; in a case where the fourth polishing thickness is less than the first polishing thickness, configure the first pressure as the target pressure; in a case where the fourth polishing thickness is greater than or equal to the first polishing thickness, configure the fourth pressure as the target pressure; control the first polishing head to ceramic polish the filling hole copper layer with the target pressure, and stop polishing in a case where a polishing depth is equal to the copper layer removal depth to obtain the first polished copper layer.

8. The method of claim 6, wherein, The first copper layer is polished by a second polishing head provided with non-woven fabric; the second polishing head is used to polish the first polished copper layer to obtain a second polished copper layer, comprising: obtaining historical polishing information of the second polishing head, wherein the historical polishing information represents historical polishing times, historical polishing time and historical polishing pressure of the second polishing head; determining a damage coefficient of the second polishing head according to the historical polishing times, the historical polishing time and the historical polishing pressure; obtaining a second flatness of the second polished copper layer and a first flatness of the first polished copper layer; determining a target polishing time and a target polishing pressure of the second polishing head according to a flatness difference between the second flatness and the first flatness and the damage coefficient; controlling the second polishing head to polish the first copper layer by non-woven fabric at the target polishing pressure for the target polishing time to obtain the second polished copper layer.

9. The method of claim 1, wherein, The fourth circuit board is processed by line forming to obtain a target circuit board, comprising: a fifth circuit board is obtained by manufacturing outer line of the fourth circuit board; a sixth circuit board is obtained by sequentially performing line detection, impedance test and solder resist on the outer line of the fifth circuit board; the sixth circuit board is gold filled and cut to form the target circuit board.

10. A circuit board, characterized by, The circuit board is manufactured by the circuit board production method of any one of claims 1-9.

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