Magnetoresistive random access memory and magnetoresistive random access memory system

Abstract

The invention discloses a magnetoresistive random access memory and a magnetoresistive random access memory system, which are applied to the field of information storage, and the memory comprises a plurality of magnetic tunnel junction bits, a write-in driver, a first wire connected with one end of each magnetic tunnel junction bit, and a second wire connected with the other end of each magnetic tunnel junction bit, a first conductive electrode of the write-in driver is connected with the first end of the first wire, a second conductive electrode of the write-in driver is connected with the second end of the second wire, and the deviation value of the wire length between a plurality of loops formed by the first conductive electrode and the second conductive electrode through each magnetic tunnel junction bit is smaller than a preset deviation value. According to the invention, the deviation value of the routing length between a plurality of loops formed by the first conductive electrode through each magnetic tunnel junction bit and the second conductive electrode is smaller than the preset deviation value, so that the problem of over-high near-end writing voltage is avoided, the service life of the device is prolonged, and the reading efficiency of the memory is improved at the same time.

Description

Technical Field

[0001] This invention relates to the field of information storage, and in particular to a magnetoresistive random access memory and a magnetoresistive random access memory system. Background Technology

[0002] The main building block of MRAM (Magnetic Resistive Random Access Memory) is the MTJ (Magnetic Tunnel Junction), which consists of a magnetic free layer, a tunnel barrier insulating layer, and a fixed magnetic layer. Data storage is achieved by changing the magnetic direction of the magnetic free layer in the MTJ, thereby changing the resistance. Each trace in an MRAM array connects multiple MTJ bits, and each bit connected by the same trace is powered by the same write driver. However, because the distance between the MTJ and the write driver trace varies at different locations, the voltage across the MTJ differs. To ensure correct writing to the entire address range of the chip array, the write voltage of the far-end MTJ bits must meet the minimum write voltage requirement, resulting in excessively high write voltages for the near-end MTJ bits, which severely impacts the overall lifespan of the chip.

[0003] Therefore, how to provide an MRAM that ensures the normal write voltage of each MTJ bit while avoiding the impact of excessive voltage on the chip lifespan of the MTJ bit near the write driver is a technical problem that urgently needs to be solved by those skilled in the art. Summary of the Invention

[0004] In view of this, the purpose of the present invention is to provide a magnetoresistive random access memory and a magnetoresistive random access memory system, which solves the problem in the prior art that in order to ensure that the write voltage of the far-end magnetic tunnel junction bit meets the minimum write voltage requirement, the write voltage of the near-end magnetic tunnel junction bit is too high, which seriously affects the chip's working life.

[0005] To solve the above-mentioned technical problems, the present invention provides a magnetoresistive random access memory, comprising:

[0006] Multiple magnetic tunnel junction bits, a write driver, a first trace connected to one end of the magnetic tunnel junction bits, and a second trace connected to the other end of the magnetic tunnel junction bits;

[0007] The first conductive electrode of the write driver is connected to the first end of the first trace, and the second conductive electrode of the write driver is connected to the second end of the second trace;

[0008] The first end and the second end are arranged opposite each other along the arrangement direction of the plurality of magnetic tunnel junction bits, so that the first conductive electrode forms a plurality of loops with the second conductive electrode through each of the magnetic tunnel junction bits, and the deviation value of the trace length between the plurality of loops is less than a preset deviation value.

[0009] Optionally, the trace resistance between the first conductive electrode and the multiple loops formed by the second conductive electrode through each of the magnetic tunnel junction bits is the same.

[0010] Optionally, the first trace and the second trace are traces of the same material.

[0011] Optionally, both the first trace and the second trace are copper metal wires.

[0012] Optionally, the plurality of magnetic tunnel junction bits are arranged in a straight line;

[0013] Correspondingly, the magnetic tunnel junction bits at the first and second ends are arranged diagonally along multiple straight lines.

[0014] Optionally, the deviation between the bus resistance of the first trace and the bus resistance of the second trace is less than a preset line resistance deviation value.

[0015] Optionally, the bus resistance of the first trace is the same as that of the second trace.

[0016] Optionally, both the first and second traces have the same resistance everywhere.

[0017] Optionally, the resistance value of each of the magnetic tunnel junction bits is the same.

[0018] The present invention also provides a magnetoresistive random access memory system, including a plurality of magnetoresistive random access memories as described above.

[0019] As can be seen, the magnetoresistive random access memory (MRRAM) provided by this invention includes multiple magnetic tunnel junction bits, a write driver, a first trace connected to one end of the magnetic tunnel junction bits, and a second trace connected to the other end of the magnetic tunnel junction bits. A first conductive electrode of the write driver is connected to a first end of the first trace, and a second conductive electrode of the write driver is connected to a second end of the second trace. The first and second ends are arranged opposite each other along the arrangement direction of the multiple magnetic tunnel junction bits, so that the first conductive electrode forms multiple loops with the second conductive electrode through each magnetic tunnel junction bit. The deviation in trace length between the multiple loops is less than a preset deviation value. By setting the first and second conductive electrodes opposite each other along the arrangement direction of the multiple magnetic tunnel junction bits, this invention ensures that the deviation in trace length between the first conductive electrode and the second conductive electrode forming multiple loops through each magnetic tunnel junction bit is less than a preset deviation value. This avoids the problem of excessively high near-end write voltage caused by ensuring write voltage at the far-end magnetic tunnel junction bit in the prior art, thus improving device lifespan and read efficiency of the MRAM.

[0020] In addition, the present invention also provides a magnetoresistive random access memory system, which also has the above-mentioned beneficial effects. Attached Figure Description

[0021] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0022] Figure 1 This is a schematic diagram of the structure of a magnetoresistive random access memory in the prior art;

[0023] Figure 2 This is a schematic diagram of the structure of a magnetoresistive random access memory provided in an embodiment of the present invention;

[0024] Figure 3 This is a schematic diagram of the structure of a magnetoresistive random access memory system provided in an embodiment of the present invention;

[0025] Figures 1 to 3 The reference numerals in the attached figures are explained as follows:

[0026] 10-Magnetic tunnel junction bits;

[0027] 20 - Write driver, 21 - First conductive electrode, 22 - Second conductive electrode;

[0028] 30 - First routing;

[0029] 40 - Second route;

[0030] The gate terminal of a 50-MOSFET. Detailed Implementation

[0031] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0032] The main building block of spin-transfer torque magnetoresistive random access memory (STT MRAM) is the magnetic tunnel junction (MTJ), which consists of a magnetic free layer, a tunnel barrier insulating layer, and a fixed magnetic layer. Data storage is achieved by changing the magnetic direction of the free layer in the magnetic tunnel junction (MTJ). As a non-volatile memory, MRAM has the advantages of low power consumption, high speed, and high write endurance.

[0033] In an MRAM array, multiple MTJ bits are arranged in a row, with one side connected to trace BL and the other side connected to trace SL. Each trace BL connects N MTJ bits, where N is typically between 128 and 1024 or even larger, depending on the capacity. Each MTJ bit is powered uniformly through a write driver. The distance between the MTJs at different locations and the metal traces to the write driver varies (e.g., ...). Figure 1 As shown, Figure 1 This is a schematic diagram of a prior art magnetoresistive random access memory (MRRAM). The parasitic resistance values ​​caused by traces SL and BL of different lengths will result in different voltage divisions on both sides of the MTJ bit at different locations. Taking N=1024 bits as an example, bits physically located at different distances from the write driver in the array will have an expected MTJ voltage difference of 60 to 80 millivolts due to the difference in line resistance of the traces SL and BL passing through that MTJ bit. Therefore, to ensure correct writing to the entire address of the chip array, the write voltage of the far-end MTJ bit must meet the minimum write voltage requirement. This leads to excessively high write voltages for the near-end MTJ bits, severely affecting the chip's lifespan. Actual measurements show that a voltage difference of 60 to 80 millivolts between MTJ bits will reduce the chip's endurance (the number of times the memory can be written to and erased) by 2 to 3 orders of magnitude.

[0034] This invention arranges the first and second conductive electrodes opposite each other along the arrangement direction of multiple magnetic tunnel junction bits. This ensures that the deviation in trace length between the first conductive electrode and the second conductive electrode forming multiple loops through each magnetic tunnel junction bit is less than a preset deviation value. This avoids the problem of excessively high near-end write voltage caused by prior art efforts to ensure write voltage at the far-end magnetic tunnel junction bit, thus improving device lifespan and read efficiency of the magnetoresistive random access memory. Please refer to the following embodiments for details.

[0035] Example 1:

[0036] Please refer to Figure 2 , Figure 2 A schematic diagram of a magnetoresistive random access memory (MRM) provided in an embodiment of the present invention. The MRM may include:

[0037] Multiple magnetic tunnel junction bits 10, a write driver, a first trace 30 connected to one end of the magnetic tunnel junction bits 10, and a second trace 40 connected to the other end of the magnetic tunnel junction bits 10.

[0038] The first conductive electrode 21 of the write driver is connected to the first end of the first trace 30, and the second conductive electrode 22 of the write driver is connected to the second end of the second trace 40.

[0039] The first end and the second end are arranged opposite each other along the arrangement direction of the multiple magnetic tunnel junction bits 10, so that the first conductive electrode 21 forms multiple loops with the second conductive electrode 22 through each magnetic tunnel junction bit 10, and the deviation value of the trace length between the multiple loops is less than the preset deviation value.

[0040] It should be noted that the arrows in the attached diagram indicate the direction of current flow. In this embodiment, the first trace 30 is connected to one end of the magnetic tunnel junction bit 10, and the second trace 40 is connected to the other end of the magnetic tunnel junction bit 10. Typically, to ensure overall circuit simplicity, the first trace 30 and the second trace 40 are placed on opposite sides of the magnetic tunnel junction bit 10, and both the first trace 30 and the second trace 40 are connected to all magnetic tunnel junction bits 10 within a designated area. Furthermore, the first conductive electrode 21 of the write driver is connected to the first end of the first trace 30, and the second electrode is connected to the second end of the second trace 40, so that the write driver can power each magnetic tunnel junction bit 10, enabling information storage and retrieval. In this embodiment, the first conductive electrode 21 and the second conductive electrode 22 of the write driver are the positive and negative terminals of the write driver, respectively. The polarity relationship of the first conductive electrode 21 and the second conductive electrode 22 can be arbitrarily set in this embodiment, as long as one is positive and the other negative. In this embodiment, the first conductive electrode 21 of the write driver is connected to the second conductive electrode 22 sequentially through the first trace 30, the magnetic tunnel junction bit 10, and the second trace 40 to form a closed loop. The first end and the second end are arranged opposite each other along the arrangement direction of the multiple magnetic tunnel junction bits 10. It should be noted that the arrangement direction of the multiple magnetic tunnel junction bits 10 is not limited to a straight line, but can be arranged in any direction that changes at any time. For example, the multiple magnetic tunnel junction bits 10 can be arranged along an arc-shaped extension direction, or they can be arranged along any other extension direction. Therefore, the first end and the second end being arranged opposite each other along the arrangement direction of the multiple magnetic tunnel junction bits 10 should be understood as the two ends of the multiple magnetic tunnel junctions arranged in any direction that can change at any time. That is, no matter how the multiple magnetic tunnel junction bits 10 are arranged, the first end and the second end are always respectively located at the start end and the end end of the arrangement of the multiple magnetic tunnel junctions, so that the deviation value of the trace length between the first conductive electrode 21 through each magnetic tunnel junction bit 10 and the multiple loops formed by the second conductive electrode 22 is less than a preset deviation value. It should be noted that the arrows in the above diagrams point to the current flow in the circuit, to facilitate understanding of the formed loop structure. The gate 50 of the MOSFET is connected in the loop, and the MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) acts as a switch, controlling the circuit's on / off state.

[0041] This embodiment does not limit the specific materials of the first trace 30 and the second trace 40, as long as they can enable the write driver to supply power to each magnetic tunnel junction bit 10. Theoretically, the lower the line resistance of the first trace 30 and the second trace 40, the better, in order to reduce current loss. Accordingly, this embodiment does not limit the specific setting value of the preset deviation value, which can be customized by the operator according to their needs.

[0042] Furthermore, in order to further improve the lifespan of the magnetoresistive random access memory, the trace resistance values ​​between the first conductive electrode 21 and the multiple loops formed by each magnetic tunnel junction bit 10 and the second conductive electrode 22 can all be set to be the same.

[0043] It should be noted that in this embodiment, the trace resistance values ​​of the multiple loops formed by the first conductive electrode 21 through the first trace 30, the magnetic tunnel junction bit 10, the second trace 40, and the second conductive electrode 22 are all the same. This avoids the problem of high voltage across the magnetic tunnel junction bit 10 in some loops due to resistance differences between different loops, thereby preventing the lifespan of the magnetoresistive random access memory from being affected. Since the loop resistance value should be kept within the minimum allowable range during the actual fabrication of the magnetoresistive random access memory, ensuring that the trace resistance values ​​of the multiple loops formed by the first conductive electrode 21 through each magnetic tunnel junction bit 10 and the second conductive electrode 22 are all the same should be understood as ensuring that the trace resistance values ​​between the multiple loops are all within the minimum allowable range, thus improving the lifespan of the memory.

[0044] Furthermore, in order to improve the fabrication efficiency of the magnetoresistive random access memory and to facilitate the control of the trace resistance values ​​of the first trace 30 and the second trace 40, the first trace 30 and the second trace 40 can be set to traces of the same material.

[0045] It should be noted that in this embodiment, the first trace 30 and the second trace 40 are set to be traces of the same material. When controlling the correspondence between the trace resistance values ​​of the first trace 30 and the second trace 40, it is only necessary to control the trace length and trace cross-sectional area of ​​the first trace 30 and the second trace 40 by controlling the manufacturing process, which reduces the manufacturing complexity of the magnetoresistive random access memory.

[0046] Furthermore, in order to reduce the manufacturing cost of the first trace 30 and the second trace 40, both the first trace 30 and the second trace 40 can be made of copper metal wires.

[0047] It should be noted that in this embodiment, both the first trace 30 and the second trace 40 are set as copper metal wires, which reduces the manufacturing cost of the traces while taking into account the trace resistance.

[0048] Furthermore, in order to ensure the regularity of the fabrication of the magnetoresistive random access memory, the above-mentioned multiple magnetic tunnel junction bits 10 can be arranged in a straight line;

[0049] Correspondingly, the first and second ends can be arranged diagonally along multiple straight lines with magnetic tunnel junction bits 10.

[0050] It should be noted that in this embodiment, the multiple magnetic tunnel junction bits 10 are arranged in a straight line, which can ensure the regularity of the memory structure and facilitate fabrication. At the same time, the first end and the second end are set diagonally, that is, when the first end is set at the upper right corner of the entire magnetic tunnel junction bits 10 arranged in a straight line, the corresponding second end is set at the lower left corner of the entire magnetic tunnel junction bits 10 arranged in a straight line. This ensures that the deviation value of the trace length between the first conductive electrode 21 and the second conductive electrode 22 forming multiple loops through each magnetic tunnel junction bit 10 is less than the preset deviation value.

[0051] Furthermore, in order to improve the lifespan of the magnetoresistive random access memory based on the magnetic tunnel junction bit 10, the resistance value of each of the magnetic tunnel junction bits 10 can be set to be the same.

[0052] It should be noted that, in this embodiment, by setting the resistance value of each magnetic tunnel junction bit 10 to be the same, the complexity of reducing the deviation between each loop can be further reduced, which is beneficial to improving the convenience of large-scale fabrication of magnetoresistive random access memory. The above-mentioned loop is the loop in which the first conductive electrode 21 of the write driver is connected to the second conductive electrode 22 of the write driver in sequence through the first trace 30, through each magnetic tunnel junction bit 10, and the second trace 40.

[0053] The magnetoresistive random access memory provided in this embodiment of the invention includes a plurality of magnetic tunnel junction bits 10, a write driver, a first trace 30 connected to one end of the magnetic tunnel junction bits 10, and a second trace 40 connected to the other end of the magnetic tunnel junction bits 10. The first conductive electrode 21 of the write driver is connected to the first end of the first trace 30, and the second conductive electrode 22 of the write driver is connected to the second end of the second trace 40. The first end and the second end are arranged opposite to each other along the arrangement direction of the plurality of magnetic tunnel junction bits 10, so that the first conductive electrode 21 forms a plurality of loops with the second conductive electrode 22 through each magnetic tunnel junction bit 10, and the deviation value of the trace length between the plurality of loops is less than a preset deviation value. This invention configures the first conductive electrode 21 and the second conductive electrode 22 to face each other along the arrangement direction of the plurality of magnetic tunnel junction bits 10. This ensures that the deviation of the trace length between the first conductive electrode 21 and the second conductive electrode 22 forming multiple loops through each magnetic tunnel junction bit 10 is less than a preset deviation value. This avoids the problem of excessively high near-end write voltage caused by ensuring the write voltage of the far-end magnetic tunnel junction bit 10 in the prior art, thereby improving the device lifespan and the read efficiency of the magnetoresistive random access memory.

[0054] Furthermore, by ensuring that the trace resistance values ​​of the multiple loops formed by the first conductive electrode 21 through the first trace 30, the magnetic tunnel junction bit 10, the second trace 40, and the second conductive electrode 22 are all the same, this embodiment of the invention avoids the problem of high voltage across the magnetic tunnel junction bit 10 in some loops due to resistance differences between different loops, thereby preventing the lifespan of the magnetoresistive random access memory from being affected. By setting the first trace 30 and the second trace 40 to traces of the same material, controlling the correspondence between the trace resistance values ​​of the first trace 30 and the second trace 40 only requires controlling the fabrication process. The trace length and cross-sectional area of ​​the first trace 30 and the second trace 40 are sufficient, which reduces the fabrication complexity of the magnetoresistive random access memory. By setting both the first trace 30 and the second trace 40 as copper metal wires, the fabrication cost of the traces is reduced while taking into account the trace resistance value. Setting the multiple magnetic tunnel junction bits 10 to be arranged in a straight line can ensure the regularity of the memory structure and facilitate fabrication. By setting the resistance value of each magnetic tunnel junction bit 10 to be the same, the complexity of reducing the deviation between each loop can be further reduced, which is conducive to improving the convenience of large-scale fabrication of magnetoresistive random access memory.

[0055] Example 2:

[0056] The magnetoresistive random access memory provided in this embodiment of the invention differs from that in Embodiment 1 in that:

[0057] The deviation between the bus resistance of the first trace and the bus resistance of the second trace is less than the preset line resistance deviation value.

[0058] It should be noted that, in this embodiment, by setting the deviation between the bus resistance of the first trace and the bus resistance of the second trace to be less than the preset line resistance deviation value, the voltage difference required for the magnetic tunnel junction to flip at both ends along the magnetic tunnel junction bit arrangement direction can be further reduced, which makes it easier to ensure that the resistance deviation of the closed loop through each magnetic tunnel junction bit is within the allowable range.

[0059] Furthermore, in order to further ensure that the resistance values ​​of the loops passing through each magnetic tunnel junction bit are the same, the bus resistance of the first trace can be set to be the same as that of the second trace.

[0060] It should be noted that, in this embodiment, by setting the bus resistance of the first trace to be the same as that of the second trace, the voltage difference required for the magnetic tunnel junction to flip at both ends along the magnetic tunnel junction bit arrangement direction can be maximized, thereby ensuring that the resistance value of the closed loop through each magnetic tunnel junction bit is the same, and improving the service life of the magnetoresistive random access memory.

[0061] Furthermore, in order to further improve the ease of fabrication of the first and second traces, both the first and second traces can be configured to have equal resistance everywhere.

[0062] In this embodiment, by setting the first trace and the second trace to have the same resistance everywhere, the uniformity of the resistance values ​​of the first trace and the second trace can be guaranteed. There is no need to consider the resistance value of the first trace or the second trace in a specified area. Thus, while ensuring that the loop resistance value of the first conductive electrode connected to the second conductive electrode through each magnetic tunnel junction bit is the same, the fabrication efficiency of the first trace and the second trace is improved.

[0063] By applying the magnetoresistive random access memory provided in this embodiment of the invention, and by setting the deviation between the bus resistance of the first trace and the bus resistance of the second trace to be less than a preset line resistance deviation value, the voltage difference required for the magnetic tunnel junction to flip at both ends along the magnetic tunnel junction bit arrangement direction can be further reduced, making it easier to ensure that the resistance deviation of the closed loop through each magnetic tunnel junction bit is within the allowable range. Furthermore, by further setting the bus resistance of the first trace and the bus resistance of the second trace to be the same, this embodiment of the invention can maximize the voltage difference required for the magnetic tunnel junction to flip at both ends along the magnetic tunnel junction bit arrangement direction, thereby ensuring that the resistance of the closed loop through each magnetic tunnel junction bit is the same, and improving the service life of the magnetoresistive random access memory. By setting the first trace and the second trace to traces with equal line resistance everywhere, the uniformity of the resistance values ​​of the first trace and the second trace can be ensured. While ensuring that the loop resistance value of the first conductive electrode connected to the second conductive electrode through each magnetic tunnel junction bit is the same, the fabrication efficiency of the first trace and the second trace is improved.

[0064] To make the present invention easier to understand, the above-mentioned magnetoresistive random access memory may specifically include the following structure:

[0065] Multiple magnetic tunnel junction bits, a write driver, a first trace connected to one end of the magnetic tunnel junction bit, and a second trace connected to the other end of the magnetic tunnel junction bit;

[0066] The first conductive electrode of the write driver is connected to the first end of the first trace, and the second conductive electrode of the write driver is connected to the second end of the second trace.

[0067] Multiple magnetic tunnel junction bits are arranged in a straight line. The magnetic tunnel junction bits at the first end and the second end are diagonally arranged in a straight line so that the trace resistance between the first conductive electrode and the second conductive electrode through each magnetic tunnel junction bit is the same.

[0068] Both the first and second traces are copper metal wires;

[0069] The bus resistance of the first trace is the same as that of the second trace, and both the first trace and the second trace have the same resistance everywhere.

[0070] The resistance of each magnetic tunnel junction bit is the same.

[0071] In one specific embodiment, taking a set of arranged magnetic tunnel junction bits including 1024 magnetic tunnel junction bits as an example, wherein the line resistance of the first trace and the line resistance of the second trace are both 0.2 ohms per center distance between two adjacent pins or contacts. A first control group is set up: the first and second ends of the magnetic tunnel junction bits are diagonally arranged along multiple straight lines, the line resistance of the first trace is 0.128 ohms per center distance between two adjacent pins or contacts, and the line resistance of the second trace is 0.37 ohms per center distance between two adjacent pins or contacts; a second control group is set up: the first and second ends are arranged on the same side of the multiple magnetic tunnel junction bits along the arrangement direction, and the line resistance of the first trace is 0.128 ohms per center distance between two adjacent pins or contacts, and the line resistance of the second trace is 0.37 ohms per center distance between two adjacent pins or contacts. Specific test values ​​are shown in Table 1.

[0072] Among them, the voltage difference required for near-far magnetic tunnel junction bit flipping when writing 0 (AP2P) is reduced by 90% compared with the first control group; the voltage difference required for near-far MTJ flipping when writing 1 (P2AP) is reduced by 85% compared with the first control group.

[0073] When writing 0 (AP2P), the voltage difference required for the near-far MTJ to flip is reduced by 99% compared to the second control group; when writing 1 (P2AP), the voltage difference required for the near-far MTJ to flip is reduced by 92% compared to the second control group.

[0074] Table 1

[0075] Write operation The magnetic tunnel junction bits at the first and second ends are diagonally arranged along multiple straight lines. The line resistance of both the first and second traces is 0.2 ohms / pitch. The magnetic tunnel junction bits at the first and second ends are diagonally arranged along multiple straight lines. The line resistance of the first trace is 0.128 ohms / pitch, and the line resistance of the second trace is 0.37 ohms / pitch. The first and second ends are located on the same side of the multiple magnetic tunnel junctions along the arrangement direction. The line resistance of the first trace is 0.128 ohms / pitch, and the line resistance of the second trace is 0.37 ohms / pitch. The voltage difference required for near-far MTJ to flip when writing 0 (AP2P) 1mV 42mV 88mV The voltage difference required for near-far MTJ to flip when writing 1 (P2AP) 10mV 67mV 118mV

[0076] The magnetoresistive random access memory system provided in the embodiments of the present invention will be described below. The magnetoresistive random access memory system described below can be referred to in correspondence with the magnetoresistive random access memory described above.

[0077] Please refer to the details. Figure 3 , Figure 3 This is a schematic diagram of a magnetoresistive random access memory system provided in an embodiment of the present invention. The magnetoresistive random access memory system may include multiple magnetoresistive random access memories as described above.

[0078] It should be noted that in this embodiment, a magnetoresistive random access memory system is composed of multiple magnetoresistive random access memories as described above. In this embodiment, the multiple magnetoresistive random access memories can be configured independently or interconnected.

[0079] The magnetoresistive random access memory system provided in this embodiment of the invention includes multiple magnetoresistive random access memories as described above. Each magnetoresistive random access memory includes at least multiple magnetic tunnel junction bits 10, a write driver, a first trace 30 connected to one end of the magnetic tunnel junction bits 10, and a second trace 40 connected to the other end of the magnetic tunnel junction bits 10. A first conductive electrode 21 of the write driver is connected to a first end of the first trace 30, and a second conductive electrode 22 of the write driver is connected to a second end of the second trace 40. The first and second ends are arranged opposite each other along the arrangement direction of the multiple magnetic tunnel junction bits 10, so that the first conductive electrode 21 forms multiple loops with the second conductive electrode 22 through each magnetic tunnel junction bit 10, and the deviation value of the trace length between the multiple loops is less than a preset deviation value. This invention configures the first conductive electrode 21 and the second conductive electrode 22 to face each other along the arrangement direction of the plurality of magnetic tunnel junction bits 10. This ensures that the deviation of the trace length between the first conductive electrode 21 and the second conductive electrode 22 forming multiple loops through each magnetic tunnel junction bit 10 is less than a preset deviation value. This avoids the problem of excessively high near-end write voltage caused by ensuring the write voltage of the far-end magnetic tunnel junction bit 10 in the prior art, thereby improving the device lifespan and the read efficiency of the magnetoresistive random access memory.

[0080] The various embodiments in this specification are described in a progressive manner. Each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.

[0081] Furthermore, it should be noted that in this document, relationships such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "comprising," "including," or any other variations are intended to cover non-exclusive inclusion.

[0082] The foregoing has provided a detailed description of a magnetoresistive random access memory and a magnetoresistive random access memory system provided by the present invention. Specific examples have been used to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only for the purpose of helping to understand the method and core ideas of the present invention. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of the present invention. Therefore, the content of this specification should not be construed as a limitation of the present invention.

Claims

1. A magnetoresistive random access memory, characterized in that, include: Multiple magnetic tunnel junction bits, a write driver, a first trace connected to one end of the magnetic tunnel junction bits, and a second trace connected to the other end of the magnetic tunnel junction bits; The first conductive electrode of the write driver is connected to the first end of the first trace, and the second conductive electrode of the write driver is connected to the second end of the second trace; The first end and the second end are arranged opposite each other along the arrangement direction of the plurality of magnetic tunnel junction bits, so that the first conductive electrode forms a plurality of loops with the second conductive electrode through each of the magnetic tunnel junction bits, and the deviation value of the trace length between the plurality of loops is less than a preset deviation value.

2. The magnetoresistive random access memory according to claim 1, characterized in that, The trace resistance between the first conductive electrode and the second conductive electrode through each of the magnetic tunnel junction bits is the same.

3. The magnetoresistive random access memory according to claim 1, characterized in that, The first trace and the second trace are traces made of the same material.

4. The magnetoresistive random access memory according to claim 3, characterized in that, Both the first and second traces are copper metal wires.

5. The magnetoresistive random access memory according to claim 1, characterized in that, Multiple magnetic tunneling nodes are arranged in a straight line; Correspondingly, the magnetic tunnel junction bits at the first and second ends are arranged diagonally along multiple straight lines.

6. The magnetoresistive random access memory according to any one of claims 1 to 5, characterized in that, The deviation between the bus resistance of the first trace and the bus resistance of the second trace is less than the preset line resistance deviation value.

7. The magnetoresistive random access memory according to claim 6, characterized in that, The bus resistance of the first trace is the same as that of the second trace.

8. The magnetoresistive random access memory according to claim 7, characterized in that, Both the first and second traces have the same resistance everywhere.

9. The magnetoresistive random access memory according to claim 1, characterized in that, Each of the magnetic tunnel junction bits has the same resistance value.

10. A magnetoresistive random access memory system, characterized in that, It includes multiple magnetoresistive random access memories as described in any one of claims 1 to 9.

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