High-precision low-power-consumption time-to-digital conversion circuit for focal plane detector
By using a segmented timing dual-delay chain vernier-type time-to-digital converter circuit, combined with a coarse and fine counting structure, the problems of high power consumption and large area in the focal plane detector are solved, achieving high-precision, low-power, and large-range time-to-digital conversion.
Patent Information
- Application Number
- CN202510937608.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-07-08
- Publication Date
- 2025-11-28
AI Technical Summary
Existing time-to-digital conversion circuits have high power consumption and large area in focal plane detectors, making it difficult to meet the requirements of low power consumption and high precision for large arrays.
A segmented timing dual-delay chain vernier-type time-to-digital converter circuit is adopted, combined with a coarse and fine counting structure. Time programming is achieved through adjustable delay units and gate-level circuits, resulting in high resolution and low power consumption.
It achieves high-efficiency time resolution and results, reduces power consumption and area, reduces the requirements of delay chain on process, temperature and power supply deviations, and expands the time measurement range.
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Figure CN121028496A_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of electronic and optoelectronic technology, and relates to a high-precision, low-power time-to-digital conversion circuit for focal plane detectors. It is suitable for applications that convert photon time of flight into digital signals. Specifically, it relates to a time-to-digital conversion circuit, which is applicable to laser imaging and laser ranging technologies of array laser focal plane detectors. Background Technology
[0002] High-precision laser focal plane detectors based on Time-of-Flight (TOF) measurement have become core components in the field of 3D perception due to their parallelization, high sensitivity, and anti-interference characteristics. Time-of-flight measurement is a technique that calculates the target distance by measuring the time difference between the emission of a light pulse and its return to the detector after being reflected by the target, combined with the speed of light. There are generally two implementation modes: direct TOF and indirect TOF. Direct TOF measurement technology is mostly used for long-distance, high-precision applications, while indirect TOF technology is more commonly used for short-distance, high-frame-rate scenarios. Focal plane detectors based on TOF measurement technology have wide applications in military and consumer electronics fields such as autonomous driving, aerospace, laser imaging, laser ranging, and navigation communications.
[0003] The Time-to-Digital (TDC) circuit converts the time interval (the time difference between two events) into a digital signal, and is a core component of Time-of-Flight (TOF) measurement technology. Its performance directly affects the ranging accuracy, imaging depth, and reliability of focal plane detectors based on TOF time-of-flight measurements. As laser focal plane detectors develop towards larger array sizes, higher densities, higher precision, and lower power consumption, the detectors also place higher demands on the accuracy, area, and power consumption of the time measurement circuit. Therefore, designing a time-to-digital (TDC) circuit with better time resolution, smaller area, and lower power consumption has become one of the key aspects of focal plane detector development.
[0004] Traditional time-to-digital converter (TDC) circuits based on timers use GHz high-frequency clocks to measure time by recording the number of clock cycles. However, they consume a lot of power and the time resolution is limited by the clock frequency. High-frequency clocks are also difficult to route in large arrays. Vernier delay line TDC structures use a single delay chain to achieve clock cycle accuracy, but they require a large number of delay units, resulting in a large area and a surge in power consumption. Time amplification TDCs amplify tiny time differences using analog circuits before quantization, but they consume a lot of power, have a large area, and a small dynamic range. Summary of the Invention
[0005] (I) Purpose of the Invention
[0006] The purpose of this invention is to propose a miniaturized, low-power, high-resolution, and wide-range segmented timing dual-delay chain vernier time-to-digital converter circuit that addresses the very limited unit circuit area in the readout circuit of a laser focal plane detector and the low power consumption requirement under large array scale.
[0007] (II) Technical Solution
[0008] To address the aforementioned technical problems, this invention provides a high-precision, low-power time-to-digital conversion circuit for a focal plane detector, comprising three main parts: a control module, a measurement module, and a decoding module. The control module is externally connected to a start signal START and an end signal STOP. When the start signal START is valid, the control module generates and outputs a measurement module reset signal RDN, a measurement module start signal START1, and a measurement module end signal STOP1. Upon receiving the start signal START1, the measurement module begins timing; upon receiving the end signal STOP1, it stops timing and generates a 16-bit fine-count temperature code T<15:0> and an 8-bit coarse-count code t<7:0>. The decoding module decodes the 16-bit fine-count code and the 8-bit coarse-count code generated by the measurement module and outputs them as 12-bit binary time digital information.
[0009] Furthermore, the control module, measurement module, and decoding module are connected to the EN signal. The EN signal is the enable signal for the entire circuit. When the EN signal is valid, each module of the circuit works normally; otherwise, the circuit will be in standby mode.
[0010] Furthermore, the control module, measurement module, and decoding module are connected to the CLK signal. The CLK signal is an external clock signal for the circuit, and the clock frequency is a high-frequency clock of 125MHz. The circuit timing is effective at the rising edge of the clock.
[0011] Furthermore, the control module includes an adjustable delay unit, an XOR gate, and an AND gate; the adjustable delay unit is externally connected to a stop signal STOP, the XOR gate is externally connected to a start signal START, the adjustable delay unit is connected to the XOR gate, and the XOR gate is connected to the AND gate; the adjustable delay unit is composed of multiple different adjustable delay modules connected in series. When the stop signal is valid, a reset signal RDN is generated through the gate circuit operation of the XOR gate and the AND gate; the measurement module start signal START1 and the measurement module stop signal STOP1 processed by the control module are transmitted to the measurement module.
[0012] Furthermore, the measurement module includes a coarse counting circuit and a fine counting circuit. The coarse counting circuit is connected to the control module. After the START1 signal output by the control module is valid, the measurement module starts timing. The coarse counting circuit is converted into a gate-level circuit through Verilog programming. The coarse counting circuit adopts a dual-edge triggered structure to receive the measurement module start signal START1, the measurement module end signal STOP1, and the reset signal RDN, obtain the coarse timing value t<7:0>, and output it to the decoding module. The fine counting circuit adopts a dual-delay chain counting structure to obtain the fine counting value T<15:0> and output it to the decoding module.
[0013] Furthermore, in the coarse counting circuit, the counter increments by 1 for each additional clock cycle. When the measurement time is less than one clock cycle, the time data is transmitted to the fine counting circuit. At this time, the value of the counter is read and multiplied by the clock cycle to obtain the coarse timing value t<7:0>.
[0014] Furthermore, in the dual-delay chain counting structure of the fine counting circuit, the delay chain driven by the measurement module start signal START1 is a slow chain, with a transmission delay of td1 for each delay unit. The delay chain input by the measurement module end signal STOP1 is a fast chain, with a transmission delay of td2 for each delay unit. The time interval between the START1 signal and the STOP1 signal is the time to be measured, Tin. Each delay unit shortens the time interval: TLSB = td1 - td2. After the START1 signal and the STOP1 signal pass through the nth delay unit, the time interval between them is Tn = Tin - n·TLSB. Each time the value of n increases, the fine counting code is incremented by 1 and negated once. When Tn is less than or equal to 0 for the first time, time catching up is completed, and the fine count value T<15:0> at this time is read out.
[0015] Furthermore, the decoding module reads the fine count value T<15:0> and the coarse count value t<7:0>, and uses Verilog programming to convert the digital circuit into a gate-level circuit built with AND gates, OR gates, and NAND gates. The 16-bit circuit temperature code is converted into binary code, and after decoding, a 4-bit binary fine count value is obtained as the lower four bits of the time quantization number. This value is then combined with the 8-bit time quantization information output by the measurement module as the higher eight bits of the time quantization number, together forming a 12-bit time quantization information to complete the measurement.
[0016] (III) Beneficial Effects
[0017] The high-precision, low-power time-to-digital conversion circuit for focal plane detectors provided by the above technical solution has the following beneficial effects:
[0018] (1) This invention uses a coarse and fine segmented timing dual-delay chain vernier time-to-digital converter circuit structure, combined with a 4-digit fine timing and an 8-digit coarse timing structure, to achieve high time resolution and large dynamic range of the TDC circuit. Compared with the traditional single-delay chain TDC structure, the difference between the dual delay chains greatly reduces the requirements of delay accuracy on process, temperature and power supply deviation. At the same time, the coarse and fine segmented counting method further expands the time measurement range.
[0019] (2) The circuit structure of the present invention is simple and occupies a small area. Compared with the phase-locked loop structure TDC circuit, it reduces the design difficulty of high-precision clock, reduces power consumption, and reduces area. It is suitable for focal plane laser detector readout circuits with strict requirements on unit circuit area and low power consumption, as well as other small-area, low-power application scenarios.
[0020] (3) The circuit of the present invention adds an adjustable delay laser function for starting timing, which increases the flexibility and applicability of the system application and reduces the complexity of subsequent system data processing. Attached Figure Description
[0021] Figure 1 This is a circuit block diagram of the present invention.
[0022] Figure 2 This is a circuit diagram illustrating the working principle of the present invention.
[0023] Figure 3 This is a diagram of the fine counting structure used in the measurement module of this invention.
[0024] Figure 4 This is the circuit timing diagram of the present invention.
[0025] Figure 5 This is a timing diagram for signal reading in an embodiment. Detailed Implementation
[0026] To make the objectives, contents, and advantages of the present invention clearer, the specific embodiments of the present invention will be described in further detail below with reference to the accompanying drawings and examples.
[0027] Time-to-digital converters (TD-SCDs) used in laser focal plane detectors are limited by their requirements for low power consumption, low parasitic parameters, and small area. This invention provides a low-power, small-area, high-resolution, and wide-range time-to-digital converter (TD-SCD) circuit based on traditional delay-chain TD-SCD circuits, primarily suitable for high-precision time measurement during flight of large-array laser focal plane detectors. The main parameters determining the performance of a time-to-digital converter (TD-SCD) circuit include time resolution, time measurement range, area, and power consumption. The dual-delay-chain segmented timing TD-SCD circuit structure proposed in this invention not only achieves better time resolution but also reduces the number of required D flip-flops, lowering area and power consumption. Furthermore, by combining coarse and fine counting in a two-stage timing method, it obtains a higher number of bits for time conversion, achieving a wider time measurement range.
[0028] like Figure 1 As shown, the high-precision, low-power time-to-digital converter circuit for a focal plane detector in this embodiment includes three main parts: a control module, a measurement module, and a decoding module. The control module is externally connected to a start signal START and an end signal STOP. When the start signal START is valid, the control module generates and outputs a measurement module reset signal RDN, a measurement module start signal START1, and a measurement module end signal STOP1. After receiving the start signal START1, the measurement module starts timing and stops timing after receiving the end signal STOP1, and generates a 16-bit fine-count temperature code T<15:0> and an 8-bit coarse-count code t<7:0>. The decoding module decodes the 16-bit fine-count code and the 8-bit coarse-count code generated by the measurement module and outputs them as 12-bit binary time digital information.
[0029] Furthermore, the control module, measurement module, and decoding module are connected to the EN signal. The EN signal is the enable signal for the entire circuit. When the EN signal is valid, each module of the circuit works normally; otherwise, the circuit will be in standby mode.
[0030] Furthermore, the control module, measurement module, and decoding module are connected to the CLK signal. The CLK signal is an external clock signal for the circuit, and the clock frequency is a high-frequency clock of 125MHz. The circuit timing is effective at the rising edge of the clock.
[0031] like Figure 2As shown, the control module includes an adjustable delay unit, an XOR gate, and an AND gate. The adjustable delay unit is connected to an external stop signal (STOP), and the XOR gate is connected to an external start signal (START). The adjustable delay unit is composed of multiple different adjustable delay modules connected in series, suitable for the delay requirements of different focal plane detector applications. When the stop signal is valid, a reset signal RDN is generated through gate circuit operations of the XOR gate and the AND gate. The control module processes the measurement module's start signal START1 and end signal STOP1, which are then transmitted to the measurement module.
[0032] like Figure 2 As shown, the measurement module includes a coarse counting circuit and a fine counting circuit. The coarse counting circuit is connected to the control module and receives the measurement module start signal START1, the measurement module end signal STOP1, and the reset signal RDN.
[0033] After the START1 signal output by the control module becomes valid, the measurement module starts timing. Using Verilog programming, the coarse counting circuit is converted into a gate-level circuit. The coarse counting circuit is built with a simple double-edge triggered structure; the counter increments by 1 for each additional clock cycle. When the measurement time is less than one clock cycle, the time data is passed to the fine counting circuit. At this point, the counter value is read and multiplied by the clock cycle to obtain the coarse timing value t<7:0>, which is then output to the decoding module. The fine counting circuit uses a double-delay chain counting structure to obtain the fine counting value T<15:0>, which is also output to the decoding module.
[0034] like Figure 3 As shown, in the dual-delay chain counting structure, the delay chain driven by the measurement module start signal START1 is a slow chain, with a transmission delay of td1 for each delay unit. The delay chain input by the measurement module end signal STOP1 is a fast chain, with a transmission delay of td2 for each delay unit. The time interval between the START1 signal and the STOP1 signal is the time to be measured, Tin. Each delay unit shortens the time interval: TLSB = td1 - td2. After the nth delay unit, the time interval between the START1 signal and the STOP1 signal is Tn = Tin - n·TLSB. Each time the value of n increases, the fine count code is incremented by 1 and negated once. When Tn is less than or equal to 0 for the first time, time catching up is completed, and the fine count value T<15:0> is read out at this time.
[0035] like Figure 2As shown, the decoding module reads the fine count value T<15:0> and the coarse count value t<7:0>, and uses Verilog programming to convert the digital circuit into a gate-level circuit built with AND gates, OR gates, NAND gates, etc., converting the 16-bit circuit temperature code into binary code. The code table is shown in Table 1. After decoding, a 4-bit binary fine count value is obtained, which is used as the lower four bits of the time quantization number. Combined with the 8-bit time digital information output by the measurement module, which is used as the higher eight bits of the time quantization number, the two bits together form a 12-bit time digital quantization information to complete the measurement.
[0036] Temperature code binary code Temperature code binary code 1000000000000000 0000 0111111111111111 0000 1100000000000000 0001 0011111111111111 0001 1110000000000000 0010 0001111111111111 0010 1111000000000000 0011 0000111111111111 0011 1111100000000000 0100 0000011111111111 0100 1111110000000000 0101 0000001111111111 0101 1111111000000000 0110 0000000111111111 0110 1111111100000000 0111 0000000011111111 0111 1111111110000000 1000 0000000001111111 1000 1111111111000000 1001 0000000000111111 1001 1111111111100000 1010 0000000000011111 1010 1111111111110000 1011 0000000000001111 1011 1111111111111000 1100 0000000000000111 1100 1111111111111100 1101 0000000000000011 1101 1111111111111110 1110 0000000000000001 1110 1111111111111111 1111 0000000000000000 1111
[0037] Example
[0038] The overall working principle diagram of the present invention is as follows: Figure 4 As shown, when the circuit is working, the enable signal EN is set to active. After the time signal arrives, the START signal is set to high level. The measurement time is T, and TN is the minimum period of CLK (i.e., the clock period of the coarse timing module, 8ns). The period is measured as an integer using coarse timing, and the measurement result is n×TN. The time that does not meet an integer period is the error between the start signal START and the stop signal STOP, which is then measured using fine timing, thus completing the measurement of the entire flight time. Assuming the flight time is 20.6ns, if... Figure 5 As shown.
[0039] Step 1: When the START signal is high, the coarse timer starts working. After the falling edge of the reset signal arrives, the timer stops counting. The timer reads the value dou[7:0] as 00000010, and the corresponding counting time is 8ns × (21) = 16ns.
[0040] Step 2: The portion less than 8ns is not read; instead, it is read by a fine counter. Since the fine counter circuit consists of a double-delay chain vernier circuit, due to delays from triggers and inverting gates, the fine counter circuit has a fixed delay of 1.25ns. The temperature code read from the fine counter at this point is 1111111000000000.
[0041] Step 3: The 16-bit temperature code is converted into a 4-bit binary code 0110 using a decoding circuit. The overall timing value of the readout circuit is 000000100110, corresponding to a timing time of 8ns × 2¹ + 0.5ns × (2² + 2¹) = 19ns. Adding a fixed delay of 1.25ns, the timing time is 20.25ns, which is within 0.5ns of the flight time of 20.6ns, meeting the design requirements.
[0042] The above description is only a preferred embodiment of the present invention. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the technical principles of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.
Claims
1. A high-precision, low-power time-to-digital conversion circuit for a focal plane detector, characterized in that, include: The system consists of three main parts: a control module, a measurement module, and a decoding module. The control module is externally connected to a start signal (START) and an end signal (STOP). When the start signal (START) is valid, the control module generates and outputs a measurement module reset signal (RDN), a measurement module start signal (START1), and a measurement module end signal (STOP1). Upon receiving the start signal (START1), the measurement module begins timing, and upon receiving the end signal (STOP1), it stops timing and generates a 16-bit fine-count temperature code (T<15:0>) and an 8-bit coarse-count code (t<7:0>). The decoding module decodes the 16-bit fine-count code and the 8-bit coarse-count code generated by the measurement module and outputs them as 12-bit binary time information.
2. The high-precision, low-power time-to-digital conversion circuit for a focal plane detector as described in claim 1, characterized in that, The control module, measurement module, and decoding module are connected to the EN signal. The EN signal is the enable signal for the entire circuit. When the EN signal is valid, each module of the circuit works normally; otherwise, the circuit will be in standby mode.
3. The high-precision, low-power time-to-digital conversion circuit for a focal plane detector as described in claim 2, characterized in that, The control module, measurement module, and decoding module are connected to the CLK signal. The CLK signal is an external clock signal for the circuit, and the clock frequency is a high-frequency clock of 125MHz. The circuit timing is valid at the rising edge of the clock.
4. The high-precision, low-power time-to-digital conversion circuit for a focal plane detector as described in claim 3, characterized in that, The control module includes an adjustable delay unit, an XOR gate, and an AND gate. The adjustable delay unit is connected to an external stop signal (STOP), and the XOR gate is connected to an external start signal (START). The adjustable delay unit is connected to the XOR gate and the AND gate. The adjustable delay unit is composed of multiple different adjustable delay modules connected in series. When the stop signal is valid, a reset signal (RDN) is generated through the gate circuit operation of the XOR gate and the AND gate. The measurement module start signal (START1) and the measurement module stop signal (STOP1) processed by the control module are transmitted to the measurement module.
5. The high-precision, low-power time-to-digital conversion circuit for a focal plane detector as described in claim 4, characterized in that, The measurement module includes a coarse counting circuit and a fine counting circuit. The coarse counting circuit is connected to the control module. After the START1 signal output by the control module is valid, the measurement module starts timing. The coarse counting circuit is converted into a gate-level circuit through Verilog programming. The coarse counting circuit adopts a dual-edge triggered structure to receive the measurement module start signal START1, the measurement module end signal STOP1, and the reset signal RDN, and obtains the coarse timing value t<7:0> and outputs it to the decoding module. The fine counting circuit adopts a dual-delay chain counting structure to obtain the fine counting value T<15:0> and outputs it to the decoding module.
6. The high-precision, low-power time-to-digital conversion circuit for a focal plane detector as described in claim 5, characterized in that, In the coarse counting circuit, the counter increments by 1 for each additional clock cycle. When the measurement time is less than one clock cycle, the time data is transmitted to the fine counting circuit. At this time, the counter value is read and multiplied by the clock cycle to obtain the coarse timing value t<7:0>.
7. The high-precision, low-power time-to-digital conversion circuit for a focal plane detector as described in claim 6, characterized in that, In the dual-delay chain counting structure of the fine counting circuit, the delay chain driven by the measurement module start signal START1 is a slow chain, with a transmission delay of td1 for each delay unit. The delay chain input by the measurement module end signal STOP1 is a fast chain, with a transmission delay of td2 for each delay unit. The time interval between the START1 signal and the STOP1 signal is the time to be measured, Tin. Each delay unit shortens the time interval: TLSB = td1 - td2. After the nth delay unit, the time interval between the START1 signal and the STOP1 signal is Tn = Tin - n·TLSB. Each time the value of n increases, the fine counting code is incremented by 1 and negated once. When Tn is less than or equal to 0 for the first time, time catching up is completed, and the fine count value T<15:0> is read out at this time.
8. The high-precision, low-power time-to-digital conversion circuit for a focal plane detector as described in claim 7, characterized in that, The decoding module reads the fine count value T<15:0> and the coarse count value t<7:0>, and uses Verilog programming to convert the digital circuit into a gate-level circuit built with AND, OR, and NAND gates. It converts the 16-bit circuit temperature code into binary code, and after decoding, obtains a 4-bit binary fine count value, which serves as the lower four bits of the time quantization digit. This value is then combined with the 8-bit time quantization digit output by the measurement module, which serves as the higher eight bits of the time quantization digit, to form a total of 12-bit time quantization digits, thus completing the measurement.
9. The high-precision, low-power time-to-digital conversion circuit for a focal plane detector as described in claim 8, characterized in that, The code table for converting the 16-bit circuit temperature code to binary code is as follows: 。 10. An array laser focal plane detector, characterized in that, The high-precision, low-power time-to-digital converter circuit for a focal plane detector includes any one of claims 1-9.