Transistor selection method, apparatus and computer device for equalizing current

Abstract

The application discloses a transistor selection method, device and computer equipment for balancing current. The method comprises the following steps: acquiring a plurality of rise times corresponding to a plurality of transistors respectively and a target number of transistors for a parallel circuit, wherein the rise time is a time required for a drain-source voltage of the transistor to rise to a corresponding preset voltage measurement point during turn-off; selecting the target number of transistors from the plurality of transistors, traversing all selected combinations to obtain a plurality of parallel groups of the plurality of transistors; determining an average difference coefficient corresponding to each of the plurality of parallel groups of the plurality of transistors based on the plurality of rise times corresponding to the plurality of transistors respectively; and taking the plurality of transistors in a parallel group of transistors with the average difference coefficient less than a preset threshold as a plurality of target transistors, wherein the plurality of target transistors are used for the parallel circuit. The application solves the technical problems of high complexity and poor dynamic response of the current balancing control technology for the transistors of the parallel circuit.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor technology, and in particular, to a transistor selection method, device and computer equipment for balancing current. BACKGROUND

[0002] In the field of power electronics, silicon carbide (SiC) MOSFET (Metal Oxide Semiconductor Field Effect Transistor) has become a key technology driving industry development due to its unique material properties. However, as the limitations of single MOSFET carrying capacity become increasingly apparent, in order to meet higher power requirements, the use of multiple chips in parallel becomes necessary. Parallel MOSFETs can significantly improve the total power handling capacity of the system and reduce the difficulty of thermal management, but at the same time, it also brings a key challenge: current unbalance. Even MOSFETs of the same batch may have differences in key parameters such as on-resistance, switching time and thermal characteristics, and these small differences will be amplified under parallel conditions, leading to uneven distribution of current among different chips, which not only affects system efficiency, but also may cause overheating, voltage imbalance and circulating current, etc., thereby reducing overall reliability and stability.

[0003] Existing current balancing control techniques, such as control based on gate drive or current monitoring feedback, while being able to solve the problem of uneven current to some extent, often require complex hardware circuits, increasing design complexity and cost, and may be disturbed by noise in high-frequency switching environments, affecting control accuracy and response speed. In addition, chip sorting methods based on static parameters (such as on-resistance) can initially screen out chips with similar parameters, but do not fully consider the matching of dynamic characteristics, resulting in less than ideal current balancing effect in actual applications, especially under fast switching conditions.

[0004] In view of the above problems, no effective solutions have been proposed so far. SUMMARY

[0005] The embodiments of the present application provide a transistor selection method, device and computer equipment for balancing current, to at least solve the technical problems of high complexity and poor dynamic response of current balancing control techniques for parallel circuit transistors.

[0006] According to an aspect of the embodiments of the present application, a transistor selection method for balancing current is provided, including: obtaining a plurality of rise times respectively corresponding to a plurality of transistors and a target number of transistors for a parallel circuit, wherein the rise time is a time required for a drain-source voltage of the transistor to rise to a corresponding preset voltage measurement point during a turn-off process of the transistor; selecting the target number of transistors from the plurality of transistors, traversing all selected combinations to obtain a plurality of parallel groups of the plurality of transistors; determining an average difference coefficient respectively corresponding to each of the plurality of parallel groups of the plurality of transistors based on the plurality of rise times respectively corresponding to the plurality of transistors, wherein the average difference coefficient represents an average difference degree of turn-off characteristics between the plurality of transistors in the corresponding parallel group of the transistors; and taking the plurality of transistors in the parallel group of the transistors with the average difference coefficient less than a preset threshold as a plurality of target transistors, wherein the plurality of target transistors are used for the parallel circuit.

[0007] Optionally, the obtaining the plurality of rise times respectively corresponding to the plurality of transistors includes: generating a plurality of single pulse signals based on a signal generator, wherein a width and an amplitude of each of the plurality of single pulse signals are matched with a working condition respectively corresponding to each of the plurality of transistors; simulating a turn-off process of the plurality of transistors based on a preset test circuit and the plurality of single pulse signals to determine a relationship curve between a drain-source voltage and a time of the plurality of transistors during the turn-off process; and determining the plurality of rise times respectively corresponding to the plurality of transistors based on the relationship curve respectively corresponding to each of the plurality of transistors and a plurality of preset voltage measurement points.

[0008] Optionally, the preset test circuit is a symmetric circuit, wherein in the symmetric circuit, distances from the drain of each of the plurality of transistors to a positive input point of the symmetric circuit are the same, and distances from the source of each of the plurality of transistors to a negative output point of the symmetric circuit are the same.

[0009] Optionally, the determining the average difference coefficient respectively corresponding to each of the plurality of parallel groups of the plurality of transistors based on the plurality of rise times respectively corresponding to the plurality of transistors, wherein the average difference coefficient represents an average difference degree of turn-off characteristics between the plurality of transistors in the corresponding parallel group of the transistors, includes: determining a difference coefficient between any two transistors in the plurality of parallel groups of the plurality of transistors based on the plurality of rise times respectively corresponding to the plurality of transistors, wherein the difference coefficient represents a difference degree of turn-off characteristics between the two transistors; and respectively calculating an average value of the plurality of difference coefficients respectively corresponding to each of the plurality of parallel groups of the plurality of transistors to determine the average difference coefficient respectively corresponding to each of the plurality of parallel groups of the plurality of transistors.

[0010] Optionally, the difference coefficient between any two transistors in the parallel group of transistors is determined based on the plurality of rise times corresponding to the plurality of transistors, respectively, wherein the difference coefficient between the first transistor and the second transistor is calculated as follows: the first transistor and the second transistor are any two transistors in any one of the parallel groups of transistors: a difference value between the rise times corresponding to the first transistor and the second transistor at the plurality of preset voltage measurement points is calculated; an average time difference is determined based on the difference value; and the difference coefficient between the first transistor and the second transistor is determined according to the average time difference.

[0011] According to another aspect of the embodiments of the present application, a transistor selection system for balancing current is also provided, comprising: a test platform configured to obtain a plurality of rise times corresponding to a plurality of transistors, respectively, wherein the rise time is a time required for a drain-source voltage of the transistor to rise to a corresponding preset voltage measurement point during a turn-off process; and an analysis platform configured to determine a plurality of target transistors based on the plurality of rise times corresponding to the plurality of transistors, respectively, wherein the plurality of target transistors are used in a parallel circuit.

[0012] Optionally, the test platform comprises: a signal generator, a test circuit, an oscilloscope, and a calculation module, wherein the signal generator is configured to generate a plurality of single pulse signals, wherein the width and amplitude of each of the plurality of single pulse signals are matched with the working condition of each of the plurality of transistors; the test circuit is configured to simulate the turn-off process of the plurality of transistors; the oscilloscope is configured to determine a relationship curve between the drain-source voltage and the time during the turn-off process of the plurality of transistors; and the calculation module is configured to determine the plurality of rise times corresponding to the plurality of transistors based on the relationship curve corresponding to each of the plurality of transistors and the plurality of preset voltage measurement points.

[0013] According to another aspect of the embodiments of the present application, a transistor selection device for balancing current is also provided, comprising: an obtaining module configured to obtain a plurality of rise times corresponding to a plurality of transistors, respectively, and a target number of transistors used in a parallel circuit, wherein the rise time is a time required for a drain-source voltage of the transistor to rise to a corresponding preset voltage measurement point during a turn-off process; a traversal module configured to select the target number of transistors from the plurality of transistors, traverse all selected combinations, and obtain a plurality of parallel groups of transistors; a determining module configured to determine an average difference coefficient corresponding to each of the plurality of parallel groups of transistors based on the plurality of rise times corresponding to the plurality of transistors, respectively, wherein the average difference coefficient represents an average difference degree of turn-off characteristics between the plurality of transistors in the corresponding parallel group of transistors; and a selection module configured to select the plurality of transistors in the parallel group of transistors with the average difference coefficient less than a preset threshold as a plurality of target transistors, wherein the plurality of target transistors are used in the parallel circuit.

[0014] According to a further aspect of the embodiments of the present application, a non-transitory storage medium is also provided, which includes a stored program, wherein the program, when executed, controls a device in which the non-transitory storage medium is located to perform any one of the above transistor selection methods for balancing current.

[0015] According to a further aspect of the embodiments of the present application, a computer device is also provided, which includes a processor configured to execute a program, wherein the program, when executed, performs any one of the above transistor selection methods for balancing current.

[0016] According to a further aspect of the embodiments of the present application, a computer program product is also provided, which includes a computer program configured to, when executed by a processor, implement any one of the above transistor selection methods for balancing current.

[0017] In the embodiments of the present application, the transistor selection method for balancing current is adopted, the target number of transistors for the parallel circuit is obtained by acquiring a plurality of rise times corresponding to the plurality of transistors respectively and the target number of transistors, wherein the rise time is the time required for the drain-source voltage of the transistor to rise to the corresponding preset voltage measurement point during the turn-off process; the target number of transistors is selected from the plurality of transistors, all selected combinations are traversed to obtain a plurality of parallel groups of transistors; the average difference coefficient corresponding to each of the plurality of parallel groups of transistors is determined based on the plurality of rise times corresponding to the plurality of transistors respectively, wherein the average difference coefficient represents the average difference degree of the turn-off characteristics between the plurality of transistors in the corresponding parallel group of transistors; the plurality of transistors in the parallel group of transistors with the average difference coefficient less than the preset threshold value are taken as the plurality of target transistors, wherein the plurality of target transistors are used for the parallel circuit, thereby achieving the purpose of selecting the transistor combination with balanced branch current in parallel, and realizing the technical effect of improving system stability and efficiency, and further solving the technical problems of high complexity and poor dynamic response of the current balancing regulation technology for transistors used in the parallel circuit. BRIEF DESCRIPTION OF DRAWINGS

[0018] The accompanying drawings, which are included to provide a further understanding of the present application and are incorporated in and constitute a part of this application, illustrate embodiments of the present application and serve to explain the present application. In the drawings:

[0019] Figure 1 Fig. 1 shows a hardware structure block diagram of a computer terminal for implementing the transistor selection method for balancing current according to an embodiment of the present application;

[0020] Figure 2 Fig. 2 is a flowchart of the transistor selection method for balancing current according to an embodiment of the present application;

[0021] Figure 3is a flow chart of a process of building a silicon carbide MOSFET dynamic characteristic test platform according to an optional embodiment of the present application;

[0022] Figure 4 is a flow chart of single pulse signal test and voltage rising curve acquisition according to an optional embodiment of the present application;

[0023] Figure 5 is an experimental test schematic diagram of 30 silicon carbide MOSFET chip turn-off voltage rising curves according to an optional embodiment of the present application;

[0024] Figure 6 is a flow chart of chip sorting according to an optional embodiment of the present application;

[0025] Figure 7 is a structural block diagram of a transistor selection device for equalizing current according to an embodiment of the present application. DETAILED DESCRIPTION

[0026] In order to make the personnel in the technical field better understand the present application scheme, the technical scheme in the embodiments of the present application will be described clearly and completely below in combination with the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, not all. Based on the embodiments in the present application, all other embodiments obtained by the person skilled in the art without creative labor should belong to the protection scope of the present application.

[0027] It should be noted that the terms "first", "second", and the like in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and do not necessarily describe a specific order or sequence. It should be understood that the data used in this way can be interchanged under appropriate circumstances, so that the embodiments of the present application described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusion, for example, a process, method, system, product or device including a series of steps or units does not necessarily limit to those steps or units clearly listed, but can include other steps or units not clearly listed or inherent to these processes, methods, products or devices.

[0028] According to an embodiment of the present application, a transistor selection method embodiment for equalizing current is provided. It should be noted that the steps shown in the flowchart of the drawings can be executed in a computer system such as a set of computer executable instructions, and although the logical order is shown in the flowchart, in some cases, the steps shown or described herein can be executed in an order different from that herein.

[0029] The method embodiment provided in Embodiment 1 of this application can be executed on a mobile terminal, computer terminal, or similar computing device. Figure 1 A hardware block diagram of a computer terminal for implementing a transistor selection method for balancing current is shown. Figure 1 As shown, the computer terminal 10 may include one or more processors (shown as 102a, 102b, ..., 102n in the figure) (the processor may include, but is not limited to, a microprocessor MCU or a programmable logic device FPGA, etc.) and a memory 104 for storing data. In addition, it may also include: a display, an input / output interface (I / O interface), a universal serial bus (USB) port (which may be included as one of the ports of a BUS bus), a network interface, a power supply, and / or a camera. Those skilled in the art will understand that... Figure 1 The structure shown is for illustrative purposes only and does not limit the structure of the aforementioned electronic device. For example, computer terminal 10 may also include... Figure 1 The more or fewer components shown, or having the same Figure 1 The different configurations shown.

[0030] It should be noted that the aforementioned one or more processors and / or other data processing circuits are generally referred to herein as "data processing circuits". These data processing circuits may be embodied, in whole or in part, in software, hardware, firmware, or any other combination thereof. Furthermore, the data processing circuits may be a single, independent processing module, or may be integrated, in whole or in part, into any other element within the computer terminal 10. As involved in the embodiments of this application, the data processing circuits serve as a processor control mechanism (e.g., selection of a variable resistor termination path connected to an interface).

[0031] The memory 104 can be used to store software programs and modules for application software, such as the program instructions / data storage device corresponding to the transistor selection method for balancing current in the embodiments of the present invention. The processor executes various functional applications and data processing by running the software programs and modules stored in the memory 104, that is, implementing the transistor selection method for balancing current in the above-mentioned application. The memory 104 may include high-speed random access memory, and may also include non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some instances, the memory 104 may further include memory remotely located relative to the processor, and these remote memories can be connected to the computer terminal 10 via a network. Examples of such networks include, but are not limited to, the Internet, corporate intranets, local area networks, mobile communication networks, and combinations thereof.

[0032] The display can be a liquid crystal display (LCD) of the touch screen type, which enables the user to interact with the user interface of the computer terminal 10.

[0033] Figure 2 is a flowchart of a transistor selection method for balancing current according to an embodiment of the present application, as shown, the method comprises the following steps: Figure 2

[0034] In step S201, a plurality of rise times corresponding to a plurality of transistors respectively and a target number of transistors for a parallel circuit are obtained, wherein the rise time is the time required for the drain-source voltage of the transistor to rise to a corresponding preset voltage measurement point during the turn-off process.

[0035] In this step, in the present embodiment, the transistors can be silicon carbide MOSFETs. The rise time can refer to the time required for the drain-source voltage (Vds) of the transistor to rise from a certain initial value to a preset voltage measurement point during the turn-off process. Specifically, this preset voltage measurement point can be a certain percentage of the blocking voltage of the transistor (i.e. the voltage when completely turned off), for example, the time from 10% of the blocking voltage to 90% of the blocking voltage, which is often used to evaluate the switching speed and dynamic performance of the transistor. In order to obtain these rise times, a high-precision dynamic characteristic test platform can be used. The platform can apply a single pulse signal to simulate the normal turn-off process of the transistor, and monitor the voltage waveform of Vds in real time through an oscilloscope or a high-precision data acquisition system. By accurately measuring the time taken for the Vds voltage to rise from 10% to 90% of the blocking voltage when each transistor is turned off, the dynamic voltage rise curve of each transistor can be obtained, and the rise time of each transistor can be obtained.

[0036] In step S202, a target number of transistors are selected from the plurality of transistors, and all selected combinations are traversed to obtain a plurality of parallel transistor groups.

[0037] In this step, traversing the selected combinations means trying all possible combinations in the transistor pool in order. For example, if there are 20 transistors and 5 transistors are selected for parallel connection, there are theoretically C(20,5) combinations (i.e. the number of combinations of selecting 5 from 20 different objects). After traversing all combinations, a plurality of parallel transistor groups are obtained. The combinations in these parallel transistor groups that are highly consistent in the characteristics of the turn-off voltage rise curve are the ideal choices for current balancing.

[0038] In step S203, based on the plurality of rise times corresponding to the plurality of transistors respectively, an average difference coefficient corresponding to each of the plurality of parallel transistor groups is determined, wherein the average difference coefficient represents the average difference degree of the turn-off characteristics between the plurality of transistors in the corresponding parallel transistor group. ​

[0039] In this step, the smaller the average difference coefficient, the more consistent the turn-off characteristics of the transistors in the parallel group, i.e., the smaller the time difference of the drain-source voltage rising to the preset measurement point during the turn-off process. This indicates that the transistors have high consistency in dynamic characteristics, which is beneficial to reduce the current unbalanced flow phenomenon in parallel operation and improve the stability and efficiency of the overall circuit. By traversing all possible parallel group combinations, their average difference coefficients are calculated and compared, and the parallel group with a coefficient less than the preset threshold is selected as the final preferred combination, ensuring that the turn-off characteristics of the transistors in the parallel circuit are matched, thereby achieving balanced distribution of current, avoiding circulating current and voltage imbalance problems, and improving the performance and reliability of the circuit under high power density applications.

[0040] In step S204, the transistors in the parallel group with an average difference coefficient less than the preset threshold are selected as a plurality of target transistors, wherein the plurality of target transistors are used in the parallel circuit.

[0041] In this step, the preset threshold is a standard value set according to the circuit design requirements, system stability requirements, and specific application conditions (such as power level, switching frequency), which is used to distinguish which parallel group's average difference coefficient is considered acceptable. The setting of this threshold needs to consider multiple factors, including but not limited to the accuracy requirements of current sharing, the demand for system reliability, cost budget, and actual operability. For example, for applications with high-precision current sharing and high reliability requirements, the preset threshold may be set lower to ensure that the transistors have extremely high consistency in dynamic characteristics. After calculating the average difference coefficients of all possible parallel groups, the transistors in the parallel group with an average difference coefficient less than the threshold can be marked as "target transistors" according to the preset threshold. These target transistors, due to their high consistency in turn-off dynamic characteristics, are ideal choices for achieving current sharing and optimizing the performance of the parallel circuit.

[0042] Through the above steps, the purpose of selecting a transistor combination with balanced shunt current in parallel is achieved, thereby achieving the technical effect of improving system stability and efficiency, and further solving the technical problems of high complexity and poor dynamic response of the current balancing control technology for transistors used in parallel circuits.

[0043] As an optional embodiment, the step of obtaining the plurality of rise times corresponding to the plurality of transistors respectively comprises: generating a plurality of single pulse signals based on the signal generator, wherein the plurality of single pulse signals respectively correspond to the working conditions of the plurality of transistors one by one; simulating the turn-off process of the plurality of transistors based on the preset test circuit and the plurality of single pulse signals to determine the relationship curves between the drain-source voltage and time of the plurality of transistors in the turn-off process; and determining the plurality of rise times corresponding to the plurality of transistors respectively based on the relationship curves corresponding to the plurality of transistors respectively and the plurality of preset voltage measurement points.

[0044] Optionally, the signal generator is a test device capable of generating a specific signal waveform. In the present application, it is used to generate a series of single pulse signals to simulate the switching process of MOSFET under actual working conditions. The width and amplitude of these single pulse signals need to match the working conditions of each MOSFET transistor being tested, so as to ensure that the test results can accurately reflect the dynamic characteristics of the transistor in real application scenarios.

[0045] The preset test circuit is a specific circuit configuration designed to capture and analyze the dynamic characteristics of the transistor. In this step, the single pulse signal generated by the signal generator is applied to the gate of each transistor to simulate its dynamic behavior in the turn-off process. The test circuit usually includes necessary power supply, load, measurement equipment (such as oscilloscope) and protection circuit to ensure the safety and accuracy of the test. After receiving the single pulse signal, the transistor will undergo a dynamic process from turn-on to turn-off. This process can be recorded by monitoring the waveform of the drain-source voltage (Vds) of the transistor changing over time. Through the oscilloscope or other high-precision data acquisition system, the relationship curve between the Vds voltage and time of the transistor in the turn-off process can be obtained, which helps to understand the dynamic response characteristics of the transistor, especially the voltage change rate in the turn-off process.

[0046] After obtaining the relationship curve between the Vds voltage and time of the transistor in the turn-off process, the curve can be analyzed to determine the rise time of the transistor. The rise time refers to the time required for the Vds voltage of the transistor to rise from a preset low voltage point to a high voltage point in the turn-off process. The selection of the preset voltage measurement points is determined according to the specific application requirements and the characteristics of the transistor. For example, a common choice is to rise from 10% of the blocking voltage to 90% of the blocking voltage as the measurement interval, because this interval covers the main dynamic process of the transistor from near turn-on to near complete turn-off, which can effectively reflect the switching speed and dynamic characteristics of the transistor. By analyzing the relationship curve between the Vds voltage and time of each transistor, the rise time of the transistor between different preset voltage measurement points can be determined.

[0047] As an optional embodiment, the preset test circuit is a symmetric circuit, wherein the distance from the drain of each transistor to the positive input point of the symmetric circuit is the same, and the distance from the source of each transistor to the negative output point of the symmetric circuit is the same.

[0048] Optionally, the main purpose of the symmetric circuit design is to eliminate the additional parasitic parameter differences introduced by the asymmetric circuit layout, which may affect the accuracy of the test results and further affect the subsequent transistor sorting and parallel circuit performance optimization. In parallel testing, if the circuit layout is asymmetric, each transistor may face different parasitic inductance and parasitic resistance, which may cause the current and voltage waveforms to be inconsistent between different transistors, even if their own characteristics are very close. The preset test circuit adopts a symmetric layout, which means that the distance from the drain of all transistors in the circuit to the positive input point of the test circuit is the same, and the distance from their source to the negative output point of the test circuit is also the same. This design ensures that the circuit environment experienced by each transistor during testing is consistent, avoiding test errors caused by layout differences.

[0049] As an optional embodiment, based on the plurality of rise times corresponding to the plurality of transistors, the average difference coefficient corresponding to each of the plurality of parallel groups of transistors is determined, wherein the average difference coefficient represents the average difference degree of the turn-off characteristics between the plurality of transistors in the corresponding parallel group of transistors, comprising: based on the plurality of rise times corresponding to the plurality of transistors, determining the difference coefficient between any two transistors in the plurality of parallel groups of transistors, wherein the difference coefficient represents the difference degree of the turn-off characteristics between the two transistors; respectively calculating the average value of the plurality of difference coefficients corresponding to each of the plurality of parallel groups of transistors to determine the average difference coefficient corresponding to each of the plurality of parallel groups of transistors.

[0050] Optionally, for each parallel group, all difference coefficients between any two transistors in the group can be calculated, and then the average value of these difference coefficients, i.e. the average difference coefficient, is calculated. The average difference coefficient reflects the consistency level of the turn-off characteristics of the transistors in the parallel group. After completing the average difference coefficient calculation of all parallel groups, the parallel group with the smallest average difference coefficient or below a preset threshold value will be selected as the target group for the final parallel circuit design. This selection ensures that the circuit can achieve the best current sharing under high power density applications, improving the stability and efficiency of the overall circuit.

[0051] As an optional embodiment, the difference coefficient between any two transistors in the parallel group of transistors is determined based on the respective rising times of the plurality of transistors. The difference coefficient between the first transistor and the second transistor is calculated as follows: the difference between the respective rising times of the first transistor and the second transistor at the plurality of preset voltage measurement points is calculated; based on the difference, the average time difference is determined; and the difference coefficient between the first transistor and the second transistor is determined according to the average time difference.

[0052] Optionally, any two transistors in the parallel group can be selected, for example, the first transistor and the second transistor. Based on the previous dynamic characteristic test, the voltage rising curve of the two transistors during the off process has been obtained, as well as the rising time of the plurality of preset voltage measurement points in the interval from 10% blocking voltage to 90% blocking voltage. For each measurement point, the difference between the rising times of the first transistor and the second transistor is calculated, which directly reflects the consistency of the two transistors in the off characteristic. All the calculated differences are averaged to obtain the "average time difference". The average time difference quantifies the consistency level of the first transistor and the second transistor in the off characteristic. The smaller the difference is, the closer the dynamic characteristics of the two transistors are. Finally, the average time difference can be used as the difference coefficient to more intuitively evaluate the consistency of the off characteristics of the two transistors.

[0053] As an optional embodiment, a silicon carbide MOSFET multi-chip parallel off current sharing regulation method based on dynamic parameter sorting is also provided. The method realizes the current equalization distribution of parallel chips through dynamic sorting technology, thereby improving the stability and efficiency of the system. The specific steps can include:

[0054] Step one: build a silicon carbide MOSFET dynamic characteristic test platform. Figure 3 According to the optional embodiment of the present application, a flow chart for building a silicon carbide MOSFET dynamic characteristic test platform is provided, as shown in Figure 3 The specific process can include:

[0055] S1: test platform design. A high-precision, repeatable dynamic characteristic test platform is built to support dynamic performance evaluation of different types of silicon carbide MOSFETs. The test platform includes a signal generator, an oscilloscope, a direct current power source, and a driving voltage source.

[0056] S2: single pulse signal generation. The signal generator is used to generate a single pulse signal with precise timing and amplitude. The width and amplitude of the pulse signal should cover the actual working conditions to simulate various situations that the MOSFET may encounter during the off process.

[0057] S3: Test circuit symmetrical layout design. In order to avoid the influence of the difference of the circuit parasitic parameters caused by the asymmetrical layout of the circuit on the parallel current distribution, the circuit parameters are adjusted through the symmetrical layout design of the test circuit, and each parallel MOSFET to be tested is placed under the symmetrical layout.

[0058] Step two: Single pulse signal test and voltage rising curve acquisition. Figure 4 A flowchart of single pulse signal test and voltage rising curve acquisition is provided according to an optional embodiment of the present application, as shown in Figure 4 The specific flow can include:

[0059] S4: Single pulse signal application. A single pulse signal is applied to the gate of each MOSFET to simulate the switching process in normal operation. The rising edge of the first pulse turns on the MOSFET, and the falling edge of the first pulse turns off the MOSFET to acquire the voltage rising curve.

[0060] S5: Voltage waveform acquisition. The voltage rising curve of the MOSFET during the turn-off process is monitored in real time through an oscilloscope or a high-precision data acquisition system. Figure 5 An experimental test schematic diagram of the turn-off voltage rising curve of 30 silicon carbide MOSFET chips is provided according to an optional embodiment of the present application, as shown in Figure 5 The experimental results prove that the turn-off voltage rising curves of the chips are inconsistent, and the chips need to be sorted.

[0061] S6: Data storage and analysis. The test data will be stored and transmitted to the data analysis platform, and the voltage rising curves of different chips are statistically analyzed to evaluate their consistency.

[0062] S7: Turn-off voltage rising curve sorting standard. The chips are sorted according to the consistency of the voltage rising curve. For the chips with large differences in the turn-off voltage rising curve, they should be rejected, and the chips with consistent voltage rising curves are selected for parallel connection to realize the balanced distribution of the turn-off current.

[0063] Step three: Chip sorting. Figure 6 A flowchart of chip sorting is provided according to an optional embodiment of the present application, as shown in Figure 6 The specific flow can include:

[0064] S7: Feature matching and sorting rule making. According to the characteristics of the voltage rising curve, the standard for chip sorting is made. The voltage rising curve consistency standard is selected as the voltage rising curve consistency standard for evaluating the switching characteristics of the chips, which is the voltage from 10% of the blocking voltage to 90% of the blocking voltage of the drain-source voltage of the MOSFET.

[0065] S8: Sorting process implementation. The tested silicon carbide MOSFETs are grouped according to the similarity of their voltage rise curves. For chips with consistent voltage rise curves, it is considered that they have similar turn-off characteristics and can be grouped in the same group.

[0066] S9: Confirmation of sorting results. Through further experimental verification, it is ensured that the chips after sorting can minimize the voltage difference and avoid the generation of circulating current and uneven current when used in parallel.

[0067] It should be noted that, for the foregoing method embodiments, in order to simply describe, they are all expressed as a series of action combinations, but those skilled in the art should know that the present application is not limited by the order of the described actions, because according to the present application, certain steps can be performed in other order or simultaneously. Secondly, those skilled in the art should know that the embodiments described in the specification all belong to preferred embodiments, and the actions and modules involved are not necessarily necessary for the present application.

[0068] Through the description of the above embodiments, those skilled in the art can clearly understand that the transistor selection method for balancing current according to the above embodiments can be realized by means of software and the necessary general hardware platform, of course, it can also be realized by hardware, but in many cases the former is a better embodiment. Based on such understanding, the technical solutions of the present application can be embodied in the form of a software product, which is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk), and includes a plurality of instructions for causing a terminal device (which can be a mobile phone, computer, server, or network device, etc.) to execute the method described in each embodiment of the present application.

[0069] According to the embodiments of the present application, a transistor selection system for balancing current is also provided for applying the transistor selection method for balancing current described above, and the system includes a test platform and an analysis platform, which will be described below.

[0070] The test platform is used to obtain a plurality of rise times corresponding to a plurality of transistors respectively, wherein the rise time is the time required for the drain-source voltage of the transistor to rise to a corresponding preset voltage measurement point during the turn-off process.

[0071] Optionally, the test platform is used to evaluate and obtain the dynamic characteristic parameters of the transistor during the turn-off process, especially the key parameter of "rise time". The rise time refers to the time required for the drain-source voltage (Vds) of the transistor to rise to a preset voltage measurement point when the transistor is converted from an on state to an off state.

[0072] The analysis platform is configured to determine a plurality of target transistors based on a plurality of rise times corresponding to the plurality of transistors, wherein the plurality of target transistors are used in the parallel circuit.

[0073] Optionally, the analysis platform is a core component in the system, which uses sophisticated data analysis algorithms to filter a set of "target transistors" from the dynamic characteristic data collected by the test platform, where the "target transistors" meet the preset conditions of the difference coefficient, and is used to construct the parallel circuit. This process ensures the uniform distribution of current in the parallel circuit, avoids uneven current and circulating current phenomena, and thus improves the overall stability and efficiency of the circuit.

[0074] As an optional embodiment, the test platform comprises a signal generator, a test circuit, an oscilloscope, and a calculation module. The signal generator is configured to generate a plurality of single pulse signals, wherein the width and amplitude of each single pulse signal correspond to the working conditions of each transistor. The test circuit is configured to simulate the turn-off process of the plurality of transistors. The oscilloscope is configured to determine the relationship curve between the drain-source voltage and time of the plurality of transistors during the turn-off process. The calculation module is configured to determine a plurality of rise times corresponding to the plurality of transistors based on the relationship curve corresponding to each transistor and a plurality of preset voltage measurement points.

[0075] Optionally, the task of the signal generator is to generate single pulse signals with specific width and amplitude. The parameters (width and amplitude) of these signals are matched with the working conditions of the plurality of transistors to be tested, so as to simulate the turn-off process of the transistors in actual application. The test circuit is used to connect the transistors and the signal generator to simulate the turn-off process of the transistors. In order to ensure the accuracy of the test results, the following points should be paid special attention when designing the test circuit: the circuit layout should be as symmetrical as possible to reduce the parasitic parameter differences caused by the layout, which will affect the consistency of the test; the circuit elements (such as resistors, capacitors, etc.) should be consistent to avoid test errors caused by element differences; the test circuit should be able to withstand the high voltage and transient current generated by the tested transistors during turn-off to ensure the stability and safety of the circuit. The oscilloscope is a high-precision voltage waveform acquisition and display device. In the test platform, the oscilloscope is used to monitor the change of the drain-source voltage (Vds) of the transistors in real time during the turn-off process, and record the voltage waveform changing with time. The calculation module is the data processing center of the test platform, which determines a plurality of rise times corresponding to the plurality of transistors based on the voltage-time relationship curve collected by the oscilloscope and the preset voltage measurement points (for example, the points at which the voltage rises from 10% of the blocking voltage to 90% of the blocking voltage).

[0076] According to the embodiments of the present application, a transistor selection method device for balancing current is also provided, Figure 7This is a structural block diagram of a transistor selection method apparatus for balancing current provided according to an embodiment of the present invention, such as... Figure 7 As shown, the device includes: an acquisition module 71, a traversal module 72, a determination module 73, and a selection module 74. The device will be described below.

[0077] The acquisition module 71 is used to acquire multiple rise times corresponding to multiple transistors and the target number of transistors for parallel circuits, wherein the rise time is the time required for the drain-source voltage of the transistor to rise to the corresponding preset voltage measurement point during the turn-off process.

[0078] The traversal module 72, connected to the acquisition module 71, is used to select a target number of transistors from multiple transistors, traverse all selection combinations, and obtain multiple transistor parallel groups.

[0079] The determination module 73, connected to the traversal module 72, is used to determine the average difference coefficient corresponding to each of the multiple transistor parallel groups based on the multiple rise times corresponding to each of the multiple transistors. The average difference coefficient represents the average degree of difference in the turn-off characteristics among the multiple transistors in the corresponding transistor parallel group.

[0080] Selection module 74, connected to determination module 73, is used to select multiple transistors in a parallel group of transistors with an average difference coefficient less than a preset threshold as multiple target transistors, wherein the multiple target transistors are used in a parallel circuit.

[0081] It should be noted that the acquisition module 71, traversal module 72, determination module 73, and selection module 74 mentioned above correspond to steps S201 to S204 in the embodiments. Multiple modules implement the same instances and application scenarios as their corresponding steps, but are not limited to the content disclosed in the above embodiments. It should also be noted that the above modules, as part of the device, can run on the computer terminal 10 provided in the embodiments.

[0082] Embodiments of the present invention may provide a computer device. Optionally, in this embodiment, the computer device may be located in at least one of a plurality of network devices in a computer network. The computer device includes a memory and a processor.

[0083] The memory can be configured to store software programs and modules, such as program instructions / modules corresponding to the transistor selection method and device for balancing current in the embodiments of the present application. The processor can execute various functional applications and data processing by running the software programs and modules stored in the memory, i.e., implement the transistor selection method for balancing current as described above. The memory can include a high-speed random access memory, and can further include a non-volatile memory, such as one or more magnetic storage devices, flash memories, or other non-volatile solid-state memories. In some examples, the memory can further include a memory remotely disposed relative to the processor, which can be connected to the computer terminal through a network. Examples of the network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and a combination thereof.

[0084] The processor can call information and applications stored in the memory through the transmission device to execute the following steps:

[0085] Optionally, the processor can further execute program codes of the following steps: obtaining a plurality of rise times corresponding to the plurality of transistors respectively, including: generating a plurality of single pulse signals based on the signal generator, wherein the width and amplitude of each of the plurality of single pulse signals are matched with the working condition corresponding to each of the plurality of transistors respectively; simulating the turn-off process of the plurality of transistors based on the preset test circuit and the plurality of single pulse signals to determine the relationship curve between the drain-source voltage and the time of the plurality of transistors in the turn-off process; and determining a plurality of rise times corresponding to the plurality of transistors respectively based on the relationship curve corresponding to each of the plurality of transistors and a plurality of preset voltage measurement points.

[0086] Optionally, the preset test circuit is a symmetrical circuit, wherein the distance from the drain of each of the plurality of transistors to the positive input point of the symmetrical circuit is the same, and the distance from the source of each of the plurality of transistors to the negative output point of the symmetrical circuit is the same.

[0087] Optionally, the processor can further execute program codes of the following steps: determining an average difference coefficient corresponding to each of the plurality of parallel transistor groups based on the plurality of rise times corresponding to the plurality of transistors respectively, wherein the average difference coefficient represents the average difference degree of the turn-off characteristics between the plurality of transistors in the corresponding parallel transistor group, including: determining a difference coefficient between any two transistors in the plurality of parallel transistor groups based on the plurality of rise times corresponding to the plurality of transistors respectively, wherein the difference coefficient represents the difference degree of the turn-off characteristics between the two transistors; and calculating the average value of the plurality of difference coefficients corresponding to each of the plurality of parallel transistor groups respectively to determine the average difference coefficient corresponding to each of the plurality of parallel transistor groups.

[0088] Optionally, the processor can further execute program codes for determining a difference coefficient between any two transistors in the parallel group of transistors based on the plurality of rise times corresponding to the plurality of transistors, wherein the difference coefficient between the first transistor and the second transistor is determined by calculating a difference between the rise times corresponding to the plurality of preset voltage measurement points of the first transistor and the second transistor, determining an average time difference based on the difference, and determining the difference coefficient between the first transistor and the second transistor according to the average time difference.

[0089] The embodiment of the present application provides a transistor selection method for balancing current. The transistor selection method comprises the following steps: obtaining a plurality of rise times corresponding to a plurality of transistors and a target number of transistors for a parallel circuit, wherein the rise time is a time required for a drain-source voltage of the transistor to rise to a corresponding preset voltage measurement point during a turn-off process; selecting the target number of transistors from the plurality of transistors, and obtaining a plurality of parallel groups of transistors by traversing all selected combinations; determining an average difference coefficient corresponding to each of the plurality of parallel groups of transistors based on the plurality of rise times corresponding to the plurality of transistors, wherein the average difference coefficient represents an average difference degree of turn-off characteristics between the plurality of transistors in the corresponding parallel group of transistors; and selecting the plurality of transistors in a parallel group of transistors with an average difference coefficient less than a preset threshold as a plurality of target transistors, wherein the plurality of target transistors are used for the parallel circuit, so that a combination of transistors with balanced branch currents in parallel is selected, thereby achieving the technical effect of improving system stability and efficiency, and further solving the technical problems of high complexity and poor dynamic response of the current balancing regulation technology for transistors used in the parallel circuit.

[0090] Those skilled in the art can understand that all or part of the steps in the above-mentioned embodiments can be completed by instructing the hardware related to the terminal device through a program, and the program can be stored in a non-volatile storage medium, which can include a flash disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk, etc.

[0091] The embodiment of the present application further provides a non-volatile storage medium. Optionally, in the embodiment, the non-volatile storage medium can be used to save the program codes executed by the transistor selection method for balancing current provided by the above-mentioned embodiments.

[0092] Optionally, in the embodiment, the non-volatile storage medium can be located in any one of the computer terminal in the computer terminal group in the computer network, or in any one of the mobile terminal in the mobile terminal group.

[0093] Optionally, in the embodiment, the non-volatile storage medium is configured to store program code for performing the following steps: obtaining a plurality of rise times respectively corresponding to the plurality of transistors, wherein the rise time is a time required for a drain-source voltage of the transistor to rise to a corresponding preset voltage measurement point during the turn-off process; selecting a target number of transistors from the plurality of transistors, traversing all selected combinations to obtain a plurality of parallel connection groups of the plurality of transistors; determining an average difference coefficient respectively corresponding to each of the plurality of parallel connection groups of the plurality of transistors based on the plurality of rise times respectively corresponding to the plurality of transistors, wherein the average difference coefficient represents an average difference degree of the turn-off characteristics between the plurality of transistors in the corresponding parallel connection group; and taking the plurality of transistors in the parallel connection group with the average difference coefficient less than a preset threshold as a plurality of target transistors, wherein the plurality of target transistors are used for the parallel circuit.

[0094] Optionally, in the embodiment, the non-volatile storage medium is configured to store program code for performing the following steps: obtaining a plurality of rise times respectively corresponding to the plurality of transistors, including: generating a plurality of single pulse signals based on a signal generator, wherein the width and amplitude of each of the plurality of single pulse signals are matched with the working condition of each of the plurality of transistors; simulating the turn-off process of the plurality of transistors based on the preset test circuit and the plurality of single pulse signals to determine a relationship curve between the drain-source voltage and the time of the plurality of transistors during the turn-off process; and determining a plurality of rise times respectively corresponding to the plurality of transistors based on the relationship curve respectively corresponding to the plurality of transistors and a plurality of preset voltage measurement points.

[0095] Optionally, in the embodiment, the non-volatile storage medium is configured to store program code for performing the following steps: the preset test circuit is a symmetric circuit, wherein in the symmetric circuit, the distance from the drain of each of the plurality of transistors to the positive input point of the symmetric circuit is the same, and the distance from the source of each of the plurality of transistors to the negative output point of the symmetric circuit is the same.

[0096] Optionally, in the embodiment, the non-volatile storage medium is configured to store program code for performing the following steps: determining an average difference coefficient respectively corresponding to each of the plurality of parallel connection groups of the plurality of transistors based on the plurality of rise times respectively corresponding to the plurality of transistors, wherein the average difference coefficient represents an average difference degree of the turn-off characteristics between the plurality of transistors in the corresponding parallel connection group, including: determining a difference coefficient between any two transistors in the plurality of parallel connection groups of the plurality of transistors based on the plurality of rise times respectively corresponding to the plurality of transistors, wherein the difference coefficient represents a difference degree of the turn-off characteristics between the two transistors; and calculating an average value of the plurality of difference coefficients respectively corresponding to each of the plurality of parallel connection groups to determine the average difference coefficient respectively corresponding to each of the plurality of parallel connection groups.

[0097] Optionally, in the embodiment, the nonvolatile storage medium is configured to store program code for performing the following steps: determining a difference coefficient between any two transistors in the plurality of parallel transistor groups based on the plurality of rise times corresponding to the plurality of transistors respectively, wherein the step of calculating the difference coefficient between the first transistor and the second transistor is as follows: calculating a difference value between the rise times corresponding to the first transistor and the second transistor at the plurality of preset voltage measurement points respectively; determining an average time difference based on the difference value; and determining the difference coefficient between the first transistor and the second transistor according to the average time difference.

[0098] The embodiment of the present application further provides a computer program product, comprising a computer program, and optionally, when the computer program is executed by a processor, the computer program can realize the following steps: obtaining a plurality of rise times corresponding to a plurality of transistors respectively and a target number of transistors for a parallel circuit, wherein the rise time is a time required for a drain-source voltage of the transistor to rise to a corresponding preset voltage measurement point during the turn-off process; selecting the target number of transistors from the plurality of transistors, traversing all selected combinations to obtain a plurality of parallel transistor groups; determining an average difference coefficient corresponding to each of the plurality of parallel transistor groups based on the plurality of rise times corresponding to the plurality of transistors respectively, wherein the average difference coefficient represents an average difference degree of turn-off characteristics between the plurality of transistors in the corresponding parallel transistor group; and taking the plurality of transistors in the parallel transistor group with the average difference coefficient less than a preset threshold as a plurality of target transistors, wherein the plurality of target transistors are used for the parallel circuit.

[0099] The above-mentioned serial numbers of the embodiments of the present application are only for description, and do not represent the advantages and disadvantages of the embodiments.

[0100] In the above-mentioned embodiments of the present application, the description of each embodiment has its own emphasis, and the parts not described in detail in a certain embodiment can be referred to the related description of other embodiments.

[0101] In several embodiments provided in the present application, it should be understood that the disclosed technical contents can be implemented by other ways. Among them, the above-mentioned device embodiments are only schematic, for example, the division of the units can be a logical function division, and actual implementation can have another division way, for example, a plurality of units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the coupling or direct coupling or communication connection between the displayed or discussed each other can be through some interface, indirect coupling or communication connection between units or modules, which can be electrical or other forms.

[0102] The units described as separate components may or may not be physically separate, and the components displayed as units may or may not be physical units, that is, may be located in one place, or may be distributed to multiple units. Part or all of the units can be selected according to actual needs to achieve the purpose of the embodiment scheme.

[0103] In addition, each functional unit in each embodiment of the present application can be integrated in one processing unit, or each unit can exist physically, or two or more units can be integrated in one unit. The integrated unit can be realized in the form of hardware or in the form of a software functional unit.

[0104] The integrated unit, if realized in the form of a software functional unit and sold or used as an independent product, can be stored in a non-volatile storage medium. Based on this understanding, the technical solutions of the present application, essentially or the part that contributes to the prior art, or all or part of the technical solutions can be embodied in the form of a software product. The computer software product is stored in a storage medium, including a number of instructions to make a computer device (which can be a personal computer, a server or a network device, etc.) execute all or part of the steps of the method described in each embodiment of the present application. The foregoing storage medium includes: a U disk, a read-only memory (ROM, Read-Only Memory), a random access memory (RAM, Random Access Memory), a mobile hard disk, a magnetic disk or an optical disk, and various program code storage media.

[0105] The above is only the preferred embodiment of the present application, it should be noted that for those skilled in the art, without departing from the principles of the present application, can make a number of improvements and refinements, these improvements and refinements should also be considered as the protection scope of the present application.

Claims

1. A transistor selection method for equalizing current, characterized by, The method comprises: obtaining a plurality of rise times corresponding to a plurality of transistors respectively and a target number of transistors for a parallel circuit, wherein the rise time is a time required for a drain-source voltage of a transistor to rise to a corresponding preset voltage measurement point during a turn-off process of the transistor; selecting the target number of transistors from the plurality of transistors, traversing all selected combinations to obtain a plurality of parallel groups of transistors; determining an average difference coefficient corresponding to each of the plurality of parallel groups of transistors based on the plurality of rise times corresponding to the plurality of transistors respectively, wherein the average difference coefficient represents an average difference degree of turn-off characteristics between the plurality of transistors in the corresponding parallel group of transistors; and taking the plurality of transistors in a parallel group of transistors with an average difference coefficient less than a preset threshold as a plurality of target transistors, wherein the plurality of target transistors are used for the parallel circuit.

2. The method of claim 1, wherein, The method of obtaining the plurality of rise times corresponding to the plurality of transistors respectively comprises: generating a plurality of single pulse signals based on a signal generator, wherein the width and amplitude of each of the plurality of single pulse signals are matched with the working conditions of each of the plurality of transistors respectively; simulating a turn-off process of the plurality of transistors based on a preset test circuit and the plurality of single pulse signals to determine a relationship curve between a drain-source voltage and time of the plurality of transistors during the turn-off process; and determining the plurality of rise times corresponding to the plurality of transistors respectively based on the relationship curve corresponding to each of the plurality of transistors and a plurality of preset voltage measurement points.

3. The method of claim 2, wherein, The preset test circuit is a symmetrical circuit, wherein in the symmetrical circuit, the distance from the drain of each of the plurality of transistors to a positive input point of the symmetrical circuit is the same, and the distance from the source of each of the plurality of transistors to a negative output point of the symmetrical circuit is the same.

4. The method of claim 1, wherein, The method of determining the average difference coefficient corresponding to each of the plurality of parallel groups of transistors based on the plurality of rise times corresponding to the plurality of transistors respectively, wherein the average difference coefficient represents an average difference degree of turn-off characteristics between the plurality of transistors in the corresponding parallel group of transistors, comprises: determining a difference coefficient between any two transistors in the plurality of parallel groups of transistors based on the plurality of rise times corresponding to the plurality of transistors respectively, wherein the difference coefficient represents a difference degree of turn-off characteristics between the two transistors; and respectively calculating an average value of the plurality of difference coefficients corresponding to each of the plurality of parallel groups of transistors to determine the average difference coefficient corresponding to each of the plurality of parallel groups of transistors.

5. The method of claim 4, wherein, The method of determining the difference coefficient between any two transistors in the plurality of parallel groups of transistors based on the plurality of rise times corresponding to the plurality of transistors respectively, wherein the steps of calculating the difference coefficient between a first transistor and a second transistor are as follows, the first transistor and the second transistor are any two transistors in any one of the plurality of parallel groups of transistors: calculating a difference value between the rise times corresponding to the first transistor and the second transistor at a plurality of preset voltage measurement points respectively; determining an average time difference based on the difference value; and According to the average time difference, a coefficient of variation between the first transistor and the second transistor is determined.

6. A transistor selection system for equalizing current, characterized by, The method according to any one of claims 1 to 5, comprising: a test platform configured to obtain a plurality of rise times respectively corresponding to a plurality of transistors, wherein the rise time is a time required for a drain-source voltage of the transistor to rise to a preset voltage measurement point during a turn-off process of the transistor; an analysis platform configured to determine a plurality of target transistors based on the plurality of rise times respectively corresponding to the plurality of transistors, wherein the plurality of target transistors are used in a parallel circuit.

7. The system of claim 6, wherein, The test platform comprises a signal generator, a test circuit, an oscilloscope, and a calculation module, wherein the signal generator is configured to generate a plurality of single pulse signals, wherein a width and an amplitude of each of the plurality of single pulse signals are matched with a working condition of each of the plurality of transistors; the test circuit is configured to simulate the turn-off process of the plurality of transistors; the oscilloscope is configured to determine a relationship curve between a drain-source voltage and a time during the turn-off process of the plurality of transistors; and the calculation module is configured to determine a plurality of rise times respectively corresponding to the plurality of transistors based on the relationship curve of each of the plurality of transistors and a plurality of preset voltage measurement points.

8. A transistor selection device for equalizing current, characterized by comprising: an obtaining module configured to obtain a plurality of rise times respectively corresponding to a plurality of transistors and a target number of transistors used in a parallel circuit, wherein the rise time is a time required for a drain-source voltage of the transistor to rise to a preset voltage measurement point during a turn-off process of the transistor; a traversing module configured to select the target number of transistors from the plurality of transistors, traverse all selected combinations, and obtain a plurality of parallel groups of transistors; a determining module configured to determine an average coefficient of variation respectively corresponding to the plurality of parallel groups of transistors based on the plurality of rise times respectively corresponding to the plurality of transistors, wherein the average coefficient of variation represents an average difference degree of turn-off characteristics among the plurality of transistors in the corresponding parallel group of transistors; and a selecting module configured to select the plurality of transistors in a parallel group of transistors with an average coefficient of variation less than a preset threshold as a plurality of target transistors, wherein the plurality of target transistors are used in the parallel circuit.

9. A non-volatile storage medium, comprising: The non-volatile storage medium comprises a stored program, wherein the program controls a device in which the non-volatile storage medium is located to execute the transistor selection method for balancing current according to any one of claims 1 to 5 when the program is running.

10. A computer device, comprising: comprising: a memory and a processor, the memory stores a computer program; the processor is configured to execute the computer program stored in the memory, and the computer program causes the processor to execute the transistor selection method for balancing current according to any one of claims 1 to 5 when the computer program is running.

11. A computer program product comprising a computer program, characterized in that, The computer program is executed by the processor to implement the transistor selection method for balancing current according to any one of claims 1 to 5.

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