Intermediate layer in chip packaging structure and preparation method thereof

Abstract

The invention discloses an intermediary layer in a chip packaging structure and a preparation method thereof, and the method comprises the following steps: providing the intermediary layer, and etching and preparing a plurality of micro through holes in the intermediary layer; prefabricating a high copper column, providing a carrier wafer, and bonding an intermediate layer on the first surface of the carrier wafer; accurately matching the high-copper columns into the micro-through holes to metalize the micro-through holes, filling gaps between the high-copper columns and the micro-through holes with insulating materials, and solidifying the insulating materials; and de-bonding, removing the carrier wafer, and removing redundant materials on the surface of the intermediate layer by adopting a CMP copper exposing process, so that the end surfaces of the high-copper columns are exposed on the two surfaces of the intermediate layer. According to the manufacturing method, the mode of prefabricating the high copper column is adopted, the technical limitation of the height of the electroplated metal high copper column is avoided, the high copper column with the higher height can be manufactured, the height of the high copper column is larger than 150 micrometers, and the requirements for the high copper column in the fields of the microelectronic manufacturing technology, semiconductor device manufacturing, the electronic packaging technology and the like are met.

Description

Technical Field

[0001] This invention relates to the field of semiconductor packaging technology, and more specifically to an interposer in a chip packaging structure and its preparation method. Background Technology

[0002] As integrated circuit wafer fabrication processes have advanced to the nanometer level, the number of transistors integrated on chips has increased to a higher density, the number of input / output signal (IO) pins has increased, the spacing between IO pins has decreased to less than 100μm, and packaging technology has developed towards higher density.

[0003] Copper pillar bump packaging technology is used to achieve electrical connections between different components. With its unique advantage of fine bump pitch, good thermal conductivity, anti-electromigration performance, quality consistency and reliability, it has become the core technology of advanced chip packaging process and leads the development of chip packaging technology towards high density and ultra-fine pitch.

[0004] Traditional copper pillar manufacturing methods mainly involve electroplating, which involves electroplating a substrate to form the desired high-copper pillar.

[0005] To address the issue of copper pillar height, existing technologies employ laser drilling and chemical plating. This involves laser-drilling / opening holes on the surface of a molded wafer to create circular deep holes or trenches; after pretreatment such as cleaning, copper plating is performed inside the holes or trenches to deposit the required copper pillars.

[0006] Both of these existing technical solutions have some problems.

[0007] While electroplating simplifies the manufacturing process and reduces costs, it limits the height of copper pillars, making it impossible to produce taller pillars (i.e., those >150µm), thus failing to meet the requirements of advanced packaging structures.

[0008] While laser drilling and chemical plating can produce tall copper pillars, the laser drilling process involves ablation of patterns one by one, resulting in low efficiency and high cost. Controlling substrate deformation and molding compound thickness variations is difficult, affecting the quality of the laser-drilled depth and consequently the quality of subsequent copper pillar plating. Furthermore, deep-hole plating also has process limitations. Currently, a commonly used aspect ratio of 10:1 limits the height of mass-produced copper pillars to around 100μm. Therefore, this method of copper pillar fabrication involves numerous steps, difficult quality control, the presence of bubbles, and discontinuities within the plated copper pillars, leading to reliability issues in packaged chips using this process.

[0009] Therefore, how to simplify the manufacturing process and reduce costs while ensuring that the copper pillar height requirements of various packaging structures are met is an important issue currently facing the technology. Summary of the Invention

[0010] To address the aforementioned issues, this invention provides an interposer layer in a chip packaging structure and its fabrication method, which simplifies the process flow and reduces the technical difficulty of TGV / TMV through-hole metallization.

[0011] On one hand, this invention discloses a method for preparing an interposer layer in a chip packaging structure, the method comprising the following steps: S1. Provide an interposer layer, and etch multiple microvias on the interposer layer. The aspect ratio of the microvias is 3:1-5:1, and the depth of the microvias is greater than 150μm. S2. High copper pillars are prefabricated using mechanical and physical methods. The height of the high copper pillars is ±10μm of the depth of the micro-via. S3. Provide a carrier wafer and bond an intermediary layer on the first surface of the carrier wafer; S4. Precisely fit the high copper pillar into the micro-via to metallize the micro-via. Fill the gap between the high copper pillar and the micro-via with insulating material and cure it. S5. Debond and release the carrier wafer. Use CMP copper exposure process to remove excess material from the surface of the interposer, exposing the high copper pillar end faces on both sides of the interposer.

[0012] Preferably, the interlayer is a glass wafer or a ceramic wafer.

[0013] Preferably, the microvia is formed by laser-induced depth etching (LIDE) process; the depth of the microvia is 150μm-300μm and the diameter is 30μm-50μm.

[0014] Preferably, the mechanical and physical method is micromachining or micro-stamping.

[0015] Preferably, the method of filling and curing the insulating material in step S4 is as follows: DAF or PI insulating material is placed on the surface of the interlayer, and the high copper pillar is firmly bonded to the micro-hole by heating, pressurizing and high temperature curing process.

[0016] On the other hand, the present invention also discloses an intermediary layer prepared by the above method, the intermediary layer having a plurality of micro-vias, the micro-vias being filled with pre-fabricated high copper pillars, and the gaps between the high copper pillars and the micro-vias being filled with insulating material.

[0017] Compared with the prior art, the beneficial effects of the present invention are: This invention employs a prefabricated high copper pillar method, which avoids the height limitations of electroplated metal high copper pillars and allows for the production of even taller high copper pillars (greater than 150μm), meeting the needs of microelectronics process technology, semiconductor device manufacturing, and electronic packaging technology for taller copper pillars.

[0018] This invention fixes prefabricated high-copper pillars in the desired positions using a method similar to chip mounting. Compared to chemical plating, this method greatly simplifies the manufacturing process and reduces manufacturing costs. Because the manufacturing process of this invention is simple, it can significantly improve production efficiency and meet the needs of large-scale production.

[0019] In summary, compared with the prior art, the present invention has significant advantages by prefabricating high-precision copper pillars with a height greater than 150μm into micro-through holes and then filling the gaps with insulating material. The entire manufacturing process is simple, low-cost, and highly efficient. Attached Figure Description

[0020] Figure 1 A schematic diagram of an interposer layer with micro-vias; Figure 2 This is a schematic diagram of the carrier wafer structure; Figure 3 A schematic diagram of the bonding intermediary layer and carrier wafer structure; Figure 4 for Figure 3 A structural diagram of a high-copper pillar is provided; Figure 5 for Figure 4 A schematic diagram of a structure in which insulating material is filled into the gap between the medium-high copper pillars and the micro-through holes; Figure 6 This is a schematic diagram of an intermediate layer with tall copper pillars.

[0021] Labeling explanation: 1. Intermediate layer; 2. Microvia; 3. High copper pillar; 4. Carrier wafer; 5. TBF; 6. Insulating material. Detailed Implementation

[0022] The technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments.

[0023] Market demands for miniaturized, low-power, and high-performance devices are driving the development of microelectronic packaging technology. The rapid growth of portable consumer electronics in recent years has placed even greater demands on packaging integration, lightweight design, and low latency. Vertical interconnect is a key technology for achieving high-density 3D interconnects in wafer-level packaging.

[0024] Common vertical interconnect structures include TSV (through silicon via), TGV (through glass via), and TMV (through molding via).

[0025] This invention discloses an interposer layer 1 in a chip packaging structure based on 2.5D / 3D packaging and its fabrication method. The interposer layer 1 is a glass wafer or a ceramic wafer, mainly targeting TGV and TMV structures. A taller copper pillar 3 (height greater than 150μm) is set within the interposer layer 1 to meet the requirements of microelectronics process technology, semiconductor device manufacturing, and electronic packaging technology for taller copper pillars, while simplifying the process flow and reducing costs.

[0026] like Figure 6 As shown, the intermediate layer 1 is provided with multiple micro-holes 2, the micro-holes 2 are filled with prefabricated high copper pillars 3, and the gaps between the high copper pillars 3 and the micro-holes 2 are filled with insulating material 6.

[0027] In this invention, the high-copper pillar 3 refers to a copper pillar with a height exceeding 150 μm. The prefabrication method for the high-copper pillar 3 can be any one of precision mold casting, precision stamping, precision etching, or precision laser processing, or a combination of the aforementioned methods.

[0028] Compared with the prior art, the present invention uses a prefabricated high-precision copper pillar 3 with a height greater than 150μm to be installed into a micro-through hole 2, and then fills the gap with insulating material 6. The whole manufacturing process is simple, low-cost, and highly efficient, and has obvious advantages.

[0029] The preparation method of the aforementioned intermediate layer 1 includes the following steps: S1, providing such Figure 1 The intermediate layer 1 shown is used to etch and prepare multiple micro-vias 2. The aspect ratio of the micro-vias 2 is 3:1-5:1, and the depth of the micro-vias 2 is greater than 150μm.

[0030] The micro-via 2 is formed using a laser-induced depth etching (LIDE) process; the depth of the micro-via 2 is 150μm-300μm, and the diameter is 30μm-50μm. LIDE (laser-induced depth etching) is a novel fundamental processing technology for fabricating glass microstructures. It can process glass quickly, precisely, and without defects, creating structures with a minimum aperture-to-thickness ratio typically of 1:10 or smaller, making it the optimal solution for industrial mass production.

[0031] S2. High copper pillars 3 are prefabricated using mechanical and physical methods. The height of the high copper pillars 3 is ±10μm of the depth of the micro-holes 2.

[0032] The mechanical and physical methods employed are micromachining or micro-stamping, which are mature technologies with simple processes and low costs. The height of the prefabricated high copper pillar 3 is also unrestricted, avoiding the height limitations of electroplated metal copper pillars. This allows for the production of even taller copper pillars, meeting the needs of microelectronics manufacturing, semiconductor device manufacturing, and electronic packaging technologies for taller copper pillars 3.

[0033] S3, providing such as Figure 2 The carrier wafer 4 shown has an intermediate layer 1 temporarily bonded to its first surface using a hot-press bonding process. The structure after bonding is as follows. Figure 3 As shown; the bonding material is TBF5.

[0034] S4. Precisely fit the high-copper pillar 3 into the micro-via 2, thus metallizing the micro-via 2, resulting in a structure as follows: Figure 4 As shown; the gap between the high copper pillar 3 and the micro-hole 2 is filled with insulating material 6 and cured, and the cured structure is as follows. Figure 5 As shown.

[0035] The method of filling and curing the insulating material 6 is as follows: DAF or PI insulating material 6 is set on the surface of the intermediate layer 1, and the high copper pillar 3 is firmly bonded to the micro-hole 2 by heating, pressurizing and high temperature curing process.

[0036] S5. Debonding: Remove the carrier wafer 4 and use CMP (Cellular Metallurgy) to expose excess material on the surface of interposer 1, revealing the high-copper pillar 3 end faces on both sides of interposer 1. CMP is an existing technology and will not be described in detail here. This completes the process as follows: Figure 6 The interlayer shown has tall copper pillars.

[0037] This invention fixes the pre-fabricated high-copper pillars 3 to the desired positions using a method similar to chip mounting. Compared to chemical plating, this method greatly simplifies the manufacturing process and reduces manufacturing costs. Because the manufacturing process of this invention is simple, it can significantly improve production efficiency and meet the needs of large-scale production.

[0038] The above descriptions are merely some embodiments of the present invention. It should be noted that those skilled in the art can make other modifications and improvements without departing from the inventive concept of the present invention, and these all fall within the protection scope of the present invention.

Claims

1. A method for fabricating an interposer layer in a chip packaging structure, characterized in that, The method includes the following steps: S1. Provide an interposer layer, and etch multiple microvias on the interposer layer. The aspect ratio of the microvias is 3:1-5:1, and the depth of the microvias is greater than 150μm. S2. High copper pillars are prefabricated using mechanical and physical methods. The height of the high copper pillars is ±10μm of the depth of the micro-via. S3. Provide a carrier wafer and bond an intermediary layer on the first surface of the carrier wafer; S4. Precisely fit the high copper pillar into the micro-via to metallize the micro-via. Fill the gap between the high copper pillar and the micro-via with insulating material and cure it. S5. Debond and release the carrier wafer. Use CMP copper exposure process to remove excess material from the surface of the interposer, exposing the high copper pillar end faces on both sides of the interposer.

2. The method according to claim 1, characterized in that, The interlayer is a glass wafer or a ceramic wafer.

3. The method according to claim 2, characterized in that, The microvias are formed using a laser-induced depth etching (LIDE) process; the depth of the microvias is 150μm-300μm and the diameter is 30μm-50μm.

4. The method according to claim 3, characterized in that, The mechanical and physical method is micromachining or micro-stamping.

5. The method according to claim 4, characterized in that, The method for filling and curing the insulating material in step S4 is as follows: DAF or PI insulating material is placed on the surface of the interlayer, and the high copper pillar is firmly bonded to the micro-hole by heating, pressurizing and high temperature curing process.

6. An interposer layer in a chip packaging structure, prepared according to the method of any one of claims 1-5, characterized in that, The intermediate layer has multiple micro-vias, which are filled with prefabricated high copper pillars, and the gaps between the high copper pillars and the micro-vias are filled with insulating material.

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