Capacitor, circuit, circuit board, device, and method for manufacturing capacitor

Abstract

A capacitor is provided with: a conductive base material; a first dielectric layer disposed on the substrate; a first conductor disposed on the first dielectric layer and having a layer shape; a second dielectric layer disposed on the first conductor; and a second conductor disposed on the second dielectric layer. The first conductor includes an exposed portion not covered by the second dielectric layer and the second conductor. The substrate is electrically insulated from the first conductor by the first dielectric layer, and the second conductor is electrically insulated from the first conductor by the second dielectric layer. The base material includes a conductive portion electrically connected to the second conductor.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to a capacitor, a circuit, a circuit substrate, an apparatus, and a manufacturing method of a capacitor. BACKGROUND

[0002] Conventionally, a capacitor having a structure in which a plurality of dielectric layers and a plurality of conductive bodies are alternately overlaid is known.

[0003] For example, a capacitor having a metal-insulator-metal-insulator-metal (MIMIM) stack is described in Patent Literature 1. The capacitor is formed in a trench of a substrate. The trench has an end wall and a flange. The trench is configured in a manner having a pillar. A cross section of the pillar has a tripod-like profile. The trench has a filler formed of a stack alternately layered. The stack includes a first electrode, a first auxiliary layer, an additional electrode, an additional auxiliary layer, and a second electrode. The auxiliary layers electrically insulate the electrodes from each other. The electrodes are formed of a conductive material such as doped polysilicon or metal. The substrate is a high-resistance silicon substrate or a low-resistance substrate such as a p-type doped silicon wafer.

[0004] PRIOR ART DOCUMENTS PATENT LITERATURE Patent Literature 1: U.S. Patent No. 8283750 Specification SUMMARY OF INVENTION

[0005] PROBLEMS TO BE SOLVED BY THE INVENTION The present disclosure provides a capacitor having a plurality of dielectric layers and a plurality of conductive bodies and being advantageous from the viewpoint of reducing the size and the substrate constraint.

[0006] MEANS FOR SOLVING THE PROBLEMS The capacitor of the present disclosure includes a substrate having conductivity; a first dielectric layer disposed on the substrate; a first conductive body having a layer shape disposed on the first dielectric layer; a second dielectric layer disposed on the first conductive body; and a second conductive body disposed on the second dielectric layer.

[0007] The first conductive body includes an exposed portion not covered by the second dielectric layer and the second conductive body, the substrate is electrically insulated from the first conductive body by the first dielectric layer, the second conductive body is electrically insulated from the first conductive body by the second dielectric layer, and the substrate includes a conduction portion electrically connected to the second conductive body.

[0008] EFFECTS OF THE INVENTION According to the present disclosure, a capacitor having a plurality of dielectric layers and a plurality of conductive bodies and being advantageous from the viewpoint of reducing the size and the substrate constraint can be provided. BRIEF DESCRIPTION OF DRAWINGS

[0009] Figure 1This is a cross-sectional view showing an example of a capacitor of this disclosure.

[0010] Figure 2A This is a cross-sectional view schematically illustrating an example of a method for manufacturing a capacitor according to the present disclosure.

[0011] Figure 2B This is a flowchart illustrating an example of a method for manufacturing a capacitor according to the present disclosure.

[0012] Figure 3 This is a cross-sectional view showing another example of the capacitor disclosed herein.

[0013] Figure 4 yes Figure 3 A cross-sectional view of a portion of the capacitor shown.

[0014] Figure 5 This is a cross-sectional view showing yet another example of the capacitor of this disclosure.

[0015] Figure 6 This is a cross-sectional view illustrating another example of a method for manufacturing a capacitor according to the present disclosure.

[0016] Figure 7A This is a diagram schematically illustrating an example of a circuit according to the present disclosure.

[0017] Figure 7B This is a schematic diagram illustrating an example of a circuit board according to the present disclosure.

[0018] Figure 7C This is a diagram schematically illustrating an example of the device of this disclosure. Detailed Implementation

[0019] (The insights that form the basis of this disclosure) For example, the dielectric layer in an electrolytic capacitor can be formed by anodizing the valve metal. In this case, the material of the dielectric layer is limited to oxides of the valve metal, making it difficult to increase the relative permittivity of the dielectric layer obtained by anodizing. For example, by using a porous body containing the valve metal, the specific surface area of ​​the capacitor's electrodes can be increased, thereby increasing the capacitor's capacitance. On the other hand, the average pore size of such a porous body is reduced to about 100 nm, making it difficult to further increase the specific surface area of ​​the electrodes.

[0020] The capacitor described in Patent Document 1 uses a high-resistance silicon substrate or a low-resistance substrate such as a p-type doped silicon wafer, which can be understood as equivalent to a so-called silicon capacitor. Silicon capacitors aim to significantly increase the electrode surface area and thus increase capacitance by applying a three-dimensional process using metal-oxide-semiconductor (MOS) semiconductor technology. Therefore, the capacitor described in Patent Document 1 can be understood to have limitations regarding size and substrate.

[0021] Accordingly, the inventors of the present application have repeatedly and intensively studied the structure of a capacitor having a plurality of dielectric layers and a plurality of conductors and having less constraints on the size and the substrate. As a result, the inventors of the present application have newly found that a capacitor having less constraints on the size and the substrate can be configured by having a prescribed relationship between the substrate having conductivity, the dielectric, and the conductor, and have conceived the capacitor of the present disclosure.

[0022] (Embodiment) Hereinafter, an embodiment of the present disclosure will be described with reference to the drawings. The present disclosure is not limited to the following embodiment.

[0023] Figure 1 is a cross-sectional view showing one example of the capacitor of the present disclosure. As shown in Figure 1 , the capacitor la has a substrate 10 having conductivity, a first dielectric layer 21, a first conductor 31, a second dielectric layer 22, and a second conductor 32. The first dielectric layer 21 is disposed on the substrate 10. The first conductor 31 is disposed on the first dielectric layer 21 and has a layer shape. The second dielectric layer 22 is disposed on the first conductor 31. The second conductor 32 is disposed on the second dielectric layer 22. The first conductor 31 includes an exposed portion 31e that is not covered by the second dielectric layer 22 and the second conductor 32. The substrate 10 is electrically insulated from the first conductor 31 by the first dielectric layer 21. The second conductor 32 is electrically insulated from the first conductor 31 by the second dielectric layer 22. Furthermore, the substrate 10 includes a conduction portion 10c that is electrically connected to the second conductor 32. According to such a configuration, in the capacitor la, a portion including the first dielectric layer 21 and a portion including the second dielectric layer 22 can be electrically connected in parallel, and thus the capacitor la is likely to have a high capacitance. Furthermore, the substrate 10 is not limited to a specific substrate as long as it has conductivity, and constraints on the substrate are less in the capacitor la. In addition, the capacitor la can be manufactured by a process other than a MOS process of a semiconductor, and constraints on the size of the capacitor la are also less, and for example, the capacitor la can be provided as a capacitor having a larger size than a silicon capacitor.

[0024] The electrical connection of the conduction portion 10c to the second conductor 32 is not limited to a specific form. As shown in Figure 1 , the conduction portion 10c may, for example, be in contact with the second conductor 32. According to such a configuration, the structure of the capacitor la is likely to be simple. The conduction portion 10c can be configured in a form different from a portion other than the conduction portion 10c in the substrate 10. For example, the conduction portion 10c can be configured by a conductive coating layer formed on the surface of the main body of the substrate 10. The conduction portion 10c can be electrically connected to the second conductor 32 in a state where another conductive member is disposed between the conduction portion 10c and the second conductor 32. In this case, for example, the conduction portion 10c is protected by the other conductive member, and the capacitor la is likely to have high durability.

[0025] Figure 1 A cross-sectional view of capacitor 1a with a three-dimensional shape is shown, as follows. Figure 1 As shown, the conductive portion 10c can also be surrounded by the second conductor 32, for example. With this configuration, the electrical connection between the conductive portion 10c and the second conductor 32 is less prone to failure, and the capacitor 1a can easily achieve high reliability. The conductive portion 10c is, for example, constructed with a cylindrical surface, and the second conductor 32 is formed to surround this cylindrical surface. For example, the portion of the second conductor 32 disposed on the second dielectric layer 22 and the portion surrounding the conductive portion 10c are integrally formed. The second conductor 32 is, for example, formed as a cylinder with an annular bottom, and the annular bottom surrounds the conductive portion 10c. The second conductor 32 is, for example, cylindrical.

[0026] like Figure 1 As shown, capacitor 1a further includes, for example, a first terminal 41 and a second terminal 42. The first terminal 41 is electrically connected to the substrate 10 or the second conductor 32. In capacitor 1a, the first terminal 41 is electrically connected to, for example, the substrate 10 or the second conductor 32. The first terminal 41 is electrically connected to the substrate 10 and, through the substrate 10, is also electrically connected to the second conductor 32. The second terminal 42 is electrically connected to the first conductor 31. The potential of the substrate 10 or the second conductor 32, and the potential of the first conductor 31, are adjusted via the first terminal 41 and the second terminal 42.

[0027] In capacitor 1a, for example, the anode includes a first terminal 41 and the cathode includes a second terminal 42. Alternatively, in capacitor 1a, the anode may include a second terminal 42 and the cathode may include a first terminal 41.

[0028] The electrical connection between the first terminal 41 and the substrate 10 or the second conductor 32 is not limited to a specific form. The first terminal 41 may include, for example, a lead, one end of which is fixed to the substrate 10 or the second conductor 32.

[0029] The electrical connection between the second terminal 42 and the first conductor 31 is not limited to a specific form. For example, the first conductor 31 can be electrically connected to the second terminal 42 via a conductive adhesive portion 35. With this configuration, the first conductor 31 can be protected by the conductive adhesive portion 35, and the capacitor 1a can easily have high durability.

[0030] like Figure 1 As shown, the conductive adhesive portion 35 contacts, for example, the exposed portion 31e. The second terminal 42 includes, for example, a lead, one end of which is fixed by the conductive adhesive portion 35.

[0031] The conductive adhesive portion 35 only needs to possess conductivity and adhesion, and is not limited to a specific configuration. The conductive adhesive portion 35 may contain, for example, silver or a conductive polymer. With this configuration, in the manufacture of capacitor 1a, when electrically connecting the second terminal 42 to the first conductor 31, high-temperature processing is less likely, and the yield of capacitor 1a is easily increased. Furthermore, the electrical connection between the second terminal 42 and the first conductor 31 is less prone to defects, and capacitor 1a tends to have high reliability. When the conductive adhesive portion 35 contains silver, it may, for example, comprise an adhesive containing resin and silver particles dispersed within the conductive adhesive portion 35.

[0032] like Figure 1 As shown, capacitor 1a also includes a housing 50. Inside the housing 50 are a substrate 10, a first dielectric layer 21, a first conductor 31, a second dielectric layer 22, a second conductor 32, and a conductive adhesive portion 35. The housing 50 is made of a dielectric material such as resin. For example, the housing 50 has an internal partition that electrically insulates the second conductor 32 from the conductive adhesive portion 35. A portion of the first terminal 41 and a portion of the second terminal 42 are led out to the outside of the housing 50.

[0033] like Figure 1 As shown, capacitor 1a has a MIMIM structure composed of a substrate 10, a first dielectric layer 21, a first conductor 31, a second dielectric layer 22, and a second conductor 32. Figure 1 The example shown is of a single MIMIM structure housed within the housing 50, but it is not limited to this example. Multiple MIMIM structures stacked on top of each other can also be housed within the housing 50.

[0034] The material of the substrate 10 is only required to be conductive and is not limited to a specific material. The substrate 10 may, for example, contain a metal or a semiconductor whose conductivity has been improved by including dopants. The substrate 10 preferably has high conductivity. From the viewpoint of high conductivity, the substrate 10 preferably contains a metal. The metal may also be a valve metal. In this case, the first dielectric layer 21 can be formed by anodizing. Examples of valve metals include Al, Ta, Ti, Hf, Zr, Si, and Nb.

[0035] The substrate 10 can be in sheet or column form.

[0036] The thickness of the first dielectric layer 21 is not limited to a particular value. The thickness is, for example, 5 nm or more. Thereby, the leakage current is suppressed, and the capacitor 1a is easily provided with a desired withstand voltage. The thickness of the first dielectric layer 21 is, for example, 500 nm or less. Thereby, the capacitor 1a is more easily provided with a high capacitance. The thickness of the first dielectric layer 21 can be 10 nm or more, or 400 nm or less, 300 nm or less, 200 nm or less, 100 nm or less, 50 nm or less, or 20 nm or less.

[0037] The material of the first dielectric layer 21 is not limited to a particular material. The first dielectric layer 21 contains, for example, an oxide. In this case, the oxide contains at least one selected from hafnium, zirconium, aluminum, tantalum, titanium, silicon, zinc, and niobium. Examples of the oxide are HfO2, ZrO2, Hf 1-x Zr x O2, Al2O3, Ta2O5, TiO2, SiO2, ZnO, and Nb2O5. The first dielectric layer 21 containing such an oxide can be formed, for example, by anodic oxidation of a valve metal. Thus, the first dielectric layer 21 can also be an anodized film. The oxide preferably contains at least one selected from Al2O3and Ta2O5. In this case, the capacitor 1a is easily provided with a high withstand voltage.

[0038] The first dielectric layer 21 can also contain an inorganic compound. In this case, the inorganic compound contains, for example, at least one selected from an oxide, a nitride, and an oxynitride. The inorganic compound contains, for example, at least one selected from hafnium, zirconium, aluminum, tantalum, titanium, silicon, zinc, and niobium.

[0039] The first dielectric layer 21 can be an oxide film other than an anodized film, or can be an evaporation film. In the present specification, evaporation as described in Japanese Industrial Standard JIS H0211-1992 can include physical evaporation and chemical evaporation. The evaporation film can be formed, for example, by a vapor phase method such as chemical evaporation. In this case, the first dielectric layer 21 contains at least one selected from an oxide, a nitride, and an oxynitride. Examples of the oxide are HfO2, ZrO2, Hf 1-x Zr x O2, Al2O3, Ta2O5, TiO2, SiO2, ZnO, Nb2O5. Examples of the nitride include HfN, ZrN, Hf 1-x Zr x N, AlN, and SiN. Examples of the oxynitride are HfON, ZrON, HfZrON, AlON, and SiON.

[0040] The thickness of the first conductor 31 is not limited to a specific value. For example, its thickness can be 20 nm or more. This makes it easier to reduce the resistance of the first conductor 31. For example, the thickness of the first conductor 31 can be 500 nm or less. This makes it easier to increase the capacitance density per unit volume of the capacitor 1a. The thickness of the first conductor 31 can be 30 nm or more, 40 nm or more, or 50 nm or more, or it can be 400 nm or less, 300 nm or less, 200 nm or less, or 100 nm or less.

[0041] The material of the first conductor 31 is not limited to a specific material. For example, the first conductor 31 includes at least one selected from Ti, W, Mo, Co, Ru, CoSi2, NiSi, TiN, TaN, indium tin oxide (ITO), ZnO, indium gallium zinc oxide (IGZO), WO3, and TiAlN.

[0042] The method for forming the first conductor 31 is not limited to a specific method. The first conductor 31 can be, for example, a vapor-deposited film. The first conductor 31 can be formed, for example, by a vapor-phase method such as chemical vapor deposition. In this case, the first conductor 31 readily covers the desired location of the first dielectric layer 21. The first conductor 31 is preferably formed by atomic layer deposition (ALD). In this case, the first conductor 31 more easily covers the desired location of the first dielectric layer 21, and the first conductor 31 readily becomes a uniform layer. The first conductor 31 can also be formed by physical vapor deposition such as sputtering.

[0043] like Figure 1 As shown, the first dielectric layer 21 and the first conductor 31 are disposed, for example, on a plurality of intersecting surfaces of the substrate 10.

[0044] The thickness of the second dielectric layer 22 is not limited to a specific value. For example, its thickness is 5 nm or more. This suppresses leakage current, and capacitor 1a easily possesses the desired voltage withstand capability. For example, the thickness of the second dielectric layer 22 is 500 nm or less. This makes it easier for capacitor 1a to have high capacitance. The thickness of the second dielectric layer 22 can be 10 nm or more, or it can be 400 nm or less, 300 nm or less, 200 nm or less, or 100 nm or less.

[0045] The material of the second dielectric layer 22 is not limited to a specific material. The second dielectric layer 22 may, for example, contain an inorganic compound. The inorganic compound may, for example, contain at least one selected from oxides, nitrides, and oxynitrides. Furthermore, the inorganic compound may, for example, contain at least one selected from hafnium, zirconium, aluminum, tantalum, titanium, silicon, niobium, and zinc. When the inorganic compound contained in the second dielectric layer 22 contains an oxide, the oxide may contain at least one selected from hafnium, zirconium, aluminum, tantalum, titanium, silicon, niobium, and zinc. Examples of oxides are HfO2, ZrO2, and Hf... 1-x Zrx O2, Al2O3, Ta2O5, TiO2, SiO2, Nb2O5, and ZnO. Examples of nitrides include HfN, ZrN, Hf 1-x Zr x N, AlN, and SiN. Examples of oxynitrides are HfON, ZrON, HfZrON, AlON, and SiON.

[0046] The method of forming the second dielectric layer 22 is not limited to a particular method. The second dielectric layer 22 is, for example, an evaporation film. The second dielectric layer 22 is formed by a vapor phase method such as chemical vapor deposition, for example. In this case, the second dielectric layer 22 easily covers the desired portion of the first conductor 31. The second dielectric layer 22 is preferably formed by ALD. In this case, the second dielectric layer 22 more easily covers the desired portion of the first conductor 31, and the second dielectric layer 22 easily becomes uniform. The second dielectric layer 22 can also be formed by physical evaporation such as sputtering.

[0047] The material of the second conductor 32 is not limited to a particular material. The second conductor 32 contains, for example, at least one selected from the group consisting of conductive polymers, electrolytes, manganese oxides, Ti, W, Mo, Co, Ru, CoSi2, NiSi, TiN, TaN, ITO, ZnO, IGZO, WO3, and TiAlN.

[0048] The second conductor 32 preferably contains a conductive polymer. In this case, the second conductor 32 easily functions as a self-repairing function, and the capacitor la easily has high reliability. Examples of conductive polymers are polyaniline and polypyrrole.

[0049] Figure 2A is a cross-sectional view schematically showing one example of a manufacturing method of a capacitor of the present disclosure. Figure 2B is a flowchart showing one example of a manufacturing method of a capacitor of the present disclosure. As shown in Figure 2A and Figure 2B As shown in (i) to (vi) below, for example, the manufacturing method of the capacitor la contains (i) to (vi). According to such a method, the substrate 10 is less restricted, and the size of the capacitor la that can be manufactured is also less restricted.

[0050] (i) Forming the first dielectric layer 21 on the substrate 10 having conductivity.

[0051] (ii) Forming a layer from the first conductor 31 on the first dielectric layer 21.

[0052] (iii) Forming the second dielectric layer 22 on the first conductor 31.

[0053] (iv) Forming the second conductor 32 on the second dielectric layer 22.

[0054] (v) A portion of the surface of the first conductor 31 is exposed to obtain a first exposed portion E1.

[0055] (vi) By exposing a portion of the surface of the substrate 10 to obtain a second exposed portion E2, the substrate 10 is electrically connected to the second conductor 32.

[0056] like Figure 2A as well as Figure 2B As shown, the manufacturing method of capacitor 1a may also include, for example, the following (ia) to (iva). According to such a method, the layers can be arranged at the desired locations using masks M1 and M2.

[0057] (ia) When a first mask M1 is disposed on a portion of the surface of the substrate 10, namely the first part P1, a first dielectric layer 21 is formed on the substrate 10 and the first mask M1, and a first conductor 31 is formed on the first dielectric layer 21.

[0058] (iia) A portion of the first dielectric layer 21 formed on the first mask M1, namely the second part P2, and a portion of the first conductor 31 disposed on the second part P2, namely the third part P3, are removed together with the first mask M1.

[0059] (iiia) After removing the first mask M1, with the second mask M2 in place, a second dielectric layer 22 is formed on the second mask M2, the substrate 10, and the first conductor 31. The second mask M2 is disposed on a portion of the first portion P1, namely the fourth portion P4, and a portion of the surface of the first conductor 31, namely the fifth portion P5.

[0060] (iva) A portion of the second dielectric layer 22 formed on the second mask M2, namely the sixth part P6, is removed together with the second mask M2 to obtain the first exposed part E1 and the second exposed part E2.

[0061] like Figure 2B As shown, for example, in step S101, a first mask M1 is disposed at a first portion P1 of the substrate 10. The first portion P1 is, for example, the surface of one end of the substrate 10. Next, in step S102, a first dielectric layer 21 and a first conductor 31 are formed. The formation of the first dielectric layer 21 can be performed, for example, by anodizing, or by vapor phase methods such as ALD, chemical vapor deposition (CVD), atomized CVD, and sputtering. The formation of the first conductor 31 can be performed, for example, by vapor phase methods such as ALD, chemical vapor deposition (CVD), atomized CVD, and sputtering.

[0062] Next, in step S103, the second region P2 and the third region P3 are removed together with the first mask Ml. Next, in step S104, the second mask M2 is disposed on a fourth region P4 and a fifth region P5. The fourth region P4 is a part of the first region PI, for example, a surface of an end portion of the substrate 10. The fifth region P5 is a part of a surface of the first conductor 31, for example, a surface of an end portion of the first conductor 31 located in the vicinity of an end portion on the side opposite to the fourth region P4 of the substrate 10.

[0063] Next, in step S105, the second dielectric layer 22 is formed. The formation of the second dielectric layer 22 can be performed, for example, by a vapor phase method such as ALD, CVD, atomization CVD, and sputtering.

[0064] Next, in step S106, the sixth region P6 is removed together with the second mask M2, to obtain a first exposed portion El and a second exposed portion E2.

[0065] Next, in step S107, the second terminal 42 is electrically connected to the first conductor 31. For example, a conductive adhesive is supplied so as to be in contact with the first exposed portion El, and a conductive adhesive portion 35 is formed by curing of the conductive adhesive. The second terminal 42 is fixed by the conductive adhesive portion 35.

[0066] Next, in step S108, a protective material 50r is formed so as to surround the first exposed portion El and the conductive adhesive portion 35. Next, in step S109, the second conductor 32 is formed. The second conductor 32 is formed so as to be in contact with the second exposed portion E2. In addition, the second conductor 32 is formed so as not to be in contact with the first exposed portion El. Thus, the second conductor 32 is electrically insulated from the first conductor 31. The formation of the second conductor 32 can be performed by electrolytic polymerization, or by a vapor phase method such as ALD, CVD, atomization CVD, and sputtering.

[0067] Next, in step S110, the first terminal 41 is electrically connected to the substrate 10. For example, the first terminal 41 is mounted so that one end thereof is in contact with the substrate 10.

[0068] Next, in step S111, the case 50 is formed by a mold. At this time, a part of the first terminal 41 and the second terminal 42 is led to the outside of the case 50.

[0069] Figure 3 is a cross-sectional view showing another example of the capacitor of the present disclosure. Figure 3The capacitor 1b is configured similarly to the capacitor 1a except for the portions specifically described. The same reference numerals are assigned to the constituent elements of the capacitor 1b that are the same as or correspond to the constituent elements of the capacitor 1a, and detailed description is omitted. The description of the capacitor 1a is also applicable to the capacitor 1b as far as technically not contradictory.

[0070] As Figure 3 shown in the capacitor 1b, the base material 10 includes the porous portion 11. The first dielectric layer 21 is disposed on the porous portion 11. According to such a configuration, the area of the electrode is easily made large in the capacitor 1b, and the capacitor 1b is more likely to have a high capacitance.

[0071] Figure 4 is Figure 3 a cross-sectional view of a part of the capacitor. Figure 4 is a cross-sectional view of the porous portion 11 and the peripheral portion of the porous portion 11 in the capacitor 1b in contact with the first dielectric layer 21. As Figure 4 shown, the first dielectric layer 21, the first conductive body 31, and the second dielectric layer 22 are formed so as to cover the wall surface of the porous portion 11. The pores in the porous portion 11 can extend straight without branching, or can extend branching. The porous portion 11 can have a structure such as a groove shape, a sponge shape, a lattice shape, and a tunnel shape.

[0072] The porous portion 11 includes, for example, a valve metal. In this case, for example, in the porous portion 11, the first dielectric layer 21 can be formed by anodic oxidation.

[0073] The valve metal included in the porous portion 11 can be aluminum. In this case, the porous portion 11 can be formed by electrolytic etching of, for example, an aluminum foil. Thus, the area of the electrode is more easily made large in the capacitor 1b, and the capacitor 1b is more likely to have a high capacitance.

[0074] The porous portion 11 can include a metal sintered body. In this case, the area of the electrode is more easily made large in the capacitor 1b, and the capacitor 1b is more likely to have a high capacitance.

[0075] The metal sintered body includes, for example, tantalum. In this case, the area of the electrode is more easily made large in the capacitor 1b, and the capacitor 1b is more likely to have a high capacitance.

[0076] As Figure 3 shown, the through portion 10c can also be formed of the porous portion 11. In this case, for example, when the through portion 10c is in contact with the second conductive body 32, the second conductive body 32 can exist inside the porous portion 11. Thus, the electrical connection of the through portion 10c and the second conductive body 32 is less likely to be defective. The through portion 10c can also be formed of a non-porous portion of the base material 10.

[0077] As Figure 3 illustrated, the base material 10 has a dense portion 12. The dense portion 12 is a non-porous portion. The dense portion 12, for example, constitutes a core of the base material 10. In the capacitor lb, for example, the porous portion 11 is formed around the dense portion 12.

[0078] Figure 5 is a cross-sectional view illustrating still another example of the capacitor of the present disclosure. Figure 5 The capacitor lc illustrated is constituted similarly to the capacitor la except for portions specifically described. The same reference numerals are assigned to the constituent elements of the capacitor lc that are the same as or correspond to the constituent elements of the capacitor la, and detailed description is omitted. The description regarding the capacitor la is also applicable to the capacitor lc as long as there is no technical inconsistency.

[0079] As Figure 5 illustrated, in the capacitor lc, the first terminal 41 is electrically connected to the second electrically conductive body 32. Further, the first terminal 41 is electrically connected to the base material 10 through the second electrically conductive body 32.

[0080] Figure 6 is a cross-sectional view illustrating another example of the manufacturing method of the capacitor of the present disclosure. Figure 6 An example of the manufacturing method of the capacitor lc is illustrated. As Figure 6 illustrated, first, the first dielectric layer 21 is formed on the base material 10. The formation of the first dielectric layer 21 can be performed by anodization, or can be performed by a vapor phase method such as ALD, CVD, atomization CVD, and sputtering.

[0081] Next, the first electrically conductive body 31 is formed on the first dielectric layer 21. The formation of the first electrically conductive body 31 is performed, for example, by a vapor phase method such as ALD, CVD, atomization CVD, and sputtering. Before the formation of the first electrically conductive body 31, a mask Ml is disposed at the end portion of the base material 10. This mask Ml is removed after the formation of the first electrically conductive body 31 together with a portion of the first electrically conductive body 31 deposited on the mask Ml.

[0082] Next, the second dielectric layer 22 is formed on the first electrically conductive body 31 and the first dielectric layer 21. The formation of the second dielectric layer 22 is performed, for example, by a vapor phase method such as ALD, CVD, atomization CVD, and sputtering. Before the formation of the second dielectric layer 22, a mask M2 is disposed at the end portion of the first electrically conductive body 31 on the side opposite to the end portion on which the mask Ml is disposed. The mask M2 is removed after the formation of the second dielectric layer 22 together with the second dielectric layer 22 deposited on the mask M2. Thereby, the exposed portion 31e is obtained.

[0083] Next, a portion of the first dielectric layer 21 and the second dielectric layer 22 on the end portion of the substrate 10 provided with the mask M1 is removed by etching, laser processing, or cutting, or the like. Thus, a through portion 10c is formed.

[0084] Next, a second conductor 32 is formed on the through portion 10c and the second dielectric layer 22. Thus, the through portion 10c of the substrate 10 is electrically connected to the second conductor 32. The second conductor 32 is formed so as not to contact the exposed portion 31e, and is electrically insulated from the first conductor 31. The second conductor 32 can be formed by electrolytic polymerization, or can be formed by a vapor phase method such as ALD, CVD, atomization CVD, or sputtering. The second conductor 32 is connected to the first terminal 41.

[0085] Next, a conductive adhesive portion 35 is formed on the exposed portion 31e. The conductive adhesive portion 35 is formed so as not to contact the second conductor 32, and is electrically insulated from the second conductor 32. Next, the conductive adhesive portion 35 is connected to the second terminal 42. Finally, a case 50 is formed by a mold. At this time, a portion of the first terminal 41 and the second terminal 42 is drawn out to the outside of the case 50.

[0086] Figure 7A is a view schematically illustrating one example of a circuit of the present disclosure. As Figure 7A indicated, the circuit 3 includes the capacitor la. The circuit 3 can be an active circuit, or can be a passive circuit. The circuit 3 can be a discharge circuit, or can be a smoothing circuit, or can be a decoupling circuit, or can be a coupling circuit. Since the circuit 3 includes the capacitor la, the circuit 3 is likely to exhibit desired performance. For example, noise is likely to be reduced in the circuit 3. The circuit 3 can include the capacitor lb or lc.

[0087] Figure 7B is a view schematically illustrating one example of a circuit substrate of the present disclosure. As Figure 7B indicated, the circuit substrate 5 includes the capacitor la. For example, in the circuit substrate 5, the circuit 3 including the capacitor la is formed. Since the circuit substrate 5 includes the capacitor la, the circuit substrate 5 is likely to exhibit desired performance. The circuit substrate 5 can be an embedded board, or can be a mother board. The circuit substrate 5 can include the capacitor lb or lc.

[0088] Figure 7C is a view schematically illustrating one example of an apparatus of the present disclosure. As Figure 7CAs shown, the device 7 includes the capacitor 1a. The device 7 has, for example, a circuit board 5 including the capacitor 1a. The device 7 has the capacitor 1a, and thus the device 7 easily exhibits desired performance. The device 7 can be an electronic device, a communication device, a signal processing apparatus, or a power supply apparatus. The device 7 can be a server, an AC adapter, an accelerator, a liquid crystal display apparatus (LCD), or the like. The device 7 can be a USB charger, a solid state drive (SSD), a PC, a smartphone, a tablet PC, or the like. The device 7 can include the capacitor 1b or 1c.

[0089] (Addendum) According to the above description, the following technology is disclosed.

[0090] (Technology 1) A capacitor includes: a base material having electrical conductivity; a first dielectric layer disposed on the base material; a first conductive body having a layer shape and disposed on the first dielectric layer; a second dielectric layer disposed on the first conductive body; and a second conductive body disposed on the second dielectric layer, wherein the first conductive body includes an exposed portion that is not covered by the second dielectric layer and the second conductive body, the base material is electrically insulated from the first conductive body by the first dielectric layer, the second conductive body is electrically insulated from the first conductive body by the second dielectric layer, the base material includes a conduction portion that is electrically connected to the second conductive body.

[0091] (Technology 2) The capacitor according to Technology 1, wherein the conduction portion is in contact with the second conductive body.

[0092] (Technology 3) The capacitor according to Technology 1 or 2, wherein the conduction portion is surrounded by the second conductive body.

[0093] (Technology 4) The capacitor according to any one of Technologies 1 to 3, wherein the base material includes a porous portion, and the first dielectric layer is disposed on the porous portion.

[0094] (Technology 5) The capacitor according to Technology 4, wherein the porous portion includes a valve metal.

[0095] (Technology 6) The capacitor according to Technology 5, wherein the valve metal is aluminum.

[0096] (Technique 7) The capacitor according to Technique 4, wherein the porous portion contains a metal sintered body.

[0097] (Technique 8) The capacitor according to Technique 7, wherein the metal sintered body contains tantalum.

[0098] (Technique 9) The capacitor according to any one of Techniques 1 to 8, further comprising: a first terminal electrically connected to the base material or the second conductive body; and a second terminal electrically connected to the first conductive body.

[0099] (Technique 10) The capacitor according to Technique 9, further comprising a conductive adhesive portion containing silver or a conductive high molecule, the first conductive body being electrically connected to the second terminal through the conductive adhesive portion.

[0100] (Technique 11) The capacitor according to any one of Techniques 1 to 10, wherein at least one selected from the first dielectric layer and the second dielectric layer contains an inorganic compound containing at least one selected from oxides, nitrides, and oxynitrides, the oxides containing at least one selected from hafnium, zirconium, aluminum, tantalum, titanium, silicon, zinc, and niobium.

[0101] (Technique 12) The capacitor according to any one of Techniques 1 to 11, wherein the first conductive body contains at least one selected from Ti, W, Mo, Co, Ru, CoSi2, NiSi, TiN, TaN, indium tin oxide (ITO), ZnO, indium gallium zinc oxide (IGZO), WO3, and TiAlN.

[0102] (Technique 13) The capacitor according to any one of Techniques 1 to 12, wherein the second conductive body contains at least one selected from conductive high molecules, electrolytes, manganese oxides, Ti, W, Mo, Co, Ru, CoSi2, NiSi, TiN, TaN, indium tin oxide (ITO), ZnO, indium gallium zinc oxide (IGZO), WO3, and TiAlN.

[0103] (Technique 14) A circuit comprising the capacitor according to any one of Techniques 1 to 13.

[0104] (Technique 15) A circuit substrate comprising the capacitor according to any one of Techniques 1 to 13.

[0105] (Technique 16) An apparatus provided with the capacitor described in any one of Technical 1 to 13.

[0106] (Technical 17) A method for manufacturing a capacitor, comprising steps of: forming a first dielectric layer on a substrate having conductivity; forming a layer from a first conductive body on the first dielectric layer; forming a second dielectric layer on the first conductive body; forming a second conductive body on the second dielectric layer; exposing a part of a surface of the first conductive body to obtain a first exposed portion; and electrically connecting the substrate and the second conductive body through a second exposed portion obtained by exposing a part of a surface of the substrate.

[0107] (Technical 18) The method for manufacturing a capacitor according to Technical 17, wherein in the step of forming the first dielectric layer and the step of forming the layer from the first conductive body, the first dielectric layer is formed on the substrate and a first mask in a state where the first mask is arranged on a part of the surface of the substrate, i.e., a first portion, and the layer is formed from the first conductive body on the first dielectric layer, further comprising a step of removing a part of the first dielectric layer formed on the first mask, i.e., a second portion, and a part of the first conductive body arranged on the second portion, i.e., a third portion, together with the first mask, in the step of forming the second dielectric layer, the second dielectric layer is formed on the second mask, the substrate, and the first conductive body in a state where a second mask is arranged on a part of the first portion, i.e., a fourth portion, and a part of the surface of the first conductive body, i.e., a fifth portion, after the first mask is removed, in the step of obtaining the first exposed portion and the step of electrically connecting the substrate and the second conductive body, a part of the second dielectric layer formed on the second mask, i.e., a sixth portion, is removed together with the second mask to obtain the first exposed portion and the second exposed portion.

[0108] Embodiment Hereinafter, the present disclosure will be described in further detail by embodiments. Note that the following embodiments are illustrative, and the present disclosure is not limited to the following embodiments.

[0109] <Embodiment 1> An Al foil having a thickness of 120 μm was prepared as a conductive substrate. An Al2O3 film was formed on the surface of the Al foil by anodization to obtain a first dielectric layer. In the anodization, the Al foil was used as an anode while being immersed in a 0.3 mol / L aqueous diammonium adipate solution, and a voltage of 7 V was applied. The thickness of the Al2O3 film was 10 nm. Using the fact that anodization was not performed in the region not immersed in the aqueous diammonium adipate solution, a portion of the surface on which the Al2O3 film was not formed was provided at the end portion of the Al foil to form a conduction portion. A 50-nm-thick Ti film was formed on the Al2O3 film by an RF magnetron sputtering method to obtain a first conductive layer. A mask as a heat-resistant adhesive tape was arranged so as to cover the conduction portion at the end portion of the Al foil, and the Ti film was provided so as to be electrically insulated from the conduction portion of the Al foil. Next, a 20-nm-thick ZrO2 film was formed on the Ti film by an RF magnetron sputtering method to obtain a second dielectric layer. A mask as a heat-resistant adhesive tape was arranged on the Ti film at the end portion of the Al foil opposite to the conduction portion, and an exposed portion in which the conduction portion and the Ti film were exposed was formed. Finally, a 50-nm-thick Ti film was formed on the ZrO2 film by an RF magnetron sputtering method to form a second conductive layer. Before the formation of the second conductive layer, a mask as a heat-resistant adhesive tape was arranged on the exposed portion so that the Ti film was not formed on the exposed portion. On the other hand, the Ti film was formed on the conduction portion. Thus, a capacitor of Example 1 having a MIMIM structure was obtained.

[0110] The capacitor of Example 1 was probed to take contact from the exposed portion using the second conductive layer as one electrode and the first conductive layer as the other electrode. Impedance measurement was performed using Modulab manufactured by Solartron Analytical Co. The results are shown in Table 1.

[0111] <Comparative Example 1> A conductive substrate, a first dielectric layer, and a first conductive layer were formed by the same method as in Example 1. An Al foil having a thickness of 120 μm was prepared as the conductive substrate. The surface of the Al foil was formed with a porous body. An Al2O3 film was formed on the surface of the Al foil by anodization. In the anodization, the Al foil was used as an anode while being immersed in a 0.3 mol / L aqueous diammonium adipate solution, and a voltage of 7 V was applied. The thickness of the formed Al2O3 film was 10 nm. A 50-nm-thick Ti film was formed on the Al2O3 film by an RF magnetron sputtering method to form a first conductive layer. Thus, a capacitor of Comparative Example 1 having a MIM structure was obtained.

[0112] By the same method as in Example 1, using a probe, the electrically conductive substrate was taken as one electrode, and the first electrically conductive layer as the other electrode. Impedance measurement was performed using Modulab manufactured by Solartron Analytical. The results are shown in Table 1.

[0113] As shown in Table 1, the capacitance of the capacitor of the MIMIM structure of Example 1 was higher than that of the capacitor of the MIM structure of Comparative Example 1. The capacitor of Example 1 has a MIMIM structure, and therefore the specific surface area of the dielectric layer is increased compared to the capacitor of Comparative Example 1, and as a result, it is considered that the capacitance of the capacitor is increased.

[0114] Table 1

[0115] Industrial applicability The capacitor of the present disclosure has a MIMIM structure, and is less restricted in size and substrate.

[0116] Explanation of reference numerals 1a, 1b, 1c capacitor 3 circuit 5 circuit substrate 7 device 10 substrate 10c through portion 11 porous portion 12 dense portion 21 first dielectric layer 22 second dielectric layer 31 first electrically conductive body 31e exposed portion 32 second electrically conductive body 35 electrically conductive adhesive portion 41 first terminal 42 second terminal 50 case 50r protective material E1 first exposed portion E2 second exposed portion P1 first site P2 second site P3 third site P4 fourth site P5 fifth site P6 sixth site M1 first mask M2 second mask

Claims

1. A capacitor comprising: a conductive substrate; a first dielectric layer disposed on the substrate; a first conductor disposed on the first dielectric layer and having a layer shape; a second dielectric layer disposed on the first conductor; and a second conductor disposed on the second dielectric layer. in, The first conductor includes an exposed portion not covered by the second dielectric layer and the second conductor. The substrate is electrically insulated from the first conductor through the first dielectric layer. The second conductor is electrically insulated from the first conductor through the second dielectric layer. The substrate includes a conductive portion that is electrically connected to the second conductor.

2. The capacitor according to claim 1, wherein, The conductive part is in contact with the second conductor.

3. The capacitor according to claim 1, wherein, The conductive portion is surrounded by the second conductive body.

4. The capacitor according to claim 1, wherein, The substrate includes a porous portion, and the first dielectric layer is disposed on the porous portion.

5. The capacitor according to claim 4, wherein, The porous component contains valve metal.

6. The capacitor according to claim 5, wherein, The valve is made of aluminum.

7. The capacitor according to claim 4, wherein, The porous portion comprises a sintered metal body.

8. The capacitor according to claim 7, wherein, The sintered metal body contains tantalum.

9. The capacitor according to claim 1, further comprising: a first terminal electrically connected to the substrate or the second conductor; and a second terminal electrically connected to the first conductor.

10. The capacitor according to claim 9, further comprising a conductive adhesive portion containing silver or a conductive polymer, wherein the first conductor is electrically connected to the second terminal through the conductive adhesive portion.

11. The capacitor according to claim 1, wherein, The inorganic compound is selected from at least one of the first dielectric layer and the second dielectric layer, wherein the inorganic compound comprises at least one of oxides, nitrides and oxynitrides, and the oxide comprises at least one of hafnium, zirconium, aluminum, tantalum, titanium, silicon, zinc and niobium.

12. The capacitor according to claim 1, wherein, The first conductor comprises at least one selected from Ti, W, Mo, Co, Ru, CoSi2, NiSi, TiN, TaN, indium tin oxide, ZnO, indium gallium zinc oxide, WO3, and TiAlN.

13. The capacitor according to claim 1, wherein, The second conductor comprises at least one selected from conductive polymers, electrolytes, manganese oxides, Ti, W, Mo, Co, Ru, CoSi2, NiSi, TiN, TaN, indium tin oxide, ZnO, indium gallium zinc oxide, WO3, and TiAlN.

14. A circuit comprising a capacitor according to any one of claims 1 to 13.

15. A circuit board comprising a capacitor according to any one of claims 1 to 13.

16. An apparatus comprising the capacitor according to any one of claims 1 to 13.

17. A method for manufacturing a capacitor, comprising the following steps: A first dielectric layer is formed on a conductive substrate; A layer is formed on the first dielectric layer by a first conductor; A second dielectric layer is formed on the first conductor; A second conductor is formed on the second dielectric layer; A first exposed portion is obtained by exposing a portion of the surface of the first conductor. as well as The second exposed portion, obtained by exposing a portion of the surface of the substrate, electrically connects the substrate to the second conductor.

18. The method of manufacturing a capacitor according to claim 17, wherein, In the steps of forming the first dielectric layer and forming the layer from the first conductor, with the first mask disposed on a portion of the surface of the substrate, i.e., a first portion, the first dielectric layer is formed on the substrate and the first mask, and the layer is formed on the first dielectric layer from the first conductor. It also includes the following steps: removing a portion of the first dielectric layer formed on the first mask, namely the second portion, and a portion of the first conductor disposed on the second portion, namely the third portion, together with the first mask. In the step of forming the second dielectric layer, after the first mask is removed, and with the second mask disposed on a portion of the first portion (i.e., the fourth portion) and a portion of the surface of the first conductor (i.e., the fifth portion), the second dielectric layer is formed on the second mask, the substrate, and the first conductor. In the steps of obtaining the first exposed portion and electrically connecting the substrate to the second conductor, a portion of the second dielectric layer formed on the second mask, namely the sixth portion, is removed together with the second mask to obtain the first exposed portion and the second exposed portion.

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