Two-dimensional semiconductor stack device structure and method of fabricating the same

Abstract

The application provides a two-dimensional semiconductor stacked device structure and a preparation method thereof, and realizes three-dimensional vertical stacking of a two-dimensional semiconductor device through a first interlayer dielectric layer and a second interlayer dielectric layer bonding process, effectively solves the problems of organic residue introduction, material folding and fracture and other problems commonly seen in the traditional two-dimensional semiconductor film transfer process, thereby significantly enhancing the integrity and long-term working stability of the stacked structure. At the same time, a high-efficiency interlayer isolation barrier is constructed by using the dielectric layer of the bonding interface, high-efficiency electrical isolation between the two two-dimensional semiconductor layers is realized, the threshold voltage crosstalk problem in the existing stacked structure is solved, independent and accurate adjustment of the threshold voltage of the upper and lower layer transistors is realized, and greater flexibility is provided for device performance optimization.

Description

Technical Field

[0001] This invention relates to the field of semiconductor device manufacturing, and in particular to a two-dimensional semiconductor stacked device structure and its fabrication method. Background Technology

[0002] Moore's Law drives the continuous miniaturization of silicon-based transistors, but as the size approaches the physical limit, the short-channel effect leads to increased leakage current and decreased carrier mobility, highlighting power consumption and stability issues. Traditional planar transistor architectures all face bottlenecks in performance optimization and integration improvement. Stacked transistors further improve device density through vertical integration.

[0003] Two-dimensional semiconductors such as transition metal dichalcogenides (TMDs) possess atomic-level thickness, effectively suppressing short-channel effects. They also exhibit high carrier mobility and compatibility with complementary metal-oxide-semiconductor (CMOS) processes, providing a new pathway for device miniaturization. While three-dimensional stacked device structures are often achieved through thin-film transfer, challenges remain regarding transfer process stability and large-scale production. Summary of the Invention

[0004] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a two-dimensional semiconductor stacked device structure and its fabrication method, so as to solve the problems of poor stability of the two-dimensional semiconductor thin film transfer process and difficulty in achieving large-scale production when fabricating two-dimensional semiconductor stacked device structures in the prior art.

[0005] To achieve the above and other related objectives, the present invention provides a method for fabricating a two-dimensional semiconductor stacked device structure, the method comprising:

[0006] S1, a first substrate is provided, and a first two-dimensional semiconductor layer and a first interlayer dielectric layer are sequentially formed on the first substrate; a second substrate is provided, and a second two-dimensional semiconductor layer and a second interlayer dielectric layer are sequentially formed on the second substrate;

[0007] S2, the surface of the first substrate on which the first interlayer dielectric layer is formed is bonded to the surface of the second substrate on which the second interlayer dielectric layer is formed;

[0008] S3, remove the first substrate to expose the first two-dimensional semiconductor layer, and form a first transistor structure based on the first two-dimensional semiconductor layer;

[0009] S4, forming a bonding insulating layer that covers the surface of the obtained structure on which the first transistor structure is formed;

[0010] S5, providing a carrier substrate and bonding the carrier substrate to the bonding insulating layer;

[0011] S6, remove the second substrate to expose the second two-dimensional semiconductor layer, and form a second transistor structure based on the second two-dimensional semiconductor layer.

[0012] Optionally, in step S2, the surface of the first substrate where the first interlayer dielectric layer is formed and the surface of the second substrate where the second interlayer dielectric layer is formed are bonded together by covalent bonds.

[0013] Optionally, the method for forming the first transistor structure based on the first two-dimensional semiconductor layer in step S3 includes:

[0014] S31, a first source / drain electrode layer is formed on a first predetermined source / drain region on the side of the first two-dimensional semiconductor layer away from the second substrate;

[0015] S32, the first two-dimensional semiconductor layer is patterned using photolithography and etching processes, and the patterned first two-dimensional semiconductor layer is formed below the first preset channel region and the first source and drain electrode layer.

[0016] S33, a first gate dielectric layer is formed on a first predetermined gate region on the exposed surfaces of the first interlayer dielectric layer and the first two-dimensional semiconductor layer, and a first gate electrode layer is formed on the first gate dielectric layer.

[0017] Before step S6, the method further includes a step of flipping the resulting structure so that the surface having the second substrate faces upward;

[0018] The method for forming the second transistor structure based on the second two-dimensional semiconductor layer in step S6 includes:

[0019] S61, a second source / drain electrode layer is formed on the second predetermined source / drain region of the second two-dimensional semiconductor layer away from the carrier substrate;

[0020] S62, the second two-dimensional semiconductor layer is patterned using photolithography and etching processes, and the resulting patterned second two-dimensional semiconductor layer is formed below the second preset channel region and the second source / drain electrode layer.

[0021] S63, a second gate dielectric layer is formed on the second predetermined gate region on the exposed surfaces of the second interlayer dielectric layer and the second two-dimensional semiconductor layer, and a second gate electrode layer is formed on the second gate dielectric layer.

[0022] Optionally, the alignment error between the first transistor structure formed in step S3 and the second transistor structure formed in step S6 in the direction perpendicular to the carrier substrate is -0.5µm to 0.5µm.

[0023] The present invention also provides a two-dimensional semiconductor stacked device structure, the device structure comprising:

[0024] The first stacked structure includes, in sequence, a first interlayer dielectric layer, a first two-dimensional semiconductor layer, and a first transistor structure based on the first two-dimensional semiconductor layer;

[0025] The second stacked structure includes, in sequence, a second interlayer dielectric layer, a second two-dimensional semiconductor layer, and a second transistor structure based on the second two-dimensional semiconductor layer; the first interlayer dielectric layer of the first stacked structure is bonded to the second interlayer dielectric layer of the second stacked structure.

[0026] A bonding insulating layer is formed on the surface of the first stacked structure away from the second stacked structure;

[0027] The substrate is bonded to the bonding insulating layer.

[0028] Optionally, the material of the first two-dimensional semiconductor layer includes one of MoS2, MoTe2, WSe2, WS2, MoSe2, SnS2, GeAs2, Bi2Te3, GeSe, GeSb2, Sb2Te3, SnS, TiS3, h-BN, graphene, and black phosphorus; the material of the second two-dimensional semiconductor layer includes one of MoS2, MoTe2, WSe2, WS2, MoSe2, SnS2, GeAs2, Bi2Te3, GeSe, GeSb2, Sb2Te3, SnS, TiS3, h-BN, graphene, and black phosphorus; the conductivity type of the first two-dimensional semiconductor layer is N-type or P-type, and the conductivity type of the second two-dimensional semiconductor layer is N-type or P-type.

[0029] Optionally, the thickness of the first two-dimensional semiconductor layer is 1 to 10 atomic layers, and the thickness of the second two-dimensional semiconductor layer is 1 to 10 atomic layers.

[0030] Optionally, the material of the first interlayer dielectric layer includes one or more of Al2O3, SiO2, ZrO2, TiO2, La2O3, SiOCH, SiOC, h-BN, Si3N4, benzocyclobutene, parylene, and polyimide; the material of the second interlayer dielectric layer includes one or more of Al2O3, SiO2, ZrO2, TiO2, La2O3, SiOCH, SiOC, h-BN, Si3N4, benzocyclobutene, parylene, and polyimide; the thickness of the first interlayer dielectric layer is 150nm~500nm, and the thickness of the second interlayer dielectric layer is 150nm~500nm.

[0031] Optionally, the first transistor structure includes: a first source / drain electrode layer formed on a first predetermined source / drain region of the first two-dimensional semiconductor layer away from the second stacked structure, a first gate dielectric layer formed in a first predetermined gate region, and a first gate electrode layer formed on the first gate dielectric layer.

[0032] The second transistor structure includes: a second source / drain electrode layer formed on a second predetermined source / drain region on the side of the second two-dimensional semiconductor layer away from the carrier substrate, a second gate dielectric layer formed in a second predetermined gate region, and a second gate electrode layer formed on the second gate dielectric layer.

[0033] Optionally, the second interlayer dielectric layer is covalently bonded to the first interlayer dielectric layer.

[0034] Optionally, the alignment error between the first transistor structure and the second transistor structure in the direction perpendicular to the carrier substrate is -0.5µm to 0.5µm.

[0035] As described above, the two-dimensional semiconductor stacked device structure and its fabrication method of the present invention have the following beneficial effects:

[0036] Device reliability upgrade: The bonding process between the first interlayer dielectric layer and the second interlayer dielectric layer is adopted to replace the traditional thin film transfer, which blocks the introduction of contaminants such as organic residues from the source of preparation. At the same time, it avoids structural damage such as wrinkles and fractures caused by the transfer of two-dimensional semiconductor materials, which reduces the leakage rate of the stacked structure by 1 to 2 orders of magnitude and achieves a qualitative improvement in long-term working stability.

[0037] Breakthrough in electrical control flexibility: The interlayer dielectric layer at the bonding interface constructs an efficient interlayer isolation barrier, eliminating the crosstalk problem of threshold voltage in traditional stacking architectures, enabling independent and precise adjustment of the threshold voltage of the first transistor structure and the second transistor structure, and providing core support for customized optimization of device performance.

[0038] Cross-dimensional improvement in integration density: By using a vertically stacked multi-layer transistor architecture, the physical limitations of planar integration are broken, increasing the device integration density by more than 50% compared to traditional planar structures, providing a key path to overcome the bottleneck of Moore's Law.

[0039] Optimized industrialization costs: The bonding process and processes such as 2D semiconductor growth, etching, and metal deposition are all compatible with the existing CMOS manufacturing system, without the need to reconstruct production lines or add special equipment, which greatly reduces the threshold for large-scale production and the cost of industrial upgrading.

[0040] Diverse functional scenarios: It supports homogeneous stacking of two-dimensional materials or heterogeneous combination of different two-dimensional materials, and can expand N / P type complementary structures to meet the needs of multiple fields such as logic operation, sensing and detection, and information storage, thus broadening the application boundaries of the device.

[0041] Deep release of industrial value: Drive the iteration of chips towards high integration and low power consumption, support the development of cutting-edge fields such as artificial intelligence and 5G communication, and the increase in functional density per unit area is expected to drive market value growth. Attached Figure Description

[0042] Figure 1 The diagram shows a flow chart of the fabrication method of the two-dimensional semiconductor stacked device structure of the present invention.

[0043] Figure 2 The diagram shows a cross-sectional structure of the present invention in which one side of the first substrate having a first interlayer dielectric layer is bonded to one side of the second substrate having a second interlayer dielectric layer.

[0044] Figures 3 to 6 The diagram shown is a top view of the steps in the method of removing a first substrate and forming a first transistor structure based on a first two-dimensional semiconductor layer according to the present invention.

[0045] Figure 7 Shown as the present invention along Figure 6 A schematic diagram of the cross-sectional structure in the AA' direction.

[0046] Figure 8 The diagram shown is a cross-sectional view of the second transistor structure formed based on the second two-dimensional semiconductor layer according to the present invention.

[0047] Component labeling description: 1 First stacked structure, 10 First substrate, 11 First two-dimensional semiconductor layer, 12 First interlayer dielectric layer, 13 First source / drain electrode layer, 14 First gate dielectric layer, 15 First gate electrode layer, 16 First transistor structure, 2 Second stacked structure, 20 Second substrate, 21 Second two-dimensional semiconductor layer, 22 Second interlayer dielectric layer, 23 Second source / drain electrode layer, 24 Second gate dielectric layer, 25 Second gate electrode layer, 26 Second transistor structure, 30 Bonding insulating layer, 40 Carrier substrate, Steps S1~S6. Detailed Implementation

[0048] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0049] Please see Figures 1 to 8 It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the illustrations only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0050] This embodiment provides a method for fabricating a two-dimensional semiconductor stacked device structure, such as... Figure 1 As shown, the preparation method includes:

[0051] S1, a first substrate is provided, and a first two-dimensional semiconductor layer and a first interlayer dielectric layer are sequentially formed on the first substrate; a second substrate is provided, and a second two-dimensional semiconductor layer and a second interlayer dielectric layer are sequentially formed on the second substrate;

[0052] S2, the side of the first substrate with the first interlayer dielectric layer formed is bonded to the side of the second substrate with the second interlayer dielectric layer formed;

[0053] S3, remove the first substrate to expose the first two-dimensional semiconductor layer, and form a first transistor structure based on the first two-dimensional semiconductor layer;

[0054] S4, forming a bonding insulating layer that covers the surface of the obtained structure on which the first transistor structure is formed;

[0055] S5, providing a carrier substrate and bonding the carrier substrate to the bonding insulating layer;

[0056] S6, remove the second substrate to expose the second two-dimensional semiconductor layer, and form a second transistor structure based on the second two-dimensional semiconductor layer.

[0057] The fabrication method of the two-dimensional semiconductor stacked device structure in this embodiment replaces the traditional two-dimensional semiconductor thin film transfer process with a bonding process between the first and second interlayer dielectric layers, realizing three-dimensional vertical stacking of two-dimensional semiconductor devices. This solves the problems of poor stability and difficulty in large-scale production of two-dimensional semiconductor thin film transfer processes in the fabrication of two-dimensional semiconductor stacked devices in the prior art. This method not only blocks the introduction of contaminants such as organic residues at the source, avoiding performance degradation caused by structural damage such as wrinkles and fractures in two-dimensional semiconductor materials during transfer, but also reduces the leakage current of the stacked structure by 1 to 2 orders of magnitude, improving the long-term operating stability of the device. At the same time, the dielectric layer at the bonding interface constructs an efficient interlayer isolation barrier, solving the crosstalk problem of threshold voltage in the existing stacked architecture, and realizing independent and precise adjustment of the threshold voltage of the upper and lower transistors, providing core support for customized optimization of device performance. In addition, through the vertical stacking of multilayer transistors, the physical limitations of planar integration are broken, increasing the device integration density by more than 50% compared with the traditional planar structure, providing a key path to overcome the bottleneck of Moore's Law. This fabrication method is highly compatible with existing CMOS manufacturing systems, requiring no reconstruction of production lines or addition of special equipment. It significantly lowers the threshold for large-scale production and the cost of industrial upgrading, promoting the iterative development of chips towards high integration and low power consumption. This provides strong support for the development of cutting-edge fields such as artificial intelligence and 5G communication. At the same time, it broadens the application boundaries of devices in multiple fields such as logic operation, sensing and detection, and information storage, and improves the functional density per unit area. It is expected to further drive the growth of market value.

[0058] The fabrication method of the two-dimensional semiconductor stacked device structure of this embodiment will be described in detail below with reference to the specific accompanying drawings.

[0059] like Figure 2 As shown, step S1 is performed first, a first substrate 10 is provided, and a first two-dimensional semiconductor layer 11 and a first interlayer dielectric layer 12 are sequentially formed on the first substrate 10; a second substrate 20 is provided, and a second two-dimensional semiconductor layer 21 and a second interlayer dielectric layer 22 are formed on the second substrate 20.

[0060] As an example, the first substrate 10 can be any one of a glass substrate, a sapphire substrate, a quartz substrate, and a silicon (Si) substrate, and more specifically, a Si substrate with a silicon dioxide (SiO2) layer formed on its surface, wherein the thickness of the SiO2 layer is, exemplarily, 300 nm; the second substrate 20 can be any one of a glass substrate, a sapphire substrate, a quartz substrate, and a Si substrate, and more specifically, a Si substrate with a SiO2 layer formed on its surface, wherein the thickness of the SiO2 layer is, exemplarily, 300 nm. The size of the first substrate 10 can be at the wafer level, exemplarily, a 4-inch wafer; the size of the second substrate 20 can be at the wafer level, exemplarily, a 4-inch wafer. Preferably, in this embodiment, the first substrate 10 and the second substrate 20 are of the same size. The materials and sizes of the first substrate 10 and the second substrate 20 can be selected according to actual needs, and no excessive restrictions are imposed here.

[0061] As a preferred example, before forming the first two-dimensional semiconductor layer 11 on the first substrate 10 and the second two-dimensional semiconductor layer 21 on the second substrate 20, the method further includes ultrasonically cleaning the first substrate 10 and the second substrate 20 with acetone, isopropanol and deionized water for 10 minutes in sequence, and then drying them with nitrogen gas.

[0062] As an example, the materials of the first two-dimensional semiconductor layer 11 include molybdenum disulfide (MoS2), molybdenum ditelluride (MoTe2), tungsten diselenide (WSe2), tungsten disulfide (WS2), molybdenum diselenide (MoSe2), tin disulfide (SnS2), germanium diarsenide (GeAs2), bismuth tritelluride (Bi2Te3), germanium selenide (GeSe), germanium diantimonide (GeSb2), antimony tritelluride (Sb2Te3), tin sulfide (SnS), titanium trisulfide (TiS3), and hexachlorocyclohexane (HCH). The first two-dimensional semiconductor layer 11 has an N-type or P-type conductivity, and the second two-dimensional semiconductor layer 21 has an N-type or P-type conductivity. The first two-dimensional semiconductor layer 11 and the second two-dimensional semiconductor layer 21 can be homogeneous, meaning the material and conductivity of the first two-dimensional semiconductor layer 11 can be the same as those of the second two-dimensional semiconductor layer 21. Alternatively, the first two-dimensional semiconductor layer 11 and the second two-dimensional semiconductor layer 21 can be heterogeneous, meaning the material of the first two-dimensional semiconductor layer 11 is different from that of the second two-dimensional semiconductor layer 21, but the conductivity types are the same, or the material of the first two-dimensional semiconductor layer 11 is different from that of the second two-dimensional semiconductor layer 21, and the conductivity types are also different. As a specific example, the material of the first two-dimensional semiconductor layer 11 can be MoS2, and the conductivity type of the first two-dimensional semiconductor layer 11 is N-type; the material of the second two-dimensional semiconductor layer 21 can also be MoS2, and the conductivity type of the second two-dimensional semiconductor layer 21 is N-type; or the material of the first two-dimensional semiconductor layer 11 can be MoS2, and the conductivity type of the first two-dimensional semiconductor layer 11 is N-type; the material of the second two-dimensional semiconductor layer 21 can be WSe2, and the conductivity type of the second two-dimensional semiconductor layer 21 is P-type. This fabrication method can expand N / P-type complementary structures to meet the needs of various application scenarios such as logic, sensing, and storage, opening up new paths for semiconductor functional innovation.

[0063] As an example, the first two-dimensional semiconductor layer 11 can be formed "bottom-up" using processes including but not limited to chemical vapor deposition (CVD), metal-organic chemical vapor deposition (MOCVD), or molecular beam epitaxy (MBE), or "top-down" using micromechanical lift-off, ion intercalation lift-off, or ultrasonic lift-off. Similarly, the second two-dimensional semiconductor layer 21 can be formed "bottom-up" using processes including but not limited to chemical vapor deposition, metal-organic chemical vapor deposition, or molecular beam epitaxy, or "top-down" using micromechanical lift-off, ion intercalation lift-off, or ultrasonic lift-off. The methods for forming the first two-dimensional semiconductor layer 11 and the second two-dimensional semiconductor layer 21 are not excessively limited here.

[0064] As an example, the thickness of the first two-dimensional semiconductor layer 11 is 1 to 10 atomic layers, and the thickness of the second two-dimensional semiconductor layer 21 is 1 to 10 atomic layers. These can be formed according to the actual device performance requirements and are not limited to this embodiment.

[0065] Specifically, in this embodiment, a chemical vapor deposition process is used, with molybdenum trioxide (MoO3, purity 99.99%) as the molybdenum source and sulfur powder (purity 99.99%) as the sulfur source. In an atmosphere of mixed argon (Ar) and hydrogen (H2) gas, the MoS2 thin film is grown on the first substrate 10 and the second substrate 20 at 650°C for 15 minutes to obtain a single-layer atomic thickness MoS2 thin film, which serves as the first two-dimensional semiconductor layer 11 and the second two-dimensional semiconductor layer 21, respectively.

[0066] As an example, the material of the first interlayer dielectric layer 12 includes one or more of aluminum oxide (Al2O3), silicon dioxide (SiO2), zirconium dioxide (ZrO2), titanium dioxide (TiO2), lanthanum oxide (La2O3), silicon-oxygen-carbon-hydrogen (SiOCH), silicon-oxygen-carbon (SiOC), hexagonal boron nitride (h-BN), silicon nitride (Si3N4), benzocyclobutene, poly(p-xylene), and polyimide; and the material of the second interlayer dielectric layer 22 includes Al2O3, SiO2, ZrO2, TiO2, and TiO2. The material selected is one or more of O2, La2O3, SiOCH, SiOC, h-BN, Si3N4, benzocyclobutene, poly(p-xylene), and polyimide; the thickness of the first interlayer dielectric layer 12 is 150nm~500nm, and the thickness of the second interlayer dielectric layer 22 is 150nm~500nm. In this embodiment, the material of both the first interlayer dielectric layer 12 and the second interlayer dielectric layer 22 is SiO2, and the thickness of both the first interlayer dielectric layer 12 and the second interlayer dielectric layer 22 is 300nm.

[0067] As an example, the first interlayer dielectric layer 12 can be formed using processes including but not limited to atomic layer deposition, chemical vapor deposition, or physical vapor deposition. Similarly, the second interlayer dielectric layer 22 can be formed using processes including but not limited to atomic layer deposition, chemical vapor deposition, or physical vapor deposition. In this embodiment, plasma-enhanced chemical vapor deposition (PECVD) is preferably used to form the first interlayer dielectric layer 12 and the second interlayer dielectric layer 22.

[0068] like Figure 2 As shown, step S2 is then performed, whereby the surface of the first substrate 10 where the first interlayer dielectric layer 12 is formed is bonded to the surface of the second substrate 20 where the second interlayer dielectric layer 22 is formed.

[0069] Preferably, in this embodiment, the surface of the first substrate 10 where the first interlayer dielectric layer 12 is formed and the surface of the second substrate 20 where the second interlayer dielectric layer 22 is formed are bonded together by covalent bonds to achieve mechanical and electrical isolation between the first two-dimensional semiconductor layer 11 and the second two-dimensional semiconductor layer 21.

[0070] like Figure 7 As shown, step S3 is then performed to remove the first substrate 10 to expose the first two-dimensional semiconductor layer 11, and a first transistor structure 16 is formed based on the first two-dimensional semiconductor layer 11.

[0071] As an example, the first substrate 10 can be removed by a chemical etching process or a mechanical stripping process. For instance, a tetramethylammonium hydroxide (TMAH) solution can be used to remove the silicon substrate serving as the first substrate 10. Figure 3 The diagram shown is a top view of the surface of the first two-dimensional semiconductor layer 11 exposed away from the second substrate 20 after the first substrate 10 is removed in step S3.

[0072] As a specific example, such as Figures 4 to 6 As shown in the top view, the method for forming the first transistor structure 16 based on the first two-dimensional semiconductor layer 11 in step S3 includes:

[0073] S31, such as Figure 4As shown, a first source / drain electrode layer 13 is formed on a first predetermined source / drain region on the side of the first two-dimensional semiconductor layer 11 away from the second substrate 20. Specifically, the material of the first source / drain electrode layer 13 includes, but is not limited to, one or more of gold (Au), silver (Ag), platinum (Pt), nickel (Ni), titanium (Ti), aluminum (Al), chromium (Cr), copper (Cu), palladium (Pd), yttrium (Y), antimony (Sb), bismuth (Bi), tantalum nitride (TaN), titanium carbide (TiC), and titanium nitride (TiN). The formation method involves first defining the first predetermined source / drain region, and then depositing and forming the first source / drain electrode layer 13. As a further specific example, the first preset source / drain region is defined on the first two-dimensional semiconductor layer 11 by a first masking layer. The first masking layer can be photoresist or a mask. The patterning method of the first masking layer is to use photolithography, which patterns the photoresist through exposure, development, or other means; or to use a mask, which patterns the first source / drain electrode layer 13 are closely attached to the surface of the first two-dimensional semiconductor layer 11 for patterning; then, the first source / drain electrode layer 13 is prepared by vacuum evaporation or sputtering deposition. The first source / drain electrode layer 13 can be, for example, a Ti / Au stack or an Au layer. The thickness of the first source / drain electrode layer 13 can be, for example, 20nm~100nm, wherein the Ti layer in the Ti / Au stack serves as an adhesion layer with a thickness of 5nm, and the Au layer serves as a conductive layer with a thickness of 30nm. In this embodiment, photolithography is used, with photoresist as the first masking layer. The pattern of the first preset source / drain region is obtained on the surface of the first two-dimensional semiconductor layer 11 through exposure and development. The first source / drain electrode layer 13 is prepared by electron beam evaporation deposition. The formation process, materials, and thickness of the first source / drain electrode layer 13 are not limited to this embodiment.

[0074] S32, as Figure 5 As shown, the first two-dimensional semiconductor layer 11 is patterned using photolithography and etching processes. The resulting patterned first two-dimensional semiconductor layer 11 is formed below the first preset channel region and the first source / drain electrode layer 13, thereby forming the device channel of the first transistor structure 16. The photolithography process can be, for example, dry etching commonly used in the art, such as plasma etching, reactive ion etching, or ion sputtering etching. In this embodiment, inductively coupled plasma etching (ICP) is used to etch and remove the first two-dimensional semiconductor layer 11 outside the first preset channel region using a mixed gas of carbon tetrafluoride (CF4) and argon (Ar).

[0075] S33, such as Figure 6 and Figure 7As shown, a first gate dielectric layer 14 is formed on a first predetermined gate region on the exposed surfaces of the first interlayer dielectric layer 12 and the first two-dimensional semiconductor layer 11, and a first gate electrode layer 15 is formed on the first gate dielectric layer 14. Figure 7 The following is along Figure 6 A schematic diagram of the cross-sectional structure truncated along the AA' direction. The material of the first gate dielectric layer 14 includes, but is not limited to, hafnium oxide (HfO2), aluminum oxide (Al2O3), zirconium dioxide (ZrO2), lanthanum oxide (La2O3), titanium dioxide (TiO2), or silicon oxide (SiO2). The thickness of the first gate dielectric layer 14 can be 10nm~40nm. The formation method of the first gate dielectric layer 14 includes, but is not limited to, atomic layer deposition, chemical vapor deposition, or physical vapor deposition. In this embodiment, atomic layer deposition is used, with tetrakis(dimethylamino)hafnium (TDMAH) and water (H2O) as precursors, depositing HfO2 at 180°C as the first gate dielectric layer 14, with a thickness of 20nm. The material of the first gate electrode layer 15 includes, but is not limited to, one or more of Au, Ag, Ti, Al, Cr, Cu, Pt, Ni, Pd, TaN, TiC and TiN. In this embodiment, an Au layer with a thickness of 30 nm is deposited as the first gate electrode layer 15. The method for forming the first gate electrode layer 15 can be referred to the description of the method for forming the first source and drain electrode layer 13 in step S31, which will not be elaborated here.

[0076] like Figure 8 As shown, step S4 is then performed to form a bonding insulating layer 30, which covers the surface of the obtained structure on which the first transistor structure 16 is formed.

[0077] As an example, the bonded insulating layer 30 can be deposited using processes including but not limited to atomic layer deposition, chemical vapor deposition, or physical vapor deposition.

[0078] As an example, the material of the bonding insulating layer 30 includes, but is not limited to, Al2O3 or SiO2, and the thickness of the bonding insulating layer 30 is 150nm~500nm. In this embodiment, the material of the bonding insulating layer 30 is SiO2, and the thickness of the bonding insulating layer 30 is 300nm.

[0079] As an example, the bonded insulating layer 30 can be formed using processes including but not limited to atomic layer deposition, chemical vapor deposition, or physical vapor deposition. In this embodiment, plasma-enhanced chemical vapor deposition is selected to form the bonded insulating layer 30.

[0080] like Figure 8As shown, step S5 is then performed, in which a carrier substrate 40 is provided, and the carrier substrate 40 is bonded to the bonding insulating layer 30.

[0081] As an example, the carrier substrate 40 can be any one of a glass substrate, sapphire substrate, quartz substrate, silicon substrate, and flexible substrate. The size of the carrier substrate 40 can be at the wafer level, for example, a 4-inch wafer. The material and size of the carrier substrate 40 can be selected according to actual needs, and no excessive restrictions are imposed here. Preferably, in this embodiment, the first substrate 10, the second substrate 20, and the carrier substrate 40 are all the same size.

[0082] like Figure 8 As shown, step S6 is then performed to remove the second substrate 20 to expose the second two-dimensional semiconductor layer 21, and a second transistor structure 26 is formed based on the second two-dimensional semiconductor layer 21.

[0083] As a preferred specific example, before step S6, the resulting structure is further included in the step of flipping it so that the surface having the second substrate 20 is facing upwards.

[0084] The method for forming the second transistor structure 26 based on the second two-dimensional semiconductor layer 21 in step S6 includes:

[0085] S61, a second source / drain electrode layer 23 is formed on a second predetermined source / drain region on the side of the second two-dimensional semiconductor layer 21 away from the supporting substrate 40. Specifically, the material of the second source / drain electrode layer 23 includes, but is not limited to, one or more of Au, Ag, Pt, Ni, Ti, Al, Cr, Cu, Pd, Y, Sb, Bi, TaN, TiC, TaC, and TiN. The formation method is to first define the second predetermined source / drain region, and then deposit the second source / drain electrode layer 23. As a further specific example, the second predetermined source / drain region is defined on the second two-dimensional semiconductor layer 21 by a second masking layer. The second masking layer can be photoresist or a mask. The patterning method of the second masking layer is to use photolithography to pattern the photoresist through exposure, development, or other means; or to use a mask, to pattern the mask containing the pattern of the second source / drain electrode layer 23 by closely attaching it to the surface of the second two-dimensional semiconductor layer 21; and then to prepare the second source / drain electrode layer 23 by vacuum evaporation or sputtering deposition. The second source / drain electrode layer 23 can be, for example, a Ti / Au stack or an Au layer. The thickness of the second source / drain electrode layer 23 can be, for example, 20nm to 100nm. In the Ti / Au stack, the Ti layer serves as an adhesion layer with a thickness of 5nm, and the Au layer serves as a conductive layer with a thickness of 30nm. In this embodiment, photolithography is used, with photoresist as the second masking layer. The pattern of the second preset source / drain electrode region is obtained on the surface of the second two-dimensional semiconductor layer 21 through exposure and development. The second source / drain electrode layer 23 is fabricated using an electron beam evaporation deposition process. The formation process, materials, and thickness of the second source / drain electrode layer 23 are not limited to this embodiment.

[0086] S62, the second two-dimensional semiconductor layer 21 is patterned using photolithography and etching processes. The resulting patterned second two-dimensional semiconductor layer 21 is formed below the second preset channel region and the second source / drain electrode layer 23, thereby forming the device channel of the second transistor structure 26. This photolithography process can be, for example, dry etching commonly used in the art, such as plasma etching, reactive ion etching, or ion sputtering etching. In this embodiment, inductively coupled plasma etching is used to remove the second two-dimensional semiconductor layer 21 outside the second preset channel region.

[0087] S63, a second gate dielectric layer 24 is formed on the second predetermined gate region on the exposed surfaces of the second interlayer dielectric layer 22 and the second two-dimensional semiconductor layer 21, and a second gate electrode layer 25 is formed on the second gate dielectric layer 24. The material of the second gate dielectric layer 24 includes, but is not limited to, HfO2, Al2O3, ZrO2, La2O3, TiO2, or SiO2. The formation method of the second gate dielectric layer 24 includes, but is not limited to, atomic layer deposition, chemical vapor deposition, or physical vapor deposition, with a thickness of 10nm to 40nm. In this embodiment, hafnium oxide is selected as the material for the second gate dielectric layer 24, with a thickness of 20nm. The material of the second gate electrode layer 25 includes, but is not limited to, one or more of Au, Ag, Ti, Al, Cr, Cu, Pt, Ni, Pd, TaN, TiC and TiN. In this embodiment, an Au layer with a thickness of 30 nm is deposited as the second gate electrode layer 25. The method for forming the second gate electrode layer 25 can be referred to the description of the method for forming the second source and drain electrode layer 23 in step S61, which will not be elaborated here.

[0088] As an example, the alignment error between the first transistor structure 16 formed in step S3 and the second transistor structure 26 formed in step S6 in the direction perpendicular to the carrier substrate 40 is -0.5µm to 0.5µm. In this embodiment, it is preferable that the first transistor structure 16 and the second transistor structure 26 are aligned in the direction perpendicular to the carrier substrate 40 to reduce the planar size of the overall structure.

[0089] This completes the fabrication of the two-dimensional semiconductor stacked device structure of this embodiment.

[0090] This embodiment also provides a two-dimensional semiconductor stacked device structure, see reference. Figure 8 The device structure includes:

[0091] The first stacked structure 1 includes, in sequence, a first interlayer dielectric layer 12, a first two-dimensional semiconductor layer 11, and a first transistor structure 16 based on the first two-dimensional semiconductor layer 11;

[0092] The second stacked structure 2 includes, in sequence, a second interlayer dielectric layer 22, a second two-dimensional semiconductor layer 21, and a second transistor structure 26 based on the second two-dimensional semiconductor layer 21; the first interlayer dielectric layer 12 of the first stacked structure 1 is bonded to the second interlayer dielectric layer 22 of the second stacked structure 2.

[0093] A bonding insulating layer 30 is formed on the surface of the first stacked structure 1 away from the second stacked structure 2;

[0094] The substrate 40 is bonded to the bonding insulating layer 30.

[0095] The two-dimensional semiconductor stacked device structure can be prepared using the above-described method, but it is not limited to this method. Other suitable preparation methods are also possible, and their beneficial effects can be cited in full here. For the sake of brevity, they will not be elaborated further.

[0096] As an example, the material of the first two-dimensional semiconductor layer 11 includes one of MoS2, MoTe2, WSe2, WS2, MoSe2, SnS2, GeAs2, Bi2Te3, GeSe, GeSb2, Sb2Te3, SnS, TiS3, h-BN, graphene, and black phosphorus; the material of the second two-dimensional semiconductor layer 21 includes one of MoS2, MoTe2, WSe2, WS2, MoSe2, SnS2, GeAs2, Bi2Te3, GeSe, GeSb2, Sb2Te3, SnS, TiS3, h-BN, graphene, and black phosphorus; the conductivity type of the first two-dimensional semiconductor layer 11 is N-type or P-type, and the conductivity type of the second two-dimensional semiconductor layer 21 is N-type or P-type. The first two-dimensional semiconductor layer 11 and the second two-dimensional semiconductor layer 21 can be homogeneous, and the material and conductivity type of the first two-dimensional semiconductor layer 11 and the second two-dimensional semiconductor layer 21 can be the same; the first two-dimensional semiconductor layer 11 and the second two-dimensional semiconductor layer 21 can also be heterogeneous, and the material of the first two-dimensional semiconductor layer 11 and the second two-dimensional semiconductor layer 21 are different, but the conductivity type is the same, or the material of the first two-dimensional semiconductor layer 11 and the second two-dimensional semiconductor layer 21 are different, and the conductivity type is also different.

[0097] As an example, the thickness of the first two-dimensional semiconductor layer 11 is 1 to 10 atomic layers, and the thickness of the second two-dimensional semiconductor layer 21 is 1 to 10 atomic layers.

[0098] As an example, the material of the first interlayer dielectric layer 12 includes one or more of Al2O3, SiO2, ZrO2, TiO2, La2O3, SiOCH, SiOC, h-BN, Si3N4, benzocyclobutene, parylene, and polyimide; the material of the second interlayer dielectric layer 22 includes one or more of Al2O3, SiO2, ZrO2, TiO2, La2O3, SiOCH, SiOC, h-BN, Si3N4, benzocyclobutene, parylene, and polyimide; the thickness of the first interlayer dielectric layer 12 is 150nm~500nm, and the thickness of the second interlayer dielectric layer 22 is 150nm~500nm. In this embodiment, both the first interlayer dielectric layer 12 and the second interlayer dielectric layer 22 are made of SiO2, and both have a thickness of 300nm.

[0099] As an example, the first transistor structure 16 includes: a first source-drain electrode layer 13 formed on a first predetermined source-drain electrode region on the side of the first two-dimensional semiconductor layer 11 away from the second stacked structure 2, a first gate dielectric layer 14 formed on a first predetermined gate region, and a first gate electrode layer 15 formed on the first gate dielectric layer 14.

[0100] The second transistor structure 26 includes: a second source / drain electrode layer 23 formed on a second predetermined source / drain region of the second two-dimensional semiconductor layer 21 away from the carrier substrate 40, a second gate dielectric layer 24 formed on a second predetermined gate region, and a second gate electrode layer 25 formed on the second gate dielectric layer 24.

[0101] As a preferred example, the second interlayer dielectric layer 22 is covalently bonded to the first interlayer dielectric layer 12.

[0102] As a preferred example, the alignment error between the first transistor structure 16 and the second transistor structure 26 in the direction perpendicular to the carrier substrate 40 is -0.5µm to 0.5µm. In a further preferred embodiment, the first transistor structure 16 is aligned with the second transistor structure 26 in the direction perpendicular to the carrier substrate 40 to reduce the overall planar dimensions of the structure.

[0103] In summary, the two-dimensional semiconductor stacked device structure and its fabrication method of this invention, by replacing the traditional two-dimensional semiconductor thin film transfer process with a bonding process between the first and second interlayer dielectric layers, achieves three-dimensional vertical stacking of two-dimensional semiconductor devices. This solves the problems of poor stability and difficulty in large-scale production of two-dimensional semiconductor thin film transfer processes faced by existing technologies in the fabrication of two-dimensional semiconductor stacked devices. This method not only blocks the introduction of contaminants such as organic residues at the source, avoiding performance degradation caused by structural damage such as wrinkles and fractures in two-dimensional semiconductor materials during transfer, but also reduces the leakage current of the stacked structure by 1 to 2 orders of magnitude, improving the long-term operational stability of the device. Simultaneously, the dielectric layer at the bonding interface constructs an efficient interlayer isolation barrier, solving the crosstalk problem of threshold voltage in existing stacked architectures, and enabling independent and precise adjustment of the threshold voltage of upper and lower transistor layers, providing core support for customized optimization of device performance. Furthermore, through the vertical stacking of multilayer transistors, the physical limitations of planar integration are broken, increasing the device integration density by more than 50% compared to traditional planar structures, providing a key path to overcome the bottleneck of Moore's Law. This fabrication method is highly compatible with existing CMOS manufacturing systems, requiring no production line reconstruction or the addition of special equipment. This significantly lowers the barriers to large-scale production and reduces industry upgrading costs, driving the iterative development of chips towards high integration and low power consumption. It provides strong support for the development of cutting-edge fields such as artificial intelligence and 5G communication, while also broadening the application boundaries of devices in logic operations, sensing, and information storage, increasing functional density per unit area, and is expected to further drive market value growth. Therefore, this invention effectively overcomes the various shortcomings of existing technologies and has high industrial applicability.

[0104] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A method for fabricating a two-dimensional semiconductor stacked device structure, characterized in that, The preparation method includes: S1, a first substrate is provided, and a first two-dimensional semiconductor layer and a first interlayer dielectric layer are sequentially formed on the first substrate; a second substrate is provided, and a second two-dimensional semiconductor layer and a second interlayer dielectric layer are sequentially formed on the second substrate; S2, the surface of the first substrate on which the first interlayer dielectric layer is formed is bonded to the surface of the second substrate on which the second interlayer dielectric layer is formed; S3, remove the first substrate to expose the first two-dimensional semiconductor layer, and form a first transistor structure based on the first two-dimensional semiconductor layer; S4, forming a bonding insulating layer that covers the surface of the obtained structure on which the first transistor structure is formed; S5, providing a carrier substrate and bonding the carrier substrate to the bonding insulating layer; S6, remove the second substrate to expose the second two-dimensional semiconductor layer, and form a second transistor structure based on the second two-dimensional semiconductor layer; and the alignment error between the first transistor structure and the second transistor structure in the direction perpendicular to the carrier substrate is -0.5µm to 0.5µm; The method for forming the first transistor structure based on the first two-dimensional semiconductor layer in step S3 includes: S31, a first source / drain electrode layer is formed on a first predetermined source / drain region on the side of the first two-dimensional semiconductor layer away from the second substrate; S32, the first two-dimensional semiconductor layer is patterned using photolithography and etching processes, and the patterned first two-dimensional semiconductor layer is formed below the first preset channel region and the first source and drain electrode layer. S33, a first gate dielectric layer is formed on a first predetermined gate region on the exposed surfaces of the first interlayer dielectric layer and the first two-dimensional semiconductor layer, and a first gate electrode layer is formed on the first gate dielectric layer. Before step S6, the method further includes a step of flipping the resulting structure so that the surface having the second substrate faces upward; The method for forming the second transistor structure based on the second two-dimensional semiconductor layer in step S6 includes: S61, a second source / drain electrode layer is formed on the second predetermined source / drain region of the second two-dimensional semiconductor layer away from the carrier substrate; S62, the second two-dimensional semiconductor layer is patterned using photolithography and etching processes, and the resulting patterned second two-dimensional semiconductor layer is formed below the second preset channel region and the second source / drain electrode layer. S63, a second gate dielectric layer is formed on the second predetermined gate region on the exposed surfaces of the second interlayer dielectric layer and the second two-dimensional semiconductor layer, and a second gate electrode layer is formed on the second gate dielectric layer.

2. The method for fabricating a two-dimensional semiconductor stacked device structure according to claim 1, characterized in that: In step S2, the surface of the first substrate where the first interlayer dielectric layer is formed and the surface of the second substrate where the second interlayer dielectric layer is formed are bonded together by covalent bonds.

3. A two-dimensional semiconductor stacked device structure, characterized in that, The device structure sequentially includes a carrier substrate, a bonding insulating layer, a first stacked structure, and a second stacked structure: The first stacked structure includes, in sequence, a first interlayer dielectric layer, a first two-dimensional semiconductor layer, and a first transistor structure based on the first two-dimensional semiconductor layer; The first transistor structure includes: a first source-drain electrode layer formed on a first predetermined source-drain region on the side of the first two-dimensional semiconductor layer away from the second stacked structure, a first gate dielectric layer formed in a first predetermined gate region, and a first gate electrode layer formed on the first gate dielectric layer; The second stacked structure includes, in sequence, a second interlayer dielectric layer, a second two-dimensional semiconductor layer, and a second transistor structure based on the second two-dimensional semiconductor layer; the first interlayer dielectric layer of the first stacked structure is bonded to the second interlayer dielectric layer of the second stacked structure; the second transistor structure includes: a second source / drain electrode layer formed on a second predetermined source / drain region on a side of the second two-dimensional semiconductor layer away from the carrier substrate, a second gate dielectric layer formed in a second predetermined gate region, and a second gate electrode layer formed on the second gate dielectric layer; A bonding insulating layer is formed on the surface of the first stacked structure away from the second stacked structure; A substrate is bonded to the bonding insulating layer. The alignment error between the first transistor structure and the second transistor structure in the direction perpendicular to the substrate is -0.5µm to 0.5µm.

4. The two-dimensional semiconductor stacked device structure according to claim 3, characterized in that: The material of the first two-dimensional semiconductor layer includes one of MoS2, MoTe2, WSe2, WS2, MoSe2, SnS2, GeAs2, Bi2Te3, GeSe, GeSb2, Sb2Te3, SnS, TiS3, h-BN, graphene, and black phosphorus. The material of the second two-dimensional semiconductor layer includes one of MoS2, MoTe2, WSe2, WS2, MoSe2, SnS2, GeAs2, Bi2Te3, GeSe, GeSb2, Sb2Te3, SnS, TiS3, h-BN, graphene, and black phosphorus. The conductivity type of the first two-dimensional semiconductor layer is N-type or P-type, and the conductivity type of the second two-dimensional semiconductor layer is N-type or P-type.

5. The two-dimensional semiconductor stacked device structure according to claim 3, characterized in that: The thickness of the first two-dimensional semiconductor layer is 1 to 10 atomic layers, and the thickness of the second two-dimensional semiconductor layer is 1 to 10 atomic layers.

6. The two-dimensional semiconductor stacked device structure according to claim 3, characterized in that: The material of the first interlayer dielectric layer includes one or more of Al2O3, SiO2, ZrO2, TiO2, La2O3, SiOCH, SiOC, h-BN, Si3N4, benzocyclobutene, parylene, and polyimide; the material of the second interlayer dielectric layer includes one or more of Al2O3, SiO2, ZrO2, TiO2, La2O3, SiOCH, SiOC, h-BN, Si3N4, benzocyclobutene, parylene, and polyimide; the thickness of the first interlayer dielectric layer is 150nm~500nm, and the thickness of the second interlayer dielectric layer is 150nm~500nm.

7. The two-dimensional semiconductor stacked device structure according to claim 3, characterized in that: The second interlayer dielectric layer is covalently bonded to the first interlayer dielectric layer.

Images