A facula emission gallium nitride VCSEL laser chip and an epitaxial defect suppression preparation method thereof

Abstract

The application provides a surface-emitting gallium nitride VCSEL laser chip and an epitaxial defect suppression preparation method thereof, relates to the technical field of laser chips, and comprises a substrate, a low-temperature nucleation layer, a high-temperature recovery layer, a stress regulation type nano mask composite defect blocking layer, an n-type nitride DBR reflector, an active region and a polarization enhancement type tunnel junction and the like. The defect blocking layer adopts an in-situ silicon nitride nano porous mask layer in cooperation with an aluminum gallium nitride / gallium nitride stress compensation superlattice layer, penetrative dislocations are annihilated through pulse type lateral epitaxial overgrowth, the n-type nitride DBR reflector adopts an AlInN / GaN lattice matching material system combined with a hydrogen etching interruption modification technology, zero crack and high reflectivity thick film growth are realized, the top uses a polarization enhancement type tunnel junction to replace ITO, the hole tunneling probability is enhanced by using the piezoelectric polarization in InGaN, low working voltage, absorption loss-free high-efficiency current injection are realized, the dislocation density and the device voltage are significantly reduced, and the epitaxial wafer yield and the photoelectric conversion efficiency are improved.

Description

TECHNICAL FIELD

[0001] The application relates to the technical field of laser chips, in particular to a surface-emitting gallium nitride VCSEL laser chip and an epitaxial defect suppression preparation method thereof. BACKGROUND

[0002] According to a high-beam-quality VCSEL structure and a preparation method disclosed in Chinese Patent No. CN114300939A, a VCSEL chip epitaxial structure comprises P-type DBR layers, an oxidation layer, P-type waveguide layers, semiconductor multi-quantum well layers, N-type waveguide layers, N-type DBR layers and substrate layers arranged in sequence from top to bottom; a photonic crystal structure is etched on the upper surface of the P-type DBR layer, and an ion implantation current suppression area is formed on the side surface through ion implantation; and an oxidation hole is formed in the middle of the oxidation layer; and an optical resonance external cavity is arranged on the top or bottom of the VCSEL chip epitaxial structure. The current limiting effect (oxidation hole + ion implantation current suppression area) in the VCSEL device and the optical limiting effect (photonic crystal structure) are decoupled, a determined correlation between light emitting units is established through the increase of the optical resonance external cavity, the laser beam quality is improved, and finally narrow-line-width high-beam-quality laser is output.

[0003] According to a VCSEL chip, a preparation method thereof and a VCSEL laser disclosed in Chinese Patent No. CN117913659A, the chip comprises a substrate, N-type limiting layers, active layers and P-type limiting layers which are stacked in sequence on the substrate, and a light-emitting layer which is arranged on the P-type limiting layer and is provided with a light-emitting port structure for regulating reflectivity of the chip on the side surface of the light-emitting layer away from the P-type limiting layer, wherein the light-emitting port structure is a surface microstructure formed on the surface of the light-emitting layer through etching. The light-emitting layer with the surface microstructure is made on the P-type limiting layer, so that the near-field distribution and the far-field distribution of the light field can be adjusted, and the technical problem that the output power of the VCSEL chip is reduced when the aperture of the oxidation hole is reduced to a preset value in the prior art to realize the application of single-mode VCSEL is solved.

[0004] The above patent documents and prior art have the following technical problems in use:

[0005] Problem one, when gallium nitride (GaN) is grown on a sapphire or other hetero-substrate, a large number of penetrating dislocations will be generated due to lattice mismatch, these dislocations directly extend upwards like “cracks”, pass through the light-emitting area (quantum well), become non-radiative recombination centers, and result in that the laser cannot emit light or has extremely low efficiency;

[0006] Problem two, the VCSEL needs a lower mirror (DBR) with very high reflectivity (>99%), usually more than 40 pairs of aluminum indium nitride / gallium nitride (AlInN / GaN) or aluminum gallium nitride / gallium nitride (AlGaN / GaN) layers need to be grown, such thick film growth will accumulate huge tensile stress or compressive stress, causing the wafer to bend like a potato chip, even directly crack, resulting in device scrap;

[0007] Problem three, the traditional structure uses indium tin oxide (ITO) as a transparent electrode, but ITO has light absorption loss in the blue-violet light band, and the p-type GaN has poor conductivity, and the current is difficult to diffuse. SUMMARY

[0008] Technical problems to be solved:

[0009] In view of the defects of the prior art, the present application provides a surface emitting gallium nitride VCSEL laser chip and an epitaxial defect suppression preparation method thereof, which solves the technical problems existing in the prior art.

[0010] Technical scheme:

[0011] To achieve the above purpose, the present application is realized by the following technical scheme: a surface emitting gallium nitride VCSEL laser chip, the laser chip comprises a substrate, a low-temperature nucleation layer, a high-temperature recovery layer, a stress regulation type nano mask composite defect blocking layer, an n-type nitride DBR mirror, an n-type cavity length adjusting layer, an indium gallium nitride / gallium nitride multi-quantum well active region, a p-type electron blocking layer, a p-type waveguide layer and a polarization enhancement type tunnel junction which are sequentially grown on the surface of the substrate, the stress regulation type nano mask composite defect blocking layer is located between the high-temperature recovery layer and the n-type nitride DBR mirror, and the stress regulation type nano mask composite defect blocking layer structure comprises an in-situ silicon nitride nano porous mask layer directly covering the surface of the high-temperature recovery layer and an aluminum gallium nitride / gallium nitride stress compensation superlattice layer grown on the in-situ silicon nitride nano porous mask layer, a p-face dielectric DBR mirror and a p-face ring electrode are arranged on the upper surface of the polarization enhancement type tunnel junction, the in-situ silicon nitride nano porous mask layer forms randomly distributed nano pores on the surface of the high-temperature recovery layer by discontinuous deposition, and the aluminum gallium nitride / gallium nitride stress compensation superlattice layer is laterally overgrown and merged into a film through the nano pores to block the penetrating dislocations from the substrate.

[0012] Preferably, the aluminum gallium nitride / gallium nitride stress compensation superlattice layer is composed of 10 to 20 periods of sublayers alternately stacked, wherein the Al component x linearly gradually changes from 0.05 to 0.20 along the growth direction, and the thickness of each period of sublayers is less than The thickness of the sublayer is to pre-stress compensate the n-type nitride DBR mirror grown above while blocking dislocations.

[0013] Preferably, the polarization enhanced tunnel junction comprises a heavily doped n-type indium gallium nitride layer and a heavily doped p-type gallium nitride layer, the heavily doped n-type indium gallium nitride layer, a piezoelectric polarization electric field is generated by introducing In component, the direction of the piezoelectric polarization electric field is consistent with the direction of built-in electric field, so as to enhance the hole tunneling probability, the polarization enhanced tunnel junction serves as a hole injection source and has a current spreading function.

[0014] Preferably, the n-type nitride DBR mirror adopts an aluminum indium nitride / gallium nitride lattice matched material system, the In component in the aluminum indium nitride layer is controlled to be between 17% and 18% to match the gallium nitride lattice, and the n-type nitride DBR mirror has 30 to 50 pairs.

[0015] Preferably, the indium gallium nitride / gallium nitride multi-quantum well active region adopts a trapezoidal quantum well structure, a y-component gradient layer with a thickness of 1 nm to 2 nm is inserted between the indium gallium nitride quantum well and the gallium nitride quantum barrier, and the y component continuously changes at the interface to reduce the quantum confinement Stark effect caused by the polarization electric field.

[0016] Preferably, the epitaxial defect suppression preparation method comprises the following steps:

[0017] Sp1: high-temperature heat treatment is performed on the substrate to remove surface oxides and impurities;

[0018] Sp2: a low-temperature nucleation layer is grown on the surface of the substrate, and then a high-temperature recovery layer is grown by increasing the temperature;

[0019] Sp3: a stress regulation type nano mask composite defect blocking layer is prepared, first, silicon source and ammonia gas are introduced, a non-continuous in-situ silicon nitride nano porous mask layer is formed on the surface of the high-temperature recovery layer by using sub-monolayer deposition technology, then the growth conditions are switched, three-dimensional island nucleation is performed through the nano pores, and the reaction chamber pressure is adjusted to promote lateral merging, thereby forming a flat aluminum gallium nitride / gallium nitride stress compensation superlattice layer;

[0020] Sp4: the n-type nitride DBR mirror is grown on the stress regulation type nano mask composite defect blocking layer;

[0021] Sp5: the n-type cavity length adjusting layer, the indium gallium nitride / gallium nitride multi-quantum well active region, the p-type electron blocking layer and the p-type waveguide layer are sequentially grown;

[0022] Sp6: the polarization enhanced tunnel junction is grown, and in-situ thermal annealing is performed after the growth to activate.​

[0023] Sp7: complete p-plane medium DBR mirror deposition and electrode fabrication process.

[0024] Preferably, the specific process of forming a discontinuous in-situ silicon nitride nano-porous mask layer in Sp3 is: keeping the reaction chamber temperature at 850-950℃, passing in silane flow of 50-100sccm, ammonia flow of 2000-4000sccm, and growth time controlled at 30-60 seconds, so that the silicon nitride has a surface coverage of 60-80%, thereby naturally forming irregular nanopores as windows for subsequent epitaxy.

[0025] Preferably, the lateral merging process of the aluminum gallium nitride / gallium nitride stress compensation superlattice layer in Sp3 adopts a pulsed growth mode: first growing sublayers under high pressure conditions of 200-300Torr to enhance lateral mobility, and then growing gallium nitride sublayers under low pressure conditions of 70-100Torr to flatten the surface, and so on until the total thickness of the superlattice layer reaches 300-500nm.

[0026] Preferably, in Sp4, when growing the n-type nitride DBR mirror, after growing each pair of aluminum indium nitride / gallium nitride layers, a growth interruption of 10-20 seconds is introduced, and a trace amount of hydrogen is passed in during the interruption to etch and modify the surface, so as to remove metal droplets formed by surface indium segregation.

[0027] Preferably, the growth of the polarization-enhanced tunnel junction in Sp6 adopts an incremental doping technique, in which the gallium source is turned off and the magnesium source is continuously turned on for 5-10 seconds during the growth of the heavily doped p++ type indium gallium nitride layer, thereby forming a locally high-concentration magnesium doped layer at the interface, and the subsequent in-situ thermal annealing temperature is set to 700-750℃, and the carrier gas is a pure nitrogen environment.

[0028] Beneficial effects:

[0029] The present application provides a surface-emitting gallium nitride VCSEL laser chip and an epitaxial defect suppression preparation method thereof, which has the following beneficial effects:

[0030] 1. The present application solves the problem of penetrating dislocation by setting stress regulation type nano mask composite defect blocking layer, the structure contains in-situ silicon nitride nano porous mask layer, random distributed nano holes are formed by discontinuous deposition, most of the vertical extension of dislocation is physically blocked, then, aluminum gallium nitride / gallium nitride stress compensation superlattice layer promotes lateral epitaxial overgrowth and merges into film by using pulse growth mode, the remaining dislocation lines are forced to bend and annihilate each other, the present application greatly reduces the density of penetrating dislocation in the crystal, thereby significantly reducing the number of non-radiative recombination centers, and effectively improving the light emitting efficiency and laser gain of indium gallium nitride / gallium nitride multiple quantum well active region.

[0031] 2. The present application solves the problem of stress accumulation and cracking in thick film DBR growth by using aluminum indium nitride / gallium nitride lattice matched material system, the indium In component in the aluminum indium nitride layer is accurately controlled between 17% and 18%, perfect matching with the lattice constant of gallium nitride is realized, and the accumulated tensile stress in thick film growth is fundamentally eliminated, at the same time, during the DBR growth process, a growth interruption is introduced after each pair of layers is grown, and a small amount of hydrogen is introduced during the interruption to etch and modify the surface, which effectively removes the metal droplets formed by surface indium segregation and guarantees the smoothness of the interface, which completely avoids the bending and cracking of the wafer caused by stress accumulation, and ensures that the n-type nitride DBR mirror has very high reflectivity.

[0032] 3. The present application uses a polarization enhanced tunnel junction to completely replace the ITO transparent electrode, the tunnel junction is composed of a heavily doped type indium gallium nitride layer and a heavily doped type gallium nitride layer, wherein, The indium gallium nitride layer uses the introduced indium component to generate a strong piezoelectric polarization electric field, the direction of the electric field is consistent with the direction of the built-in electric field, which greatly compresses the hole tunneling barrier at the interface, and at the same time, the local high concentration magnesium doped layer is formed at the interface by combining the incremental doping technology, which greatly enhances the hole tunneling probability, the present application eliminates the light absorption loss of ITO, significantly reduces the working voltage of the laser, and improves the electro-optical conversion efficiency and current expansion function. BRIEF DESCRIPTION OF DRAWINGS

[0033] Fig. 1 is a preparation method step diagram of the epitaxial defect suppression of the present application;

[0034] Fig. 2 is a front view of the laser chip of the present application.

[0035] Wherein: 1, substrate; 2, low-temperature nucleation layer; 3, high-temperature recovery layer; 4, stress-regulated nano-mask composite defect blocking layer; 401, in-situ silicon nitride nano-porous mask layer; 402, aluminum gallium nitride / gallium nitride stress compensation superlattice layer; 5, n-type nitride DBR mirror; 6, n-type cavity length adjustment layer; 7, indium gallium nitride / gallium nitride multi-quantum well active region; 8, p-type electron blocking layer; 9, p-type waveguide layer; 10, polarization-enhanced tunnel junction; 11, p-face dielectric DBR mirror; 12, p-face ring electrode. DETAILED DESCRIPTION

[0036] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work fall within the scope of protection of the present application. Specific embodiment one:

[0038] As shown in the drawing, Figs. 1-2 A surface-emitting gallium nitride VCSEL laser chip, the laser chip comprising a substrate 1, a low-temperature nucleation layer 2, a high-temperature recovery layer 3, a stress-regulated nano-mask composite defect blocking layer 4, an n-type nitride DBR mirror 5, an n-type cavity length adjustment layer 6, an indium gallium nitride / gallium nitride multi-quantum well active region 7, a p-type electron blocking layer 8, a p-type waveguide layer 9, and a polarization-enhanced tunnel junction 10, which are sequentially grown on the surface of the substrate 1. The stress-regulated nano-mask composite defect blocking layer 4 is located between the high-temperature recovery layer 3 and the n-type nitride DBR mirror 5, and the structure of the stress-regulated nano-mask composite defect blocking layer 4 comprises an in-situ silicon nitride nano-porous mask layer 401 directly covering the surface of the high-temperature recovery layer 3 and an aluminum gallium nitride / gallium nitride stress compensation superlattice layer 402 grown on the in-situ silicon nitride nano-porous mask layer 401. A p-face dielectric DBR mirror 11 and a p-face ring electrode 12 are provided on the upper surface of the polarization-enhanced tunnel junction 10. The in-situ silicon nitride nano-porous mask layer 401 forms randomly distributed nano-pores on the surface of the high-temperature recovery layer 3 through non-continuous deposition. The aluminum gallium nitride / gallium nitride stress compensation superlattice layer 402 is laterally overgrown and merged into a film through the nano-pores to block penetrating dislocations from the substrate 1.

[0039] The substrate 1 is the physical basis of the whole laser chip, and the substrate 1 is preferably a C-plane sapphire material. The sapphire process is mature, low in cost, and good in light transmission. Although there is a lattice mismatch of about 17% and a large difference in thermal expansion coefficient between sapphire and gallium nitride (GaN), the mature processing technology and excellent light transmission make it the first choice, and this problem is solved through subsequent special structures. A low-temperature nucleation layer 2 is first epitaxially grown on the surface of the substrate 1. The layer is usually an amorphous or polycrystalline gallium nitride or aluminum nitride (AlN) film, with a thickness of 20-30 nm. The low-temperature nucleation layer 2 serves as a buffer layer to alleviate the large lattice mismatch between the substrate 1 and the GaN, providing high-density and uniform nucleation centers for subsequent high-temperature growth, effectively covering the heterogeneous substrate 1, starting the subsequent single-crystal epitaxy, and then growing a high-temperature recovery layer 3, which is undoped gallium nitride, with a growth temperature usually higher than 1,000 degrees Celsius. The low-temperature nucleation layer 2 is combined at high temperature to form a continuous single-crystal film, providing a relatively flat interface for the growth of the subsequent core structure, but its surface still has a large number of penetrating dislocations originating from the substrate.

[0040] The stress regulation type nano mask composite defect blocking layer 4 is located between the high temperature recovery layer 3 and the n-type nitride DBR mirror 5, and is the core of the scheme to realize high-quality crystal growth. It contains two key structure layers: an in-situ silicon nitride (SiNx) nano porous mask layer 401 and an aluminum gallium nitride (AlGaN) / gallium nitride (GaN) stress compensation superlattice layer 402. The in-situ silicon nitride nano porous mask layer 401 is directly covered on the surface of the high temperature recovery layer 3, and the material is silicon nitride. By precisely controlling the flow of silicon source and ammonia gas and the growth time, the sub-monolayer deposition technology is used to form in-situ in the high temperature epitaxial furnace. The growth time is strictly controlled within thirty to sixty seconds, and the coverage of silicon nitride on the surface is ensured within 60%-80%. This non-continuous deposition intentionally forms randomly distributed nanoscale holes on the surface of the high temperature recovery layer, instead of a continuous film. The silicon nitride layer has a physical blocking effect on penetrating dislocations. Most of the dislocations are blocked when they encounter the layer. Those dislocations that are not blocked are limited to the nanohole area and become the growth point of subsequent lateral epitaxy. SiNx has a reverse wetting effect on GaN, and GaN is difficult to nucleate directly on SiNx. It can only grow out of the nanoholes naturally formed on the SiNx layer. A large number of penetrating dislocations in the high temperature recovery layer 3 are blocked by SiNx and cannot extend upward. Only a few dislocations at the hole site can pass through, thereby physically filtering most of the defects; the aluminum gallium nitride / gallium nitride stress compensation superlattice layer 402 is grown on the in-situ silicon nitride nano porous mask layer 401. The growth process adopts a pulse type lateral overgrowth mode. After the gallium nitride crystal nucleates through the nanoholes of the mask layer, the gas pressure and temperature of the reaction chamber are precisely adjusted to force it to expand laterally and merge into a film. During this lateral epitaxial overgrowth process, the originally vertically upward penetrating dislocation lines will bend by ninety degrees due to the change of growth direction, and will collide and annihilate each other during lateral expansion and merging, thereby reducing the dislocation density above the superlattice layer to The following is significantly lower than the conventional method. The superlattice layer is composed of 10 to 20 periods of The sub-layers are alternately stacked, that is, ten to twenty periods of aluminum gallium nitride sub-layers and gallium nitride sub-layers are alternately stacked, wherein the Al component x of the aluminum gallium nitride sub-layer linearly gradually changes from 0.05 at the bottom to 0.20 at the top along the growth direction, and in addition, the thickness of the aluminum gallium nitride sub-layer of each period is designed to be smaller than the thickness of the gallium nitride sub-layer. This structure design realizes dislocation blocking, and through accurate control of the material component and thickness, a gradually changing stress field is introduced, which pre-stress compensates the tensile stress generated by the thick n-type nitride DBR mirror 5 to be grown above, effectively avoiding the crystal cracking that may be caused by thick film growth. Specifically, the n-type nitride DBR mirror 5 above is usually composed of a material with a high Al component, which will produce a great tensile stress to cause cracking. The aluminum gallium nitride / gallium nitride stress compensation superlattice layer 402 generates a compressive stress gradient by introducing a gradually changing Al component, which is like a reverse spring, pre-compensating the tensile stress generated when the n-type nitride DBR mirror 5 is grown subsequently, and ensuring that the epitaxial wafer is flat and does not crack.

[0041] The n-type nitride DBR mirror 5 (n-type nitride distributed Bragg reflector) is the lower optical reflection interface, and the number thereof is required to be thirty to fifty pairs to ensure that the reflectivity is higher than 99.9%. The n-type nitride DBR mirror 5 adopts an aluminum indium nitride (AlInN) / gallium nitride (GaN) lattice matching material system, which is a crucial technical choice: the indium (In) component in the aluminum indium nitride layer is strictly controlled to be between 17% and 18%, and within this component range, the lattice constant of the aluminum indium nitride can be perfectly matched with the lattice constant of the gallium nitride. Since lattice matching is achieved, stress will not accumulate when growing dozens of pairs of mirrors, completely eliminating the cracking risk caused by excessive stress of traditional high-aluminum-component aluminum gallium nitride DBR, ensuring the yield and reliability of the device, which is the physical basis for achieving high reflectivity (R>99.9%), and the refractive index difference between AlInN and GaN is larger than that between AlGaN and GaN, so that higher reflectivity can be obtained with fewer pairs, thereby widening the stopband width of the reflection spectrum; the material of the n-type cavity length adjusting layer 6 is n-type doped GaN, which accurately adjusts the total optical length of the laser resonant cavity to satisfy the standing wave condition, that is, the antinode of the optical field standing wave is accurately overlapped with the position of the active region quantum well, so as to obtain the maximum optical gain.

[0042] The indium gallium nitride (InGaN) / gallium nitride (GaN) multi-quantum well active region 7 is responsible for photon generation, adopts a trapezoidal quantum well structure, including an InGaN well layer, a GaN barrier layer, and a 1nm-2nm gradient layer (GRADIENT LAYER) between the two. The indium gallium nitride (InGaN) / gallium nitride (GaN) multi-quantum well active region 7 is responsible for photon generation, adopts a trapezoidal quantum well structure, including an InGaN well layer, a GaN barrier layer, and a 1nm-2nm gradient layer (GRADIENT LAYER) between the two. The In component y of the gradual change layer is continuously changed along the growth direction to reduce the quantum confined Stark effect caused by the polarization electric field. The nitride material has a strong polarization effect, which can generate a huge built-in electric field in the quantum well, causing the wave functions of electrons and holes to separate in space (one to the left and one to the right), reducing the recombination light emission efficiency, which is called the quantum confined Stark effect (QCSE) effect. This gradual change layer design aims to reduce the quantum confined Stark effect caused by the polarization electric field. By introducing the gradual change layer with continuously changing In component, the originally steep square well interface is changed into a gentle trapezoidal interface, which effectively “softens” the band bending caused by the polarization electric field, significantly increasing the overlap of the wave functions of electrons and holes, thereby greatly improving the light emission efficiency and gain.

[0043] The material of the p-type electron blocking layer 8 is a high-Al component p-type AlGaN, which forms a higher barrier by using a wide band gap to prevent the injected electrons from “flying over” the quantum well and leaking to the p region, forcing the electrons to stay in the quantum well for recombination; the material of the p-type waveguide layer 9 is p-type GaN, which limits the optical field and conducts holes; the polarization enhanced tunnel junction 10 is located above the p-type waveguide layer 9, which is the top layer structure of semiconductor epitaxy, and is the key to achieving high-efficiency current injection. The detailed composition is: the lower layer is a heavily doped type indium gallium nitride (InGaN) layer, and the upper layer is a heavily doped type gallium nitride (GaN) layer. Traditional structures use indium tin oxide (ITO) for conduction, but ITO absorbs light. The polarization enhanced tunnel junction 10 replaces the traditional high-loss, high-absorption ITO transparent electrode, changes the p-type contact to an n-type contact, allows current to be injected through tunneling effect, and at the same time solves the problem of poor conductivity of p-type gallium nitride. In the heavily doped type indium gallium nitride layer, by introducing an indium (In) component, a strong piezoelectric polarization electric field is generated at the p-n junction interface. The direction of the piezoelectric polarization electric field is designed to be consistent with the direction of the built-in electric field in the junction region. The superposition of the two greatly compresses the potential barrier width required for hole-electron tunneling, enhancing the hole tunneling probability. Therefore, as a hole injection source, this structure can achieve high-efficiency current injection with extremely low series resistance and excellent current spreading function. Electrons can easily tunnel from the n-layer valence band to the p-layer conduction band (i.e. hole injection), greatly reducing voltage loss and resistance, and achieving high-efficiency current injection without absorption.

[0044] The upper surface of the polarization enhanced tunnel junction 10 is provided with a p-plane dielectric DBR mirror 11 and a p-plane ring electrode 12. The p-plane dielectric DBR mirror 11 is formed by alternately stacking insulating dielectric materials such as silicon dioxide / titanium dioxide, and is located at the center light-emitting area on the surface of the polarization enhanced tunnel junction 10, serving as an upper mirror and forming a resonant cavity together with the n-type nitride DBR mirror 5 below. Since it is a dielectric material, there is no need for electrical conduction, and it can be designed to have a very high reflectivity and no absorption. Its advantage is that, as a non-semiconductor material, it can avoid light absorption, and a higher refractive index difference can be achieved through a precise deposition process, thereby achieving the required light-emitting reflectivity with fewer logarithms. The n-type gallium nitride (GaN) layer is in contact with the polarization enhanced tunnel junction 10, forming a good ohmic contact and serving as a current injection end, thereby solving the problem of difficult contact with the p-type GaN. Specific embodiment two:

[0046] As shown in Figs. 1-2 the above specific embodiments, the following content is further disclosed:

[0047] The preparation method is realized in a metal organic chemical vapor deposition (MOCVD) reaction furnace, and all operations are completed by accurately controlling the temperature, pressure, gas flow and time sequence logic of the reaction chamber. The epitaxial defect suppression preparation method of the laser chip includes the following steps:

[0048] Sp1: high-temperature heat treatment is performed on the substrate 1 to remove surface oxides and impurities;

[0049] High-temperature heat treatment of the substrate 1: the high-temperature heat treatment of the substrate 1 is a pre-purification step before epitaxy. After the substrate 1 is loaded into the reaction chamber, high-purity hydrogen gas is introduced into the reaction chamber as a carrier gas, and the substrate temperature is accurately raised to between 1,050 degrees Celsius and 1,150 degrees Celsius. This temperature range is necessary to ensure surface atomic rearrangement and oxide vaporization. The heat treatment time is set to 10-15 minutes, which is sufficient to remove oxides and organic impurities naturally formed on the surface of the substrate 1 or adsorbed during transportation. The high-temperature hydrogen gas flow performs thermal etching and atmosphere purification on the surface of the substrate 1. Hydrogen is a strong reducing atmosphere that can efficiently convert residual silane or oxynitride on the surface of the sapphire substrate 1 into volatile substances at this high temperature. The success of this operation directly affects the nucleation quality of the first layer of epitaxy. During the operation, the temperature fluctuation range is accurately monitored by an in-situ high-temperature thermometer, and the fluctuation range should not exceed ±1 degree Celsius. After the treatment is completed, the surface of the substrate 1 is ensured to be smooth and pollution-free at the atomic scale, which is the basis for subsequent high-quality epitaxial growth.

[0050] Sp2: grow low-temperature nucleation layer 2 on the surface of substrate 1, and then grow high-temperature recovery layer 3 by increasing the temperature;

[0051] Growth of low-temperature nucleation layer 2 and high-temperature recovery layer 3: after the heat treatment is completed, the temperature in the reaction chamber is quickly reduced to 500-550 degrees Celsius, the carrier gas is switched to nitrogen, trimethyl gallium (TMGa) and ammonia (NH3) are introduced, , the growth of low-temperature nucleation layer 2 is started, the thickness is controlled at 20-30 nanometers, too thin cannot effectively cover the substrate, too thick introduces too many defects, this process requires very high V / III molar flow ratio, after the growth is completed, the TMGa supply is stopped, the temperature is quickly increased to 1,000-1,050 degrees Celsius at a rate of 50-100 degrees Celsius per minute to prevent the low-temperature layer from decomposing during the temperature increase, TMGa and are re-introduced, and high-temperature recovery layer 3 is grown, the thickness of this layer is usually about 1 micrometer to form high-quality single-crystal gallium nitride;

[0052] Low-temperature nucleation layer 2 serves as a lattice transition layer to relieve the lattice mismatch between substrate 1 and the main body of gallium nitride, to achieve rapid and complete coverage of the surface of substrate 1, and then to recover the growth at high temperature, which is to recrystallize the low-temperature layer, to promote the recovery of the crystal structure by heat energy, to reduce the density of dislocation stacking, to improve the crystal quality of high-temperature recovery layer 3, and to prepare for the core defect inhibition layer, during the growth process, the in-situ reflection pyrometer is used to monitor the changes in film thickness and surface morphology, and the later high-resolution X-ray diffraction should show a sharp main peak, proving that the crystal quality is good.

[0053] Sp3: prepare stress-regulated nano-mask composite defect blocking layer 4, first introduce silicon source and ammonia, use sub-monolayer deposition technology to form non-continuous in-situ silicon nitride nano-porous mask layer 401 on the surface of high-temperature recovery layer, then switch the growth conditions, perform three-dimensional island nucleation through nano-pores, and adjust the reaction chamber pressure to promote lateral merging, to form flat aluminum gallium nitride / gallium nitride stress compensation superlattice layer 402;

[0054] Preparation of stress-regulated nano-mask composite defect blocking layer 4: this step is the core of the preparation method, and is divided into mask layer deposition and superlattice lateral overgrowth:

[0055] Details of forming in-situ silicon nitride nano-porous mask layer 401: stabilize the temperature in the reaction chamber at 850-950 degrees Celsius, and maintain the pressure at a low level, which is the best balance temperature for chemical vapor deposition of silicon nitride on the surface of gallium nitride while avoiding thermal decomposition of the surface of gallium nitride, accurately introduce silane (SiH4) flow rate of 50-100 standard cubic centimeters per minute, and ammonia (NH3) The flow rate is two to four thousand standard cubic centimeters per minute, the growth time is controlled in an extremely short time window of thirty to sixty seconds, as soon as the time is up, the silane supply is immediately stopped, and nitrogen blowing is carried out; this process utilizes the sub-monolayer non-continuous deposition of silane on the surface of gallium nitride, by accurately controlling the time, the surface coverage of silicon nitride is just between sixty to eighty percent, the growth time is locked in thirty to sixty seconds, which is a critical time window calibrated by a large number of pre-experiments, the target is to ensure that the silicon nitride on the surface of the high-temperature recovery layer 3 reaches sixty to eighty percent coverage, and deliberately forms a random distribution of uncovered areas, i.e. nanoholes, if the coverage is less than sixty percent, the defect filtering efficiency is insufficient, if the coverage is close to one hundred percent, it will completely block the subsequent epitaxial growth, this precise sub-monolayer non-continuous deposition is the fundamental means to realize the physical filtering of dislocations;

[0056] Aluminum gallium nitride / gallium nitride stress compensation superlattice layer 402 lateral merging process: this process adopts pulse growth mode, cycles ten to twenty times, until the total thickness of the superlattice layer reaches three to five hundred nanometers, which specifically includes:

[0057] Growth of aluminum gallium nitride sub-layer (enhance lateral mobility): adjust the reaction chamber pressure to a high pressure condition of two to three hundred torr, input trimethylaluminum (TMAl), trimethylgallium (TMGa) and , high pressure can effectively inhibit the thermal decomposition of gas precursors, enhance the lateral mobility of growth substances on the surface, and benefit lateral growth merging, this improvement of lateral mobility is the key driving force to promote the lateral merging of gallium nitride crystal islands above the mask holes;

[0058] Growth of gallium nitride sub-layer (fill in the surface): then quickly switch the reaction chamber pressure to a low pressure condition of seventy to one hundred torr, close the TMAl supply, and only input TMGa and , low pressure is beneficial to improve the growth rate and improve the flatness of the growth interface, which is used to fill in the depression above the nanohole and ensure the surface flatness, and the time of each layer is accurately controlled, so that the thickness of the aluminum gallium nitride sub-layer is less than that of the gallium nitride sub-layer;

[0059] By periodically switching between high and low pressure, the surface diffusion and gas phase reaction of growth substances can be effectively controlled, the control logic of this process is based on the accurate synchronous switching of time and pressure, ensuring that in ten to twenty growth cycles, the total thickness of the superlattice layer reaches the design value of three to five hundred nanometers, realizing the lateral annihilation of defects and the gradual compensation of stress, forcing the crystal to change from vertical three-dimensional island growth to lateral two-dimensional merging growth, realizing dislocation bending and annihilation, the determination scheme relies on in-situ reflection spectrometer to monitor the reflection signal, ensuring that the thickness of each superlattice cycle is consistent with the target design value.

[0060] Sp4: An n-type nitride DBR mirror 5 is grown on a stress-controlled nanomask composite defect blocking layer 4;

[0061] Growth of n-type nitride DBR mirror 5: The temperature is stabilized at around 850 degrees Celsius, which is the optimal bonding temperature for indium. Thirty to fifty pairs of aluminum indium nitride / gallium nitride layers are then grown in a cyclic manner. Growth interruption and surface modification: After each pair of aluminum indium nitride / gallium nitride layers is grown, a growth interruption of ten to twenty seconds must be introduced. During the interruption, all metal sources are turned off, and a small amount of hydrogen is introduced to etch and modify the surface. Then, the next pair is grown. The hydrogen modification during the growth interruption is crucial. It can remove indium metal droplets that have segregated on the surface of the aluminum indium nitride layer due to low-temperature growth. Hydrogen, as a strong etchant, can selectively re-vaporize and remove these indium metal droplets. At the same time, it performs atomic-level modification on the gallium nitride surface, thereby ensuring the smoothness of the interface and optical quality, and improving the reflectivity and uniformity of the film. The determination method relies on in-situ reflectivity monitoring to ensure that the peak and valley values ​​and periodicity of reflectivity are accurate.

[0062] Sp5: n-type cavity length adjustment layer 6, indium gallium nitride / gallium nitride multi-quantum well active region 7, p-type electron blocking layer 8 and p-type waveguide layer 9 are grown sequentially.

[0063] Growth of n-type cavity length adjustment layer 6 to p-type waveguide layer 9: After completing the growth of n-type nitride DBR mirror 5, the n-type cavity length adjustment layer 6 is grown first. The temperature is precisely adjusted to about 750 degrees Celsius, and the growth of indium gallium nitride / gallium nitride multi-quantum-well active region 7 begins. This process requires extremely small temperature fluctuations to ensure the uniformity of the indium composition. During the growth process, a gradient layer of one to two nanometers is precisely inserted between the quantum well and the quantum barrier by pulsed or continuous switching of the source gas. After the active region growth is completed, the temperature is rapidly increased to about 950 degrees Celsius to grow the p-type electron blocking layer 8 and the p-type waveguide layer 9, and magnesium bis(oxo) is continuously introduced. The p-type doping is performed; the growth control logic of the active region relies on precise temperature and gas flow timing control. The determination scheme is to perform photoluminescence (PL) testing after epitaxial growth is completed to confirm that the error between the emission wavelength and the design wavelength is less than one nanometer and the emission intensity is high.

[0064] Sp6: Grown polarization-enhanced tunnel junction 10, and activated by in-situ thermal annealing after growth;

[0065] Polarization-enhanced tunnel junction 10 growth and activation: Continue high-temperature growth and heavy doping For indium gallium nitride (IGa) layers, a delta doping operation is performed: near the end of the layer's growth, a high-speed valve operation is executed to shut off the trimethylgallium (TMGa) supply, while maintaining the magnesium dicerode (MgCd) supply. ) continuously for five to ten seconds, which forms a super-high concentration magnesium doping peak at the interface with only a few atomic layers thick, growing the heavily doped Gallium Nitride layer, in-situ thermal annealing activation: stop all growth gas supply, switch the carrier gas to pure nitrogen environment, and set the reaction chamber temperature to seven hundred to seven hundred and fifty degrees Celsius, keep the temperature for ten to twenty minutes of thermal annealing;

[0066] Incremental doping forms a very thin local high concentration magnesium doping layer at the interface by instantaneously over-supplying magnesium source, which is crucial for forming high-efficiency tunnel junction, thermal annealing operation is to activate passivated magnesium atoms to become electrically active hole source, the use of pure nitrogen is necessary, because at this temperature, if hydrogen is used, hydrogen will combine with magnesium atoms, re-passivating p-type doping, resulting in the failure of the tunnel junction, this operation ensures that the tunnel junction has very low ohmic contact resistance, so as to realize high-efficiency hole injection, the determination scheme is to perform transmission line model (TLM) test on the dedicated test piece after epitaxy, to confirm that the ohmic contact resistance is lower than , which proves that the tunnel junction is successfully formed.

[0067] Sp7: complete p-face dielectric DBR mirror 11 deposition and electrode fabrication process;

[0068] The wafer after epitaxial growth is taken out of the MOCVD reaction furnace and transferred to the post-processing equipment, p-face dielectric DBR mirror 11 deposition: using plasma enhanced chemical vapor deposition (PECVD) or electron beam evaporation and other methods, depositing dielectric layers such as silicon dioxide / titanium dioxide on the surface of the polarization-enhanced tunnel junction 10 to form a mirror, electrode fabrication: using photolithography and dry etching process to form a mesa, expose the n-type layer, and then perform metal evaporation and stripping process to form p-face ring electrode and n-face electrode. Specific embodiment three:

[0070] As shown in Figs. 1-2 , according to the content in the above specific embodiments, the following content is further disclosed:

[0071] The following details the actual operation steps of processing the wafer after epitaxial growth into an independent surface-emitting gallium nitride VCSEL laser chip:

[0072] First stage: pre-treatment and growth of epitaxy;

[0073] Step 1: Substrate 1 cleaning and loading: Before entering the MOCVD reaction chamber, the sapphire substrate 1 is subjected to strict wet chemical cleaning. First, it is cleaned in an ultrasonic cleaner with acetone and isopropyl alcohol to remove organic contaminants. Then, it is cleaned with a mixture of sulfuric acid and hydrogen peroxide to remove metal ions and microparticles. Finally, it is rinsed with deionized water and dried with high-purity nitrogen gas. The cleaned substrate is loaded into a graphite tray and sent to the reaction chamber.

[0074] Step 2: Full-structure epitaxial growth: The MOCVD program is started, and the growth of the low-temperature nucleation layer 2, high-temperature recovery layer 3, stress-regulated nanomask composite defect-blocking layer 4, n-type nitride DBR mirror 5, n-type cavity length adjustment layer 6, indium gallium nitride / gallium nitride multi-quantum well active region 7, p-type functional layer, and polarization-enhanced tunnel junction 10 is completed in sequence according to the parameter settings of Sp1 to Sp6. After the growth is completed, the epitaxial wafer is naturally cooled to room temperature in a nitrogen atmosphere and removed.

[0075] Second stage: Chip patterning process (FAB flow);

[0076] Step 3: Mesa isolation etching: This step aims to etch away the material around the chip to expose the underlying n-type conductive layer, thereby creating an n-face electrode:

[0077] Photolithography definition: Positive photoresist is spun on the surface of the epitaxial wafer, and the first photomask is used for exposure and development, defining a cylindrical or square central light-emitting mesa area. The photoresist in the remaining areas is removed.

[0078] ICP dry etching: An inductively coupled plasma etching device is used, with chlorine gas and boron trichloride as etching gases. The etching depth is strictly controlled to penetrate the top tunnel junction, waveguide layer, and active region, and finally stop at the upper surface of the n-type nitride DBR mirror 5 or inside the n-type cavity length adjustment layer 6.

[0079] Photoresist removal and cleaning: Special photoresist removal liquid is used to remove the remaining photoresist, completing the mesa isolation.

[0080] Step 4: Current-limiting aperture fabrication: To limit the current flow only from the central light-emitting area, the mesa edge needs to be insulated:

[0081] Mask preparation: Thick photoresist is spun again or silicon dioxide hard mask is deposited. Through the second photolithography process, only the light-emitting aperture area with a diameter of about five to ten microns in the center of the mesa is exposed, and the remaining part is protected by the mask.

[0082] Ion implantation: The wafer is sent to an ion implanter, and high-energy hydrogen ions or helium ions are used for implantation. The implanted ions will damage the lattice structure of the unprotected areas, making them become high-resistance insulating regions, thereby forming a current-limiting aperture.

[0083] Annealing repair: After removing the mask, low-temperature rapid thermal annealing is performed to stabilize the implantation damage and prevent leakage;

[0084] Step five: side wall passivation and insulation layer deposition: in order to protect the etched side wall from leakage and oxidation:

[0085] A layer of silicon dioxide insulation passivation layer is deposited on the entire surface using a plasma-enhanced chemical vapor deposition device, with a thickness of about two hundred nanometers to three hundred nanometers. The third photoetching and etching process is used to open the p-side contact window on the top of the mesa and the n-side contact window on the bottom of the mesa, respectively;

[0086] Step six: electrode deposition and alloying: making n-type and p-type ohmic contact electrodes:

[0087] n-side electrode making: the fourth photoetching process is used to expose the underlying n-type layer area, and the electron beam evaporation device is used to deposit titanium, aluminum, nickel, and gold multi-layer metal system, and then the stripping process is performed to form the n-side electrode around the bottom of the mesa;

[0088] p-side electrode making: the fifth photoetching process is used to expose the annular area on the top of the mesa (avoiding the center light emitting hole), and the titanium, gold or nickel, metal system is deposited, and after stripping, the p-side annular electrode is formed;

[0089] Rapid thermal annealing (RTA): under the protection of nitrogen, the wafer is heated to five hundred degrees Celsius to six hundred degrees Celsius, and maintained for thirty seconds to sixty seconds, so that the metal and semiconductor form low-resistance ohmic contact;

[0090] Third stage: optical coating and later testing;

[0091] Step seven: p-side dielectric DBR mirror 11 deposition: this is a key step to form the upper mirror:

[0092] Stripping process preparation: spin-coat photoresist again, use the sixth photoetching plate to expose only the circular light emitting hole area in the center of the mesa and the pad position of the p-electrode and n-electrode (for subsequent stripping protection);

[0093] Dielectric film deposition: use electron beam evaporation or ion beam sputtering device to alternately deposit silicon dioxide and titanium dioxide, usually deposit ten pairs to fifteen pairs, and the center wavelength is strictly aligned with the laser emission wavelength;

[0094] Stripping: immerse the wafer in acetone to remove the photoresist and the excess dielectric film above it, leaving only the circular dielectric DBR mirror column at the center light emitting hole;

[0095] Step eight: thinning, dicing and testing;

[0096] Substrate thinning and polishing: grinding and thinning the wafer back to 100-150 microns and polishing to facilitate heat dissipation and cleavage;

[0097] Dicing and dicing: using laser stealth cutting or diamond cutters to cut along the cutting path between the chips to separate into independent chip particles;

[0098] Probe testing: power-on testing of independent chips on an automatic probe station to screen out good chips with low threshold current, output power up to standard and single spectrum;

[0099] So far, the entire actual preparation process of the surface-emitting gallium nitride VCSEL laser chip from the raw material to the packaged use has been completed. Specific embodiment four:

[0101] As Figs. 1-2 shown, according to the content in the above specific embodiments, the following content is further disclosed:

[0102] In order to verify the technical advantages of the surface-emitting gallium nitride VCSEL laser chip and its epitaxial defect suppression preparation method, three groups of comparative experiments are designed, which are respectively aimed at verifying the crystal quality and defect density, the structural integrity of the DBR mirror and the photoelectric performance of the final device.

[0103] Experiment 1: Comparison of epitaxial crystal quality and dislocation density;

[0104] Purpose of the experiment: to verify the inhibitory effect of the stress regulation type nano mask composite defect blocking layer and the pulse type lateral overgrowth process on the penetrating dislocation;

[0105] Experimental grouping:

[0106] Experimental group A (this application): strictly according to the above preparation method, growing low-temperature nucleation layer 2 and high-temperature recovery layer 3 on sapphire substrate 1, then preparing in-situ silicon nitride nano-porous mask layer 401, and growing aluminum gallium nitride / gallium nitride stress compensation superlattice layer 402 in pulse mode;

[0107] Comparison group B (traditional process): after growing low-temperature nucleation layer 2 and high-temperature recovery layer 3 on the same sapphire substrate 1, without growing silicon nitride mask and superlattice layer, but directly growing ordinary n-type gallium nitride layer with the same thickness in the traditional continuous growth mode;

[0108] Experimental steps:

[0109] The samples of the experimental group A and the comparison group B are put into the same high-resolution X-ray diffractometer (XRD), and the rocking curve scanning is respectively performed to test the full width at half maximum (FWHM) values of the (002) symmetric plane and the (102) asymmetric plane, the smaller the FWHM value is, the higher the crystal order degree is, and the lower the dislocation density is; the sample surface is scanned by using cathodoluminescence (CL) or atomic force microscope (AFM); the number of dark spots (corresponding to dislocations) in the field of view is counted, and the penetrating dislocation density (TDD) is calculated;

[0110] Experimental results:

[0111] Table 1: Comparison table of epitaxial crystal quality and penetrating dislocation density test results

[0112] ;

[0113] The experimental data show that the nano mask combined with the pulse lateral overgrowth technology adopted in the method successfully blocks most of the penetrating dislocations originating from the substrate, and the significant reduction of the (102) plane FWHM directly reflects the significant reduction of the threading dislocations, and the comparison group B maintains a high level of dislocation density due to the lack of effective defect blocking mechanism, and the extremely low dislocation density of the experimental group A lays a solid crystallographic foundation for the subsequent growth of high reflectivity DBR and high internal quantum efficiency active region.

[0114] Experiment two: comparison experiment of DBR reflectivity and crack density

[0115] Experimental purpose: verify the advantages of the lattice-matched AlInN / GaN material system combined with hydrogen etching interruption modification technology in solving thick film cracking and surface roughness;

[0116] Experimental grouping:

[0117] Experimental group A (the application): 45 pairs of AlInN / GaN DBR are grown on the template optimized in experiment one, the In component in AlInN is 17.5%, and 15 seconds of interruption is introduced after each pair of growth and hydrogen is introduced for modification;

[0118] Comparison group C (traditional high-reflectivity DBR): a traditional AlN / GaN or high-component AlGaN / GaN DBR system is adopted, and the same number of pairs (45 pairs) are grown, and the growth process is continuous without hydrogen etching interruption;

[0119] Experimental steps:

[0120] The surfaces of the two groups of samples were observed using differential interference contrast microscopy (DIC), and the number of cracks in a unit area was counted; the reflectance spectrum of the samples was tested using a UV-visible spectrophotometer, and the peak reflectance at the center wavelength was recorded; the surface of the top layer of the DBR was scanned using atomic force microscopy (AFM), and the surface morphology and indium precipitation (metal droplets) were analyzed.

[0121] Experimental results:

[0122] Table 2: Comparison table of optical performance and structural integrity of DBR mirrors

[0123] ;

[0124] The comparison group C accumulated a huge tensile stress due to the material lattice mismatch, resulting in severe surface cracking. The cracks not only scattered light and reduced reflectivity, but also caused device leakage. The experimental group A used a lattice matching system to completely eliminate cracks. More importantly, the hydrogen etching modification technique removed the common indium segregation rough spots during AlInN growth, making the reflectivity close to the theoretical limit, which is crucial for the onset of VCSEL.

[0125] Experiment three: comparison experiment of photoelectric performance of full structure devices

[0126] Experimental purpose: to verify the comprehensive improvement effect of trapezoidal quantum wells and polarization enhanced tunnel junctions on device luminous efficiency, operating voltage and optical output power

[0127] Experimental grouping:

[0128] Experimental group A (the present application): complete VCSEL chip structure, including trapezoidal quantum wells and top polarization enhanced tunnel junctions (without ITO);

[0129] Comparison group D (traditional structure): uses a conventional square well active region, and does not grow a tunnel junction on the top, but deposits a 200 nm thick ITO transparent conductive film as a p-type contact;

[0130] Experimental steps: the two groups of epitaxial wafers were fabricated into independent VCSEL devices with an aperture of 10 microns; L-I-V (light power-current-voltage) tests were performed in continuous wave (CW) mode at room temperature; the threshold current (Ith) ), operating voltage (at 20 mA) and maximum optical output power were recorded;

[0131] Experimental results:

[0132] Table 3: Comparison table of photoelectric performance test results of full structure devices

[0133] ;

[0134] The threshold current is reduced due to the high reflectivity crack-free DBR (which reduces optical loss) and trapezoidal quantum well (which alleviates the QCSE effect and improves gain) of the present invention. In contrast, due to the poor quality of the DBR and the strong polarization field, the D group is difficult to start oscillation.

[0135] Reduced operating voltage: thanks to the polarization-enhanced tunnel junction 10, although the ITO used in the comparison group D is conductive, it has a significant absorption of blue-violet light and a large contact resistance with p-GaN. The tunnel junction of the present invention utilizes piezoelectric polarization to achieve efficient hole injection, which greatly reduces the series resistance.

[0136] Overall conclusion: The device in experimental group A exhibited true laser characteristics, while the control group D, under the same injection conditions, may only show LED-like emission or fail to oscillate.

[0137] Through the above three sets of progressively comparative experiments, it is fully demonstrated that the technical solution of the present invention is superior to the existing traditional technology in all three dimensions of material growth quality, structural integrity and device optoelectronic performance. In particular, the introduction of the defect blocking layer and lattice matching DBR solves the fundamental problems of low yield and short lifespan of gallium nitride VCSELs, and has extremely high industrialization value. Specific Implementation Example 5:

[0139] like Figs. 1-2 As shown, based on the content of the above specific embodiments, the following content is further disclosed:

[0140] To further verify the feasibility of the technical solution in this application, the following case study is provided:

[0141] Case 1: Miniature display projection light source for augmented reality (AR) glasses;

[0142] Application Background and Requirements: In the field of augmented reality (AR) glasses, in order to achieve lightweight and long battery life, the display system places extremely stringent requirements on the light source. The light source must have a micron-sized dimension, extremely high electro-optical conversion efficiency to reduce heat generation, and extremely low divergence angle to match the optical waveguide lens. Traditional LED light sources have large divergence angles and low light energy utilization, while edge-emitting lasers are difficult to integrate and have poor beam quality. The surface-emitting gallium nitride VCSEL laser chip of this invention is an ideal choice for such applications.

[0143] In this case, the chip described in this invention is manufactured in the form of a large-scale two-dimensional array. The chip's emission wavelength is finely tuned to the pure blue light band of 450 nanometers to match the blue component in RGB full-color display. A single module contains 64 by 64 pixel units, and each pixel unit is an independent VCSEL chip described in this application. Using the photolithography process in Sp7 of this application, the current-limiting aperture of a single chip is reduced to three micrometers to achieve extremely high pixel density.

[0144] Actual embodiment of technical advantages:

[0145] Yield assurance (corresponding to Sp3): Since AR glasses require thousands of micro-lasers to work simultaneously, any bad point will cause abnormal display. The stress-regulated nano-mask composite defect blocking layer 4 adopted in the application reduces the density of penetrating dislocations by an order of magnitude, so that in large-area array manufacturing, the probability of dead pixels is close to zero, greatly improving the yield of the module.

[0146] Low power consumption and long battery life (corresponding to Sp6): AR glasses are sensitive to battery life. The polarization-enhanced tunnel junction 10 of the application replaces the high-loss ITO electrode, and cooperates with the high-gain characteristics of the trapezoidal quantum well, so that the threshold current of a single pixel is reduced to less than 0.5 mA, which means that the battery life of AR glasses using the chip can be extended by more than 30% under the same battery capacity.

[0147] Case 2: High-resolution adaptive headlamp system ADB of intelligent vehicles;

[0148] Application background and demand: The new generation of intelligent vehicle headlamps need to be able to turn off the light beam irradiated to the oncoming vehicle area in real time according to the road conditions, while maintaining high-brightness illumination in other areas. This requires the light source to have high brightness, independent addressability, and the ability to work stably for a long time in a 120-degree Celsius high-temperature environment. The resolution of the traditional LED matrix is low, while the gallium nitride VCSEL of the application can achieve fine illumination of the order of one million pixels.

[0149] In this case, the chip of the application is packaged on a ceramic high-thermal-conductivity substrate and covered with yellow fluorescent powder to excite white light. Due to the high-temperature and vibration environment of the vehicle-grade, the n-type nitride DBR mirror 5 of the chip adopts an aluminum gallium indium nitride / gallium nitride lattice matching system, which increases by a factor of 50 to obtain ultra-high reflectivity. The chip uses flip-chip soldering process, and the p-face ring electrode 12 is directly soldered on the heat dissipation substrate. The light is emitted from the back of the sapphire substrate 1.

[0150] Actual embodiment of technical advantages:

[0151] Zero-crack reliability (corresponding to Sp4): The automobile headlamp will experience a huge temperature impact when starting in extremely cold and running in high temperature. The traditional high-aluminum component DBR is prone to micro-cracks due to thermal stress mismatch during this process, resulting in failure. The lattice matching material system combined with hydrogen etching modification technology adopted in the application eliminates the residual stress inside the epitaxial layer, ensuring that the chip still maintains zero cracks and zero light decay after passing through one thousand hours of vehicle-grade cold and hot impact test.

[0152] High power output (corresponding to Sp6): In order to illuminate the road two hundred meters away, the chip needs to be driven by a large current. The polarization enhanced tunneling junction 10 of the application realizes extremely low series resistance by using the incremental doping technology, which greatly reduces the generation of Joule heat, so that the chip can withstand a continuous driving current of up to two amperes without thermal quenching.

[0153] Case three: underwater high-speed wireless optical communication base station Li-Fi;

[0154] Application background and demand: In marine exploration and underwater robot communication, radio waves attenuate extremely fast in water, and blue-green light of 450-520 nanometers has the smallest transmission loss in water. Therefore, visible light communication Li-Fi based on blue-green light is the core technology of underwater communication. This application requires a light source with extremely fast modulation response speed to support gigabit-level data transmission per second.

[0155] In this case, the chip is designed as a single-point high-speed modulation light source, and the emission wavelength is set to the green light band of 520 nanometers. The n-type cavity length adjustment layer 6 in Sp5 is used to accurately control the resonant cavity length to be an integer multiple of half the wavelength, ensuring that the laser works in a single longitudinal mode state, reducing the influence of dispersion on communication quality, and the current limiting aperture is designed to be five microns to reduce parasitic capacitance and improve the bandwidth limited by the RC time constant.

[0156] Actual embodiment of technical advantages:

[0157] High-speed modulation capability (corresponding to Sp6): The p-type layer resistance and capacitance of the traditional structure are large, which seriously limits the switching speed. The polarization enhanced tunneling junction 10 of the application greatly compresses the depletion region width through the piezoelectric polarization field, significantly reduces the parasitic resistance and capacitance of the device, and in combination with the low non-radiative recombination center brought by the defect blocking layer, the chip realizes a 3dB modulation bandwidth of more than 3GHz, successfully supporting real-time video transmission of five gigabits per second underwater.

[0158] Green light epitaxial quality (corresponding to Sp3): It is usually extremely difficult to grow high-indium-component green quantum wells, and phase separation and defects are easily generated. The nano-porous mask technology of the application provides a nearly perfect low-dislocation template for the green active region, so that the green VCSEL can also realize room-temperature continuous lasing, breaking through the technical bottleneck of long-wavelength nitride lasers.

[0159] It is to be understood that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting; it is not intended to exclude myriad other embodiments of the present application that other inventors can develop based on the same general inventive concepts embodied by the described embodiments. That is, although the present application is described in terms of particular embodiments and implementations, it is to be understood that the terminology used is for the purpose of descriptive clarity and that it is intended to be limited only by the words of the patent claims. A reference to an aspect of the present application employing a particular aspect, feature or structure of the described embodiments is not to be interpreted as an indication that all or even any aspects of the present application have such feature or structure in some way.

[0160] While the embodiments of the application have been shown and described herein, it will be understood by those skilled in the art that many changes, modifications, substitutions and alterations to these embodiments can be made without departing from the spirit and scope of the present application, which is defined by the appended claims and their equivalents.

Claims

1. A surface-emitting gallium nitride VCSEL laser chip, characterized in that: The laser chip includes a substrate (1), a low-temperature nucleation layer (2), a high-temperature recovery layer (3), a stress-modulated nanomask composite defect blocking layer (4), an n-type nitride DBR mirror (5), an n-type cavity length adjustment layer (6), an indium gallium nitride / gallium nitride multi-quantum well active region (7), a p-type electron blocking layer (8), a p-type waveguide layer (9), and a polarization-enhanced tunnel junction (10). The stress-modulated nanomask composite defect blocking layer (4) is located between the high-temperature recovery layer (3) and the n-type nitride DBR mirror (5), and the structure of the stress-modulated nanomask composite defect blocking layer (4) includes a direct covering on the high-temperature nucleation layer. The in-situ silicon nitride nanoporous mask layer (401) on the surface of the recovery layer (3) and the aluminum gallium nitride / gallium nitride stress-compensated superlattice layer (402) grown on the in-situ silicon nitride nanoporous mask layer (401) are provided with a p-plane dielectric DBR mirror (11) and a p-plane ring electrode (12) on the upper surface of the polarization-enhanced tunnel junction (10). The in-situ silicon nitride nanoporous mask layer (401) forms randomly distributed nanopores on the surface of the high-temperature recovery layer (3) through discontinuous deposition. The aluminum gallium nitride / gallium nitride stress-compensated superlattice layer (402) is laterally epitaxially overgrown through the nanopores and merged into a film to block penetrating dislocations from the substrate (1).

2. The surface-emitting gallium nitride VCSEL laser chip according to claim 1, characterized in that: The aluminum gallium nitride / gallium nitride stress-compensating superlattice layer (402) consists of 10 to 20 periods. The structure consists of alternating layers, where the Al composition x linearly varies from 0.05 to 0.20 along the growth direction, and each cycle... The thickness of the sublayer is less than The thickness of the sublayer is adjusted to compensate for the pre-stress of the n-type nitride DBR mirror (5) grown above while blocking dislocations.

3. The surface-emitting gallium nitride VCSEL laser chip according to claim 1, characterized in that: The polarization-enhanced tunnel junction (10) includes heavily doped components. Type I indium gallium nitride layer and heavily doped Gallium nitride layer, the heavily doped In the indium gallium nitride layer, a piezoelectric polarization field is generated by introducing an indium component. The direction of the piezoelectric polarization field is consistent with the direction of the built-in electric field to enhance the hole tunneling probability. The polarization-enhanced tunnel junction (10) serves as a hole injection source and also has a current spreading function.

4. The surface-emitting gallium nitride VCSEL laser chip according to claim 1, characterized in that: The n-type nitride DBR mirror (5) adopts an aluminum indium nitride / gallium nitride lattice matching material system, wherein the In composition in the aluminum indium nitride layer is controlled between 17% and 18% to match the gallium nitride lattice, and the number of pairs of the n-type nitride DBR mirror (5) is 30 to 50.

5. A surface-emitting gallium nitride VCSEL laser chip according to claim 1, characterized in that: The indium gallium nitride / gallium nitride multi-quantum-well active region (7) adopts a trapezoidal quantum well structure, with a thickness of 1 nm to 2 nm inserted between the indium gallium nitride quantum well and the gallium nitride quantum barrier. A gradient layer in which the y-component changes continuously at the interface to reduce the quantum confinement Stark effect caused by the polarization electric field.

6. A method for suppressing epitaxial defects in a surface-emitting gallium nitride VCSEL laser chip according to any one of claims 1-5, characterized in that: The method for suppressing epitaxial defects includes the following steps: Sp1: The substrate (1) is subjected to high-temperature heat treatment to remove surface oxides and impurities; Sp2: A low-temperature nucleation layer (2) is grown on the surface of a substrate (1), followed by a high-temperature recovery layer (3) grown by heating. Sp3: Preparation of stress-controlled nanomask composite defect blocking layer (4) First, silicon source and ammonia gas are introduced, and a discontinuous in-situ silicon nitride nanoporous mask layer (401) is formed on the surface of high temperature recovery layer using sub-monolayer deposition technology. Then, the growth conditions are switched, three-dimensional island nucleation is carried out through nanopores, and the reaction chamber pressure is adjusted to promote lateral merging, forming a flat aluminum gallium nitride / gallium nitride stress-compensating superlattice layer (402). Sp4: An n-type nitride DBR mirror (5) is grown on a stress-controlled nanomask composite defect blocking layer (4). Sp5: n-type cavity length adjustment layer (6), indium gallium nitride / gallium nitride multi-quantum well active region (7), p-type electron blocking layer (8) and p-type waveguide layer (9) are grown sequentially. Sp6: A polarization-enhanced tunnel junction (10) is grown and activated by in-situ thermal annealing after growth is completed; Sp7: Complete the deposition and electrode fabrication process of the p-surface dielectric DBR mirror (11).

7. The method for suppressing epitaxial defects in a surface-emitting gallium nitride VCSEL laser chip according to claim 6, characterized in that: The specific process for forming a discontinuous in-situ silicon nitride nanoporous mask layer (401) in Sp3 is as follows: the reaction chamber temperature is maintained at 850°C to 950°C, the silane flow rate is 50 sccm to 100 sccm, the ammonia flow rate is 2000 sccm to 4000 sccm, and the growth time is controlled at 30 seconds to 60 seconds, so that the silicon nitride coverage rate on the surface of the high temperature recovery layer (3) is 60% to 80%, thereby naturally forming irregular nanopores as windows for subsequent epitaxy.

8. The method for suppressing epitaxial defects in a surface-emitting gallium nitride VCSEL laser chip according to claim 6, characterized in that: The lateral merging process of the aluminum gallium nitride / gallium nitride stress-compensated superlattice layer (402) in Sp3 adopts a pulsed growth mode: firstly, it is grown under a high pressure condition of 200 Torr to 300 Torr. A sublayer is grown to enhance lateral mobility, followed by the growth of a gallium nitride sublayer under low-pressure conditions of 70 Torr to 100 Torr to fill the surface, and this process is repeated until the total thickness of the superlattice layer reaches 300 nm to 500 nm.

9. The method for suppressing epitaxial defects in a surface-emitting gallium nitride VCSEL laser chip according to claim 6, characterized in that: When growing the n-type nitride DBR mirror (5) in Sp4, after each pair of aluminum indium nitride / gallium nitride layers is grown, a growth interruption of 10 to 20 seconds is introduced, and a small amount of hydrogen is introduced during the interruption to etch and modify the surface in order to remove the metal droplets formed by indium segregation on the surface.

10. The method for suppressing epitaxial defects in a surface-emitting gallium nitride VCSEL laser chip according to claim 6, characterized in that: The growth of the polarization-enhanced tunnel junction (10) in Sp6 is carried out using incremental doping technology. During the growth of the heavily doped p++ type indium gallium nitride layer, the gallium source is turned off and the magnesium source is continuously introduced for 5 to 10 seconds to form a locally high concentration of magnesium doped layer at the interface. The subsequent in-situ thermal annealing temperature is set to 700°C to 750°C, and the carrier gas is a pure nitrogen environment.

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