Interrupt or exception event handling method, processor and electronic device

Abstract

The application relates to an interrupt or exception event processing method, a processor and an electronic device. The method comprises the following steps: after an interrupt or exception event is detected by a write-back unit, flushing a pipeline and triggering a hardware stack operation; based on the stack operation, a microinstruction splitting unit splits a stack microinstruction sequence of the hardware stack to obtain a register stack switching instruction while a fetch unit sequentially obtains to-be-processed instructions; the microinstruction splitting unit switches a first register stack currently used to a second register stack based on the register stack switching instruction; and sends to-be-executed instructions to an execution unit; the execution unit executes the to-be-executed instructions to perform interrupt or exception processing, and stores intermediate data and / or result data generated after execution to the second register stack. The first register stack and the second register stack are physically isolated in the processor, and a microinstruction splitting mechanism automatically triggered by hardware is combined, so that an interrupt or exception processing flow is significantly optimized.

Description

Technical Field

[0001] This application relates to the field of event technology, and more specifically, to an interrupt or exception event handling method, processor, and electronic device. Background Technology

[0002] In real-time processors, interrupts and exceptions must be responded to within strict time limits to ensure system safety and reliability. Current mainstream solutions generally use software to handle context switching: when an interrupt occurs, multiple instructions are used to save general-purpose registers and critical control status registers onto the stack, and then these are restored instruction by instruction after processing. This method requires executing dozens of instructions, resulting not only in high interrupt response latency but also significantly increasing code size and consuming valuable memory and cache resources.

[0003] Therefore, there is an urgent need for a hardware-assisted, efficient interrupt handling mechanism to eliminate the overhead of software context saving and improve response speed and predictability. Summary of the Invention

[0004] This application provides an interrupt or exception event handling method, a processor, and an electronic device.

[0005] A first aspect of this application provides an interrupt or exception event handling method, the method being applied in a processor, the processor comprising: an instruction fetch unit, a microinstruction splitting unit, an execution unit, a first register file, a second register file, and a write-back unit; the method comprising:

[0006] After the write-back unit detects an interrupt or abnormal event, it flushes the pipeline and triggers a hardware push operation.

[0007] Based on the push operation, while the instruction fetching unit sequentially fetches the instructions to be processed, the micro-instruction splitting unit splits the push micro-instruction sequence of the hardware push to obtain register file switching instructions; the instructions to be processed include: instructions to be executed; the push micro-instruction sequence is a pre-set instruction sequence.

[0008] The microinstruction splitting unit switches the currently used first register file to the second register file based on the register file switching instruction; and sends the instruction to be executed to the execution unit; wherein the second register file is physically isolated from the first register file;

[0009] The execution unit executes the instruction to be executed to perform interrupt or exception handling, and stores the intermediate data and / or result data generated after execution into the second register file.

[0010] In an optional embodiment of this application, the micro-instruction splitting unit splits the push stack micro-instruction sequence of hardware push to obtain register file switching instructions and stack pointer switching instructions.

[0011] Accordingly, before the execution unit executes the interrupt or exception handler based on the instruction to be executed, the method further includes: the microinstruction splitting unit switches the stack pointer from the normal state pointer to the interrupt stack pointer based on the stack pointer switching instruction, so that the pointers during the interrupt or exception event handling process are all interrupt stack pointers.

[0012] In an optional embodiment of this application, the instruction to be processed further includes: a pop instruction, which is located after the instruction to be processed;

[0013] The method further includes:

[0014] The micro-instruction splitting unit splits the pop instruction into a pop micro-instruction sequence;

[0015] The interrupt stack pointer is switched to the normal state pointer based on the pop microinstruction sequence.

[0016] In an optional embodiment of this application, the method further includes:

[0017] Based on the pop microinstruction sequence, the second register file is switched to the first register file, which is used to store instructions for the normal program.

[0018] In an optional embodiment of this application, the micro-instruction splitting unit splits the stack push micro-instruction sequence of hardware push, and obtains both register file switching instructions and stack space opening instructions.

[0019] Accordingly, before the execution unit executes the interrupt or exception handler based on the instruction to be executed, it also includes:

[0020] Based on the stack space creation instruction, a stack space is created in the external memory;

[0021] Store the instructions to be executed, which represent the exception return address, interrupt enable and privilege state, and interrupt or exception reason, into the opened stack space.

[0022] In an optional embodiment of this application, the method further includes:

[0023] Based on the pop microinstruction sequence, the instructions to be executed, representing the exception return address, interrupt enable and privilege state, and interrupt or exception reason, are written back to the status register, and the stack space opened in the external memory is returned.

[0024] In an optional embodiment of this application, the processor includes: a decoding unit;

[0025] The step of sending the instruction to be executed to the execution unit includes:

[0026] The instruction to be executed is sent to the execution unit via the decoding unit, which is used to decode the sub-instruction to be executed.

[0027] A second aspect of this application provides a processor, including:

[0028] The write-back unit is configured to flush the pipeline and trigger a hardware push operation when an interrupt or exception event is detected.

[0029] The instruction fetch unit is configured to sequentially fetch instructions to be processed based on the push operation; the instructions to be processed include: instructions to be executed.

[0030] The micro-instruction splitting unit is configured to split the push micro-instruction sequence of hardware push based on the push operation to obtain a register file switching instruction; switch the currently used first register file to a second register file based on the register file switching instruction; and send the instruction to be executed to the execution unit, wherein the second register file is physically isolated from the first register file;

[0031] The execution unit is configured to execute the instruction to be executed for interrupt or exception handling, and to store the intermediate data and / or result data generated after execution into the second register file.

[0032] In an optional embodiment of this application, it further includes: a decoding unit configured to send the instruction to be executed to the execution unit via the decoding unit, the decoding unit being used to decode the sub-instruction to be executed.

[0033] A third aspect of the present application provides an electronic device, including: a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the steps of any of the above methods.

[0034] A fourth aspect of this application provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of the method described in any of the preceding claims.

[0035] The implementation of this application significantly optimizes the interrupt or exception handling process by introducing physically isolated first and second register files into the processor and combining them with a hardware-triggered microinstruction splitting mechanism. When an interrupt event is detected in the write-back unit, the processor automatically triggers a preset push instruction, and the instruction fetch unit then jumps to the interrupt entry point to retrieve the instruction to be executed. The microinstruction splitting unit first switches the register file to a dedicated second register file to ensure that subsequent operations do not pollute the user context, and then splits the instruction into N atomic-level sub-requests for execution by the execution unit. Since the interrupt handling uses an independent register file throughout, there is no need for software to save / restore the Caller-saved registers, thereby saving dozens of memory access instructions and significantly reducing response latency. In addition, the interrupt entry code requires only minimal instructions, effectively reducing code size and saving storage and cache resources. Attached Figure Description

[0036] The accompanying drawings, which are included to provide a further understanding of this application and form part of this application, illustrate exemplary embodiments and are used to explain this application, but do not constitute an undue limitation of this application. In the drawings:

[0037] Figure 1 A flowchart illustrating an interruption or exception event handling method provided by the present invention;

[0038] Figure 2 This is a schematic diagram of the processor provided by the present invention;

[0039] Figure 3 This is a schematic diagram of the structure of the electronic device provided by the present invention. Detailed Implementation

[0040] In the process of developing this application, the inventors discovered that current processors have low efficiency in handling interrupts and exceptions.

[0041] To address the aforementioned issues, this application provides a method for handling interruptions or abnormal events.

[0042] Please see Figure 1 , 2 The following embodiments use the aforementioned processor as the execution entity and apply the interrupt or exception event handling method provided in this application to the aforementioned processor. The interrupt or exception event handling method provided in this application includes the following steps 101-104:

[0043] This method is applied in a processor. In this embodiment, the processor includes: an instruction fetch unit, a microinstruction splitting unit, an execution unit, a first register file (general-purpose register file), a second register file (implicit register file), and a write-back unit. The first register file stores the general-purpose register context during normal user program execution. The second register file is an implicit register file dedicated to interrupt or exception handling. Its physical structure is the same as the first register file, containing the same number and bit width of register units, but the two are physically isolated and do not interfere with each other.

[0044] It should be noted that the physical structure of the second register file can also be different from that of the first register file. For example, the second register file can contain 17 call_saved registers. The processor has a total of 32 general-purpose registers. The other 15 registers do not have a second register file, but only the first register file (general-purpose register file). Compared to all 32 registers having a second register file, the number of transistors in the corresponding chip of the processor can be reduced, thereby reducing manufacturing costs.

[0045] The method includes:

[0046] Step 101: After the write-back unit detects an interrupt or abnormal event, it flushes the pipeline and triggers a hardware push operation.

[0047] Specifically, when an interrupt or exception occurs, the processor uses the Write-back Unit at the end of its pipeline to accurately capture and respond to the event. When an interrupt (such as an external hardware request) or exception (such as an illegal instruction, system call, or other synchronous event) is recognized by the front-end pipeline and passed to the Write-back Unit, the unit will detect the validity of the interrupt or exception after completing the current instruction commit. Once a valid interrupt or exception is detected, the Write-back Unit immediately triggers a pre-installed sequence of push micro-instructions, thereby entering the flush pipeline and triggering the hardware push operation.

[0048] It is understandable that flushing the pipeline means restarting instruction fetching. While fetching instructions again, the microinstruction splitting unit will also be triggered to split the microinstruction into the stack. These are two independent and simultaneous operations.

[0049] It should be noted that the push-on microinstruction sequence can be internal microcode instructions, control signals, or micro-operation start instructions pre-embedded in the processor's hardware control logic. Its function is to activate the subsequent context switching process. In essence, this push-on microinstruction sequence sends a start signal to the instruction fetch unit, instructing it to load the corresponding sequence of instructions to be executed for the interrupt or exception event.

[0050] Understandably, after an interrupt or abnormal event occurs, this application determines whether the event is an interrupt or an abnormal event by writing back to the unit, thereby achieving high determinism and low latency in interrupt / abnormal response and avoiding the uncertainty caused by traditional software polling or delayed processing.

[0051] Step 102: Based on the push operation, while the instruction fetch unit sequentially fetches the instructions to be processed, the micro-instruction splitting unit splits the push micro-instruction sequence of the hardware push to obtain the register file switching instruction; the instructions to be processed include: instructions to be executed; the push micro-instruction sequence is a pre-set instruction sequence;

[0052] Specifically, this instruction is triggered by the write-back unit after an interrupt or exception event is acknowledged, and is used to initiate the context saving process. Its function is to notify the instruction fetch unit to switch the execution flow and enter the interrupt or exception handling entry path.

[0053] Specifically, in response to the push operation, the instruction fetch unit no longer fetches instructions from the address of the next instruction in the original user program, but automatically jumps to a preset interrupt vector table address or a fixed entry address, and sequentially fetches a series of instructions representing the interrupt or exception handling process from there. These instructions include instructions to be executed. These instructions typically include a jump instruction to a general interrupt handler (such as `trap_handler`), and may also contain a small number of micro-operations for initialization, which together constitute the minimum instruction sequence for the interrupt entry point. Simultaneously, the micro-instruction splitting unit splits the push micro-instruction sequence from the hardware push operation to obtain a register file switching instruction. This register file switching instruction is used to switch the currently used first register file to the second register file.

[0054] Subsequently, the instruction fetch unit sends the fetched instruction to the microinstruction splitting unit. This instruction is then transmitted to the execution unit for execution of the specific interrupt or exception handler.

[0055] After the register file switch is completed, the microinstruction splitting unit splits the stacked microinstruction sequence into multiple instructions (i.e., N micro-operations), where N is a positive integer greater than 1. These sub-requests include, but are not limited to: switching the stack pointer to a dedicated interrupt stack, allocating space on the interrupt stack, saving the value of the critical control and status register (CSR), and jumping to the interrupt handler entry point. After all sub-requests are generated, the microinstruction splitting unit sends the N sub-requests to the execution unit in execution order, which executes them one by one to complete the establishment of the interrupt context and the initiation of the processing flow.

[0056] Step 103: The microinstruction splitting unit switches the currently used first register file to the second register file based on the register file switching instruction; and sends the instruction to be executed to the execution unit; wherein the second register file is physically isolated from the first register file;

[0057] Specifically, the microinstruction splitting unit is used to switch the currently used first register file to the second register file based on the register file switching instruction. When the unit receives an instruction to be executed that represents an interrupt or exception handling process, it first switches the currently active register file from the first register file to the second register file, thereby isolating the context.

[0058] After the register file switch is completed, the instructions to be executed are sent to the execution unit so that the execution unit can execute each instruction to be executed.

[0059] It should be noted that the first register file is used to store the general-purpose register context during normal user program execution; the second register file is an implicit register file reserved specifically for interrupt or exception handling. The two are physically isolated, each with its own independent storage array, ensuring that any read or write operation to the general-purpose registers during interrupt handling will not contaminate the user program state stored in the first register file. This switching operation is directly completed by the microinstruction splitting unit through internal control signals, without software intervention.

[0060] Through the above mechanism, this invention utilizes hardware-level register file isolation and automatic microinstruction splitting to completely eliminate the need for explicit software saving of the Caller-saved register in traditional solutions. This not only significantly reduces interrupt response latency but also significantly improves the determinism and reliability of system execution.

[0061] Step 104: The execution unit executes the instruction to be executed to perform interrupt or exception handling, and stores the intermediate data and / or result data generated after execution into the second register file.

[0062] Specifically, the execution unit is the core hardware module in the processor responsible for actual computation and operation execution. When it receives N sub-requests sent by the microinstruction splitting unit, it will execute these low-level operations in sequence to complete the context establishment and program jump process for interrupt or exception handling.

[0063] For example, the execution unit will adjust the stack pointer, write the value of the control and status register (CSR) to the interrupt stack, and finally execute a jump micro-operation to direct the program flow to the preset interrupt or exception handler (such as trap_handler).

[0064] During the execution of an interrupt or exception handler, all intermediate data and / or result data are written to the second register file by the execution unit. It should be noted that this application writes the calculation results back to the processor's internal register file, while the second register file, as a dedicated register group physically isolated from the first register file, ensures that this data does not overwrite or interfere with the original register state of the user program.

[0065] This embodiment of the specification significantly optimizes the interrupt or exception handling process by introducing physically isolated first and second register files in the processor, combined with a hardware-triggered microinstruction splitting mechanism. When an interrupt event is detected in the write-back unit, the processor automatically triggers a preset push instruction, and the instruction fetch unit then jumps to the interrupt entry point to retrieve the instruction to be executed. The microinstruction splitting unit first switches the register file to a dedicated second register file to ensure that subsequent operations do not pollute the user context, and then splits the instruction into N atomic-level sub-requests for execution by the execution unit. Since the interrupt handling uses an independent register file throughout, there is no need for software to save / restore the Caller-saved registers, thereby saving dozens of memory access instructions and significantly reducing response latency. In addition, the interrupt entry code requires only minimal instructions, effectively reducing code size and saving storage and cache resources.

[0066] In an optional embodiment of this application, the micro-instruction splitting unit described in the above steps splits the stack push micro-instruction sequence of hardware push, and obtains both register file switching instructions and stack pointer switching instructions.

[0067] Accordingly, before the execution unit executes the interrupt or exception handler based on the instruction to be executed, the method further includes: the microinstruction splitting unit switches the stack pointer from the normal state pointer to the interrupt stack pointer based on the stack pointer switching instruction, so that the pointers during the interrupt or exception event handling process are all interrupt stack pointers.

[0068] Specifically, before the microinstruction splitting unit switches the register file from the first register file to the second register file, a stack isolation operation is performed, which switches the current stack pointer (SP) to a dedicated interrupt stack pointer. Here, the "stack pointer" refers to the register used to indicate the address of the current program stack top (such as x2 / sp in RISC-V), while the "interrupt stack pointer" is a separate stack pointer pre-configured and stored in the Control and Status Register (CSR), dedicated to interrupt or exception handling. This operation ensures that all subsequent stack-related operations operate on the independent interrupt stack space, rather than the user program's main stack, thus avoiding interference between stack data.

[0069] This embodiment ensures that all subsequent instructions or requests use the interrupt stack pointer by switching the stack pointer after switching the register file. Therefore, the interrupt context is isolated not only at the register level but also at the stack storage level, further enhancing the system's reliability and security. This mechanism is automatically implemented in hardware without software intervention, improving efficiency and eliminating the potential error risks caused by mixed stack usage in traditional solutions.

[0070] In an optional embodiment of this application, the instruction to be processed further includes: a pop instruction, wherein the pop instruction is located after the instruction to be processed;

[0071] The method further includes:

[0072] The micro-instruction splitting unit splits the pop instruction into a pop micro-instruction sequence;

[0073] The interrupt stack pointer is switched to the normal state pointer based on the pop microinstruction sequence.

[0074] Specifically, when the interrupt or exception handler finishes execution and is ready to return to the normal program, the microinstruction splitting unit also performs a stack pointer recovery operation: switching the currently used interrupt stack pointer back to the normal state stack pointer. This ensures that after the processor exits the interrupt context, the stack pointer is accurately restored to the state before the user program was interrupted, thereby guaranteeing the continuity and correctness of subsequent main program stack operations. Here, the "normal state stack pointer" refers to the main stack pointer used by the user program before the interruption, usually stored in a dedicated control and status register; while the "interrupt stack pointer" is an independent stack top address allocated specifically for the interrupt context.

[0075] This stack pointer recovery step is typically triggered by a pop instruction (such as a custom POPMRET instruction) and is executed automatically as part of a pop micro-operation sequence. By accurately restoring the stack pointer during the interrupt exit phase, this invention not only achieves the isolation and recovery of the register context but also completes the isolation and rollback of the stack storage space, effectively preventing stack data corruption or stack overflow risks. This process is entirely driven by hardware micro-instructions, requiring no explicit software intervention, further improving the efficiency, determinism, and overall system reliability of interrupt returns.

[0076] It is understandable that the pop instruction is the instruction following the instruction to be processed, which is obtained in the pipeline by the instruction fetch unit.

[0077] In an optional embodiment of this application, after completing interrupt or exception handling and restoring the stack pointer, the method further includes:

[0078] Based on the pop microinstruction sequence, the second register file is switched to the first register file, which is used to store instructions for the normal program.

[0079] Specifically, the first register file refers to the main general-purpose register file used by the processor during normal program execution, which is used to store the register context (including addresses, data, temporary variables, etc.) during the user program's runtime, while the second register file is an implicit register file reserved specifically for interrupt or exception handling.

[0080] This embodiment ensures the integrity and transparency of the user program context by precisely switching back to the first register file upon interrupt exit, making interrupt handling completely unaffected by the main program. This mechanism, working in conjunction with stack pointer recovery, constitutes a complete context isolation and restoration system, significantly improving system reliability. The entire process is completed automatically by hardware without software intervention, further optimizing the latency and determinism of the interrupt return path.

[0081] In some optional scenarios, the interrupt or exception handler can use the first register file. In one optional embodiment, the microinstruction splitting unit splits the push microinstruction sequence of the hardware push onto the stack to obtain the register file switching instruction and the stack space allocation instruction.

[0082] Accordingly, before the execution unit executes the interrupt or exception handler based on the instruction to be executed, it also includes:

[0083] Based on the stack space creation instruction, a stack space is created in the external memory;

[0084] Store the instructions to be executed, which represent the exception return address, interrupt enable and privilege state, and interrupt or exception reason, into the opened stack space.

[0085] Specifically, when the processor detects an interrupt or exception, it first flushes any uncommitted instructions in the current pipeline to ensure processor state consistency. Subsequently, the micro-instruction splitting unit automatically breaks down the hardware push operation into a series of push micro-instructions, which include at least register file switching instructions and stack space allocation instructions. The register file switching instructions are used to switch the access mapping of general-purpose registers from the first register file to the second register file (implicit register file). This ensures that all read and write operations on Caller-saved general-purpose registers (such as x1, x5–x7, x10–x17, etc.) during interrupt or exception handling are performed on this implicit register file, thus avoiding contamination of the original register states used by the user program and eliminating the need for explicit saving and restoring of these registers by the software.

[0086] Meanwhile, the stack space allocation instruction is used to allocate dedicated stack space for the current interrupt context in external memory (such as on-chip SRAM or main memory). Specifically, the execution unit adjusts the stack pointer (sp) according to this instruction, for example, by expanding the stack space downwards using `addisp, sp, -3*REGBYTES`, to reserve enough space to store critical status information. This critical status information includes the `mepc` register value representing the exception return address, the `mstatus` register value representing the interrupt enable and privileged status, and the `mcause` register value representing the interrupt or exception cause.

[0087] Furthermore, to achieve rapid isolation between the user stack and the interrupt stack, this invention introduces a dedicated stack space. This operation is automatically triggered by microinstructions when specific hardware conditions are met (such as the first entry into an interrupt / exception), ensuring that interrupt handling uses an independent stack space while the original user stack pointer is safely temporarily stored in the dedicated stack space. The entire push microinstruction sequence executes from the third stage of the processor pipeline, without waiting for software to jump to the handler, saving at least 3 clock cycles compared to traditional software solutions. After the interrupt or exception handler finishes execution, a dedicated pop return instruction (such as POPMRET) triggers a reverse microinstruction sequence to sequentially restore the CSR, release the stack space, and switch back to the user stack pointer, achieving efficient and transparent context switching.

[0088] Based on the above embodiments, in one embodiment of this specification, the method further includes:

[0089] Based on the pop microinstruction sequence, the instructions to be executed, representing the exception return address, interrupt enable and privilege state, and interrupt or exception reason, are written back to the status register, and the stack space opened in the external memory is returned.

[0090] Specifically, after the execution unit completes the interrupt or exception handler, in response to a dedicated pop return instruction (such as POPMRET), the microinstruction splitting unit generates a corresponding pop microinstruction sequence. This pop microinstruction sequence is used to rewrite the critical status information previously stored in the external memory stack space back into the processor's internal status register and release the occupied stack resources.

[0091] The "instruction to be executed representing the exception return address, interrupt enable and privileged status, and interrupt or exception cause" mentioned here are not actual instruction codes, but refer to three types of key status data saved to the stack during the push phase, corresponding to the processor's Control and Status Register (CSR):

[0092] Exception return address: corresponds to the mepc register, which indicates the program counter (PC) value at which execution should continue after the interrupt return;

[0093] Interrupt enable and privilege status: Corresponds to the mstatus register, which contains key control bits such as the global interrupt enable bit (MIE) and return privilege level (MPP);

[0094] Interrupt or exception cause: The corresponding mcause register encodes the interrupt source (such as timer, external device) or exception type (such as illegal instruction, page fault).

[0095] After the status register is restored, the stack pop microinstruction sequence further executes a stack space rollback operation to release the memory area previously allocated to save the context. Then, the stack pointer is switched back to the user program's original stack space, while the interrupt stack pointer is temporarily stored back in the MTSP register for later use. Finally, the MRET instruction is executed, using the restored MEPC and MSATUS to complete the privilege level switch and jump back to the interrupted user program, achieving seamless and efficient context recovery.

[0096] Based on the above embodiments, in one embodiment of this specification, the processor includes: a decoding unit;

[0097] The step of sending the instruction to be executed to the execution unit includes:

[0098] The instruction to be executed is sent to the execution unit via the decoding unit, which is used to decode the sub-instruction to be executed.

[0099] In one embodiment of the present invention, the processor includes a decoding unit, which is a key component of the processor pipeline, located after the instruction fetch unit and before the execution unit. Its main function is to parse and decode the instructions to be executed (including user program instructions and interrupt handling instructions) fetched from the instruction memory or microinstruction queue, generate control signals and operand information, and send the decoded instructions to the execution unit for subsequent execution.

[0100] Specifically, after the processor completes the context saving for an interrupt or exception, it needs to jump to the interrupt / exception handler. At this time, the program counter (PC) points to the handler entry point (such as `trap_handler`), and the instruction fetch unit retrieves the instruction at that address (such as `JUMP trap_handler` or `POPMRET`). These instructions are then sent to the decoding unit. The decoding unit parses the opcode and operands of the instruction: for example, it identifies `POPMRET` as a user-defined compound instruction and decodes it into a set of control signals; for ordinary jump instructions, it generates the corresponding branch control signals and target address.

[0101] Furthermore, in this invention, the push or pop microinstruction sequences generated by the microinstruction splitting unit (such as CSRR X3, CSR_X, STORE X3, 0(sp), CSR SWAP sp, mtsp, etc.) also need to be processed by the decoding unit. The decoding unit maps the opcodes in these microinstructions to functional unit enable signals within the execution unit (such as register read enable, CSR access enable, ALU operation type, memory write enable, etc.), and passes fields such as source / destination register number and immediate offset to the execution unit. For example, when the decoding unit receives the STORE X3, 8(sp) microinstruction, it parses out that the base address register is sp, the offset is 8, and the data source is x3, and generates corresponding memory control signals for the execution unit to complete data writing during the memory access phase.

[0102] By introducing a decoding unit, this invention ensures that user program instructions, system software instructions, and hardware-generated context management microinstructions can all be correctly parsed and executed under a unified pipeline architecture, thereby guaranteeing the determinism and compatibility of processor behavior.

[0103] In one optional embodiment of this application, the push instruction is pre-written into the write-back unit or the micro-instruction splitting unit.

[0104] Specifically, this push instruction is configured during the chip design phase through hardware logic or microcode memory. The push instruction is pre-written into a dedicated control register, state machine, or microcode read-only memory within the write-back unit or microinstruction splitting unit.

[0105] Understandably, this push instruction is implemented during the processor manufacturing or initialization phase. Through hardware circuit design or firmware configuration, the control logic required to trigger the interrupt context saving process is embedded into the aforementioned unit in the form of hard-wired logic, state machine jump tables, or microinstructions. Once the write-back unit detects a valid interrupt or exception event, it will automatically activate the preset push instruction without fetching instructions from memory or cache, and without the involvement of the operating system or application.

[0106] The implementation of this embodiment ensures the immediacy and determinism of the interrupt response process. Since the push instruction is built into the critical pipeline unit, its trigger latency is extremely low and it is unaffected by external memory access, cache misses, or bus contention. Furthermore, deploying it in the write-back unit or micro-instruction splitting unit allows for seamless integration with subsequent register file switching, stack pointer updates, and micro-operation generation, forming a complete hardware automated context management path and achieving fully hardware closed-loop control from interrupt detection to context switching.

[0107] To better understand the technical solution of this application, the following is a specific implementation example based on the RISC-V instruction set architecture:

[0108] Assume the processor employs a six-stage pipeline (instruction fetch, microinstruction splitting, decoding, execution, memory access, and write-back) and supports the fast interrupt exception handling mechanism proposed in this invention. The processor internally includes:

[0109] First Register Bank: Stores user program general-purpose registers x0–x31;

[0110] The second register bank (Interrupt Register Bank): a physically isolated implicit register bank with a different structure than the first register bank;

[0111] The dedicated CSR register mtsp is used to store the interrupt stack pointer of the user program in case of an interrupt or exception.

[0112] Get POPMRET (pop instruction) from the stack: used to trigger the pop micro-operation sequence.

[0113] Example of interrupt handling process:

[0114] Interrupt Trigger: When the user program reaches address 0x1000, an external interrupt occurs. The processor detects this event during the write-back phase, flushes the pipeline, and automatically triggers the preset push microinstruction.

[0115] Context switching: The microinstruction splitting unit switches the register file from the first file to the second file; executes CSR SWAPsp, mtsp, stores the current sp (e.g., 0x2000_1000) into mtsp, and loads the interrupt stack pointer (e.g., 0x2000_2000) into sp; executes addi sp, sp, -12 (i.e., -3×4 bytes), allocating stack space; thereby storing the exception return address C, interrupt enable and privilege status S, and the instruction to be executed R for the interrupt or exception cause into the allocated stack space.

[0116] Jump handling: Execute JUMP trap_handler to enter the interrupt service routine. At this time, all register reads and writes will operate on the second register file, and there is no need to save the Caller-saved register.

[0117] Interrupt return: After the Handler finishes execution, the POPMRET instruction is called, triggering a microinstruction sequence: restore mcause, mstatus, and mepc from sp+8, sp+4, and sp+0; release the stack space using addi sp, sp, 12; restore the original stack pointer (0x2000_1000) using CSR SWAP sp, mtsp; switch back to the first register file; and execute mret to return to the user program address 0x1000 + 4.

[0118] This application significantly improves the performance and reliability of interrupt / exception handling by automatically triggering micro-instruction sequences in hardware and employing a physically isolated dual-register file and dual-stack pointer mechanism. Compared to traditional software solutions that require over 50 instructions to save / restore 17 Caller-saved registers, this solution requires only two visible instructions (JUMP + POPMRET), reducing code size by over 90%. Simultaneously, it eliminates numerous memory access operations, reducing interrupt response latency from over 34 cycles to less than 10 cycles on a single-issue processor, improving real-time performance by over 70%. The entire context switch is completed by a fixed micro-operation sequence, with a defined path and no cache dependency; the complete isolation between the register file and interrupt stack effectively prevents data corruption and supports safe nested interrupts.

[0119] The solutions in this application embodiment can be implemented using various computer languages, such as the object-oriented programming language Java and the interpreted scripting language JavaScript.

[0120] To make the technical solutions and advantages of the embodiments of this application clearer, the exemplary embodiments of this application will be described in further detail below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not an exhaustive list of all embodiments. It should be noted that, unless otherwise specified, the embodiments and features in the embodiments of this application can be combined with each other.

[0121] It should be understood that although the steps in the flowchart are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order constraint on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the diagram may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these sub-steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the sub-steps or stages of other steps.

[0122] Please see Figure 2One embodiment of this application provides a processor, including:

[0123] The write-back unit is configured to flush the pipeline and trigger a hardware push operation when an interrupt or exception event is detected.

[0124] The instruction fetch unit is configured to sequentially fetch instructions to be processed based on the push operation; the instructions to be processed include: instructions to be executed.

[0125] The micro-instruction splitting unit is configured to split the push micro-instruction sequence of hardware push based on the push operation to obtain a register file switching instruction; switch the currently used first register file to a second register file based on the register file switching instruction; and send the instruction to be executed to the execution unit, wherein the second register file is physically isolated from the first register file;

[0126] The execution unit is configured to execute the instruction to be executed for interrupt or exception handling, and to store the intermediate data and / or result data generated after execution into the second register file.

[0127] Based on the above embodiments, in one embodiment of this specification, a decoding unit is further included, configured to send the instruction to be executed to the execution unit via the decoding unit, wherein the decoding unit is used to decode the sub-instruction to be executed.

[0128] For specific limitations regarding the processor described above, please refer to the limitations on interrupt or exception handling methods described above, which will not be repeated here. Each module in the processor can be implemented entirely or partially through software, hardware, or a combination thereof. These modules can be embedded in hardware within or independently of the processor in the computer device, or stored in software within the computer device's memory, so that the processor can invoke and execute the operations corresponding to each module.

[0129] In one embodiment, a computer device is provided, the internal structure of which can be as follows: Figure 3As shown. The computer device includes a processor, memory, network interface, and database connected via a system bus. The processor provides computing and control capabilities. The memory includes a non-volatile storage medium and internal memory. The non-volatile storage medium stores an operating system, computer programs, and a database. The internal memory provides an environment for the operation of the operating system and computer programs in the non-volatile storage medium. The database stores data. The network interface communicates with external terminals via a network connection. When the computer program is executed by the processor, it implements one of the above-described interrupt or exception event handling methods. It includes: memory and a processor; the memory stores a computer program; and when the processor executes the computer program, it implements any step of the above-described interrupt or exception event handling method.

[0130] In one embodiment, a computer-readable storage medium is provided having a computer program stored thereon that, when executed by a processor, can implement any step of the above interrupt or exception event handling method.

[0131] Those skilled in the art will understand that embodiments of this application can be provided as methods, systems, or computer program products. Therefore, this application can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this application can take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0132] This application is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this application. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart... Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0133] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0134] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0135] Although preferred embodiments of this application have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of this application.

[0136] Obviously, those skilled in the art can make various modifications and variations to this application without departing from the spirit and scope of this application. Therefore, if such modifications and variations fall within the scope of the claims of this application and their equivalents, this application also intends to include such modifications and variations.

Claims

1. A method for handling interruption or abnormal events, characterized in that, The method is applied in a processor, the processor comprising: an instruction fetch unit, a microinstruction splitting unit, an execution unit, a first register file, a second register file, and a write-back unit; the method includes: After the write-back unit detects an interrupt or abnormal event, it flushes the pipeline and triggers a hardware push operation; wherein, the push operation includes a push micro-instruction sequence, which is an internal microcode instruction, control signal or micro-operation start instruction pre-embedded in the processor hardware control logic; Based on the push operation, while the instruction fetch unit sequentially fetches the instructions to be processed, the micro-instruction splitting unit simultaneously splits the push micro-instruction sequence of the hardware push into register file switching instructions, stack pointer switching instructions, and stack space allocation instructions; the instructions to be processed include: instructions to be executed and pop instructions; the push micro-instruction sequence is a pre-set instruction sequence; the pop instructions are located after the instructions to be processed. The microinstruction splitting unit switches the currently used first register file to the second register file based on the register file switching instruction; and sends the instruction to be executed to the execution unit; wherein the second register file is physically isolated from the first register file; The micro-instruction splitting unit splits the pop instruction into a pop micro-instruction sequence; and switches the stack pointer from a normal state pointer to an interrupt stack pointer based on the stack pointer switching instruction, so that the pointers during interrupt or exception event handling are all interrupt stack pointers. Based on the stack space creation instruction, a stack space is created in the external memory; Store the instructions to be executed that represent the exception return address, interrupt enable and privilege state, and interrupt or exception reason in the instruction to be executed into the opened stack space; The execution unit executes the instruction to be executed to perform interrupt or exception handling, and stores the intermediate data and / or result data generated after execution into the second register file; Based on the pop micro-instruction sequence, the instructions to be executed that represent the exception return address, interrupt enable and privilege state, and interrupt or exception reason are written back to the status register, and the stack space opened in the external memory is returned. Based on the pop microinstruction sequence, the second register file is switched to the first register file, which is used to store instructions for the normal program.

2. The interruption or abnormal event handling method according to claim 1, characterized in that, The processor includes: a decoding unit; The step of sending the instruction to be executed to the execution unit includes: The instruction to be executed is sent to the execution unit via the decoding unit, which is used to decode the sub-instruction to be executed.

3. A processor, characterized in that, include: The write-back unit is configured to flush the pipeline and trigger a hardware push operation after detecting an interrupt or abnormal event; wherein the push operation includes a push micro-instruction sequence, which is an internal microcode instruction, control signal or micro-operation start instruction pre-embedded in the processor hardware control logic; The instruction fetch unit is configured to sequentially fetch instructions to be processed based on the push operation; the instructions to be processed include: instructions to be executed and pop instructions; the push micro-instruction sequence is a pre-set instruction sequence; the pop instructions are located after the instructions to be processed. The micro-instruction splitting unit is configured to synchronously split the push micro-instruction sequence of hardware push operations based on the push operation, obtaining register file switching instructions, stack pointer switching instructions, and stack space allocation instructions; based on the register file switching instructions, switch the currently used first register file to a second register file; and send the instruction to be executed to the execution unit, wherein the second register file is physically isolated from the first register file; the micro-instruction splitting unit splits the pop instruction into a pop micro-instruction sequence; and based on the stack pointer switching instructions, switches the stack pointer from a normal state pointer to an interrupt stack pointer, so that the pointers during interrupt or exception event handling are all interrupt stack pointers; based on the stack space allocation instructions, allocate stack space in external memory; and store the instructions to be executed that represent the exception return address, interrupt enable and privilege state, and interrupt or exception cause in the instructions to be executed into the allocated stack space; The execution unit is configured to execute the instruction to be executed for interrupt or exception handling, and store the intermediate data and / or result data generated after execution into the second register file; based on the pop micro-instruction sequence, write the instruction to be executed representing the exception return address, interrupt enable and privilege state, and interrupt or exception reason back to the status register, and return the stack space opened in the external memory; based on the pop micro-instruction sequence, switch the second register file to the first register file, the first register file being used to store the instructions of the normal program.

4. The processor according to claim 3, characterized in that, Also includes: A decoding unit is configured to send the instruction to be executed to the execution unit via the decoding unit, the decoding unit being used to decode the sub-instruction to be executed.

5. An electronic device, characterized in that, include: Memory; processor; as well as Computer programs; The computer program is stored in the memory and configured to be executed by the processor to implement the method as described in any one of claims 1-2.

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