Semiconductor structure and forming method thereof

Abstract

The invention provides a semiconductor structure. The semiconductor structure includes a substrate and a word line. A word line is embedded in a substrate, the word line including a high work function layer and a low work function layer on the high work function layer, where an average work function of the high work function layer is greater than an average work function of the low work function layer, the low work function layer including a lower portion and an upper portion on the lower portion, and an average grain size of the lower portion is smaller than an average grain size of the upper portion. The semiconductor structure improves the performance of the word line, such as reducing current leakage, reducing drain leakage current caused by a gate, increasing dopants in the word line, reducing resistance and the like.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to a semiconductor structure and a method of forming the same. BACKGROUND

[0002] Word lines are used in semiconductor structures, such as in dynamic random-access memory (DRAM) devices. In order to improve the electrical performance of the word lines, dopants can be doped into the word lines. However, as the doping concentration of the dopants increases, the work function of the material in the word lines can change, and the undesired work function can cause gate-induced drain leakage (GIDL). Therefore, there is a need to develop a novel word line and a novel method of forming the same to improve the electrical performance of the word lines and reduce gate-induced drain leakage. SUMMARY

[0003] A semiconductor structure is provided. The semiconductor structure includes a substrate and a word line. The word line is embedded in the substrate, and the word line includes a high work function layer and a low work function layer on the high work function layer, wherein an average work function of the high work function layer is greater than an average work function of the low work function layer, the low work function layer includes a lower portion and an upper portion on the lower portion, and an average grain size of the lower portion is less than an average grain size of the upper portion.

[0004] In some embodiments, the average grain size of the lower portion is 1 nm to 5 nm, and the average grain size of the upper portion is 5 nm to 20 nm.

[0005] In some embodiments, the average work function of the lower portion is greater than the average work function of the upper portion.

[0006] In some embodiments, the average work function of the high work function layer is greater than the average work function of the lower portion.

[0007] In some embodiments, a plurality of dopant concentrations in the lower portion and the upper portion are greater than 1 x 10 20 atoms / cm 3 .

[0008] In some embodiments, a ratio of a thickness of the lower portion to a thickness of the upper portion is 1:1 to 1:10.

[0009] In some embodiments, the high work function layer is a metal layer, and the low work function layer is a silicon-containing conductive layer.

[0010] In some embodiments, the semiconductor structure further includes a dielectric layer between the word line and the substrate.

[0011] In some embodiments, the semiconductor structure further comprises a barrier layer between the high work function layer and the low work function layer.

[0012] In some embodiments, the semiconductor structure further comprises a dielectric layer on the low work function layer.

[0013] The present disclosure also provides a method of forming a semiconductor structure. The method comprises the following operations. A first work function layer and a second work function layer are formed in a trench of a substrate on the first work function layer, wherein the second work function layer comprises a lower portion and an upper portion on the lower portion, the lower portion has a first average grain size, and the upper portion has a second average grain size. The upper portion is annealed by laser annealing to change the second average grain size to a third average grain size, wherein the third average grain size is greater than the first average grain size.

[0014] In some embodiments, after the upper portion is annealed, an average work function of the first work function layer is greater than an average work function of the second work function layer.

[0015] In some embodiments, the first average grain size and the second average grain size are the same.

[0016] In some embodiments, the laser annealing is performed at an intensity of 250 mJ / cm 2 to 400 mJ / cm 2 .

[0017] In some embodiments, a ratio of a thickness of the lower portion to a thickness of the upper portion is 1:1 to 1:10.

[0018] In some embodiments, forming the second work function layer comprises in-situ doping a dopant, and a concentration of the dopant is greater than 1x10 20 atoms / cm 3 .

[0019] In some embodiments, forming the second work function layer comprises using a precursor gas, and the precursor gas comprises monosilane, disilane, dichlorosilane, or a combination thereof.

[0020] In some embodiments, the method further comprises, before forming the first work function layer and the second work function layer, forming a dielectric layer on a sidewall of the trench.

[0021] In some embodiments, the method further comprises, after forming the first work function layer and before forming the second work function layer, forming a barrier layer on the first work function layer.

[0022] In some embodiments, the method further comprises, after annealing the upper portion, forming a dielectric layer on the second work function layer. BRIEF DESCRIPTION OF DRAWINGS

[0023] The present application can be more fully understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0024] Figure 1 is a cross-sectional view of a portion of a word line embedded in a substrate in a semiconductor structure according to some embodiments of the application.

[0025] Figure 2 is a flowchart of a method of forming a semiconductor structure according to some embodiments of the application.

[0026] Figures 3 to 7 is a cross-sectional view of a portion of a structure in a stage of forming a semiconductor structure according to some embodiments of the application. DETAILED DESCRIPTION

[0027] In order to make the description of the application more detailed and complete, the following describes various aspects of the embodiments illustratively, but not limit the embodiments of the application to only one form. The embodiments of the application can be combined or replaced with each other as appropriate, or other embodiments can be added without further description.

[0028] In addition, in the present application, spatial relative terms, such as under and over, can be used to describe a relationship of one component (or feature) to another component (or feature) in the drawings. In addition to the orientation described in the drawings, the spatial relative terms are intended to encompass different orientations of the device in use or operation. For example, the device can be oriented in other ways (e.g., rotated 90 degrees) and can be correspondingly interpreted by the spatial relative terms. In the present application, unless otherwise specified, the same component symbols in different drawings refer to the same or similar components formed of the same or similar materials by the same or similar methods.

[0029] The terms "about", "approximately", "substantially", "essentially", "virtually" and the like used in the present application include the value (or feature) as understood by one of ordinary skill in the art and a deviation from the value (or feature). For example, considering the error of the value (or feature), these terms can represent a value within one or more standard deviations (e.g., a value within ±30%, ±20%, ±15%, ±10%, or ±5%), or a deviation that the feature includes in practical operation (e.g., "substantially parallel" can mean close to parallel in practical operation, not ideal perfect parallel). In addition, the acceptable deviation range can be selected according to the nature of the measurement or other properties, not just one deviation range for all values (or features).

[0030] The present application provides a semiconductor structure. The semiconductor structure includes a substrate 101 and a word line 103, as Figure 1The word line 103 is embedded in the substrate 101 and includes a high work function layer 103H and a low work function layer 103L over the high work function layer 103H, where the average work function of the high work function layer 103H is greater than the average work function of the low work function layer 103L, the low work function layer 103L includes a lower portion P1 and an upper portion P2 over the lower portion P1, and the average grain size GS1 of the lower portion P1 is less than the average grain size GS2 of the upper portion P2. Since the average grain size GS1 of the lower portion P1 is less than the average grain size GS2 of the upper portion P2, the undesirable holes and the significant reduction of resistance in the low work function layer 103L that can cause current leakage can be reduced compared to the average grain size of the lower portion P1 being greater than the average grain size of the upper portion P2. In addition, the upper portion P2 having a larger average grain size can reduce the average work function of the low work function layer 103L, so that more dopants can be doped into the low work function layer 103L without increasing the average work function of the low work function layer 103L, thus improving the electrical performance of the word line 103. In addition, the low work function layer 103L having a lower work function than the high work function layer 103H can reduce gate-induced drain leakage. The semiconductor structure of the present application is described in more detail by the following embodiments.

[0031] The substrate 101 is first described. In some embodiments, the substrate 101 is a semiconductor substrate and can include any suitable semiconductor material. In some embodiments, the semiconductor material includes elemental semiconductor materials, such as carbon, monocrystalline silicon, polycrystalline silicon, amorphous silicon, germanium, tin, sulfur, selenium, tellurium, etc.; compound semiconductor materials, such as silicon carbide, boron nitride, aluminum nitride, gallium nitride, gallium phosphide, gallium arsenide, indium phosphide, indium arsenide, indium antimonide, zinc oxide, etc.; alloy semiconductor materials, such as SiGe, AlGaAs, InGaAs, InGaP, AlInAs, GaAsP, AlGaN, InGaN, AlGaInP, etc.; or combinations thereof.

[0032] Next, word line 103 is described. In some embodiments, word line 103 is embedded in substrate 101 to control the switching of the gate in a transistor. In some embodiments, low work function layer 103L of word line 103 serves as the gate. Word line 103 including high work function layer 103H can reduce gate-induced drain leakage compared to a word line that does not include high work function layer 103H. In some embodiments, the semiconductor structure further includes a source and a drain aside the gate. Low work function layer 103L is disposed on high work function layer 103H, and the average work function of high work function layer 103H is greater than the average work function of low work function layer 103L. In some embodiments, the average work function of high work function layer 103H is preferably 4.3 eV to 4.9 eV, such as 4.3 eV, 4.4 eV, 4.5 eV, 4.6 eV, 4.7 eV, 4.8 eV, or 4.9 eV. In some embodiments, the average work function of low work function layer 103L is preferably 4.0 eV to 4.6 eV, such as 4.0 eV, 4.1 eV, 4.2 eV, 4.3 eV, 4.4 eV, 4.5 eV, or 4.6 eV. In some embodiments, high work function layer 103H and low work function layer 103L are electrically conductive. In some embodiments, high work function layer 103H is a metal layer, such as including tungsten, and low work function layer 103L is a silicon-containing electrically conductive layer, such as including polysilicon. In some embodiments, low work function layer 103L is crystalline.

[0033] The low work function layer 103L includes a lower portion P1 and an upper portion P2 on the lower portion P1, and the average grain size GS1 of the lower portion P1 is smaller than the average grain size GS2 of the upper portion P2. In some embodiments, the grain size is different from the crystallite size and the particle size, and the grain size is defined by the boundaries between the grains, where the boundaries between the grains are where the crystal orientation changes. It is found that when the grain size in the material is small, the work function of the material can increase when more dopants are incorporated into the material. Conversely, when the grain size in the material is large, the work function of the material can decrease when more dopants are incorporated into the material. Therefore, in order to have a small grain size to reduce current leakage in the low work function layer 103L, it is preferred to have a portion of the low work function layer 103L with a large grain size to reduce the average work function of the low work function layer 103L, so that the work function of the low work function layer 103L can be smaller than the higher work function in the high work function layer 103H to reduce gate induced drain leakage current. In addition to reducing current leakage and having a small average work function in the low work function layer 103L, in the present application, the lower portion P1 of the low work function layer 103L having a small average grain size and the upper portion P2 of the low work function layer 103L having a large average grain size can also improve the electrical performance of the word line 103, such as reducing the resistance and further reducing current leakage, etc.

[0034] In some embodiments, the average grain size GS1 of the lower portion P1 of the low work function layer 103L is preferably between 1 nm and 5 nm, such as 1 nm, 2 nm, 3 nm, 4 nm, or 5 nm. In some embodiments, the average grain size GS2 of the upper portion P2 of the low work function layer 103L is preferably between 5 nm and 20 nm, such as 5 nm, 10 nm, 15 nm, or 20 nm. In some embodiments, the average work function of the lower portion P1 of the low work function layer 103L is greater than the average work function of the upper portion P2 of the low work function layer 103L. In some embodiments, the average work function of the lower portion P1 of the low work function layer 103L is preferably between 4.1 eV and 4.7 eV, such as 4.1 eV, 4.2 eV, 4.3 eV, 4.4 eV, 4.5 eV, 4.6 eV, or 4.7 eV, and the average work function of the upper portion P2 of the low work function layer 103L is preferably between 3.9 eV and 4.5 eV, such as 3.9 eV, 4.0 eV, 4.1 eV, 4.2 eV, 4.3 eV, 4.4 eV, or 4.5 eV. In some embodiments, the average work function of the high work function layer 103H is greater than the average work function of the lower portion P1 of the low work function layer 103L. In some embodiments, the work function of the word line 103 decreases from the high work function layer 103H, further decreases through the lower portion P1 of the low work function layer 103L, and reaches the upper portion P2 of the low work function layer 103L.

[0035] In some embodiments, the low work function layer 103L (e.g., the lower portion P1 and the upper portion P2) is doped with N-type dopants or P-type dopants to improve the electrical performance of the word line 103. In some embodiments, the dopants doped in the lower portion P1 of the low work function layer 103L and the dopants doped in the upper portion P2 of the low work function layer 103L are the same. In some embodiments, the dopant concentration in the low work function layer 103L (e.g., in the lower portion P1 and the upper portion P2) is preferably greater than 1 x 1019atoms / cm3and less than 1 x 1021atoms / cm3. 20 3 and preferably less than 1 x 1021atoms / cm3. 22 3 In some embodiments, the dopant concentration in the lower portion P1 of the low work function layer 103L and the dopant concentration in the upper portion P2 of the low work function layer 103L are substantially the same.

[0036] ​​In some embodiments, the ratio of the thickness Tl of the lower portion Pl of the low work function layer 103L to the thickness T2 of the upper portion P2 of the low work function layer 103L is preferably 1 : 1 to 1 : 10, such as 1 : 1, 1 : 1.5, 1 : 2.5, 1 : 5, 1 : 7.5, or 1 : 10. In some embodiments, the thickness T2 of the upper portion P2 of the low work function layer 103L is more preferably thicker than the thickness Tl of the lower portion Pl of the low work function layer 103L. In some embodiments, the thickness Tl of the lower portion Pl of the low work function layer 103L is preferably less than 10 nm.

[0037] In some embodiments, the semiconductor structure further comprises a dielectric layer 102 between the word line 103 and the substrate 101 to provide electrical isolation of the word line 103. In some embodiments, the dielectric layer 102 comprises any suitable dielectric material, such as silicon oxide, silicon nitride, or a combination thereof.

[0038] In some embodiments, the semiconductor structure further comprises a barrier layer 104 between the high work function layer 103H and the low work function layer 103L to prevent the high work function layer 103H and the low work function layer 103L from reacting. In some embodiments, the barrier layer 104 covers the entire upper surface of the high work function layer 103H and the entire lower surface of the low work function layer 103L. In some embodiments, the barrier layer 104 extends to cover the side surface of the low work function layer 103L. In some embodiments, the barrier layer 104 is on the dielectric layer 102. In some embodiments, the material of the barrier layer 104 is different from the material of the dielectric layer 102. In some embodiments, the material of the barrier layer 104 is the same as the material of the dielectric layer 102. In some embodiments, the barrier layer 104 comprises silicon oxide, titanium nitride, or a combination thereof.

[0039] In some embodiments, the semiconductor structure further comprises a dielectric layer 105 on the low work function layer 103L to provide electrical isolation of the word line 103. In some embodiments, the dielectric layer 105 covers the entire upper surface of the low work function layer 103L. In some embodiments, the dielectric layer 102 between the word line 103 and the substrate 101 extends to between the dielectric layer 105 and the substrate 101. In some embodiments, the dielectric layer 105 comprises any suitable dielectric material, such as silicon oxide, silicon nitride, or a combination thereof.

[0040] The present disclosure also provides a method 20 of forming the above semiconductor structure. Please refer to Figure 2 the flowchart of the method 20 shown, please also refer to Figure 1 and Figures 3 to 7To understand more details. The method 20 includes operation 21 to operation 22. Operation 21 includes forming a first work function layer 103H' in the trench 201 of the substrate 101 and a second work function layer 103L' on the first work function layer 103H', wherein the second work function layer 103L' includes a lower portion P1' and an upper portion P2' on the lower portion P1', the lower portion P1' has a first average grain size S1, and the upper portion P2' has a second average grain size S2. Operation 22 includes annealing the upper portion P2' by laser annealing to change the second average grain size S2 to a third average grain size S3, wherein the third average grain size S3 is greater than the first average grain size S1. The method 20 of the present disclosure is described in more detail by the following embodiments.

[0041] Referring to Figure 3 Before performing operation 21, in some embodiments, the method 20 can further include forming the trench 201 in the substrate 101 by any suitable etching method, such as by dry etching or wet etching. In some embodiments, the substrate 101 is substantially the same as the substrate 101 in the semiconductor structure described above, which is not repeated here.

[0042] Referring to Figure 4 Before performing operation 21, in some embodiments, the method 20 can further include forming the dielectric layer 102 on the sidewall of the trench 201 by any suitable deposition method, such as by chemical vapor deposition or physical vapor deposition. In some embodiments, the dielectric layer 102 is formed on the exposed surface of the trench 201. In some embodiments, the dielectric layer 102 is conformally formed in the trench 201. In some embodiments, the dielectric layer 102 is substantially the same as the dielectric layer 102 in the semiconductor structure described above, which is not repeated here.

[0043] Referring to Figure 5 Operation 21 includes forming the first work function layer 103H' in the trench 201 of the substrate 101 by any suitable deposition method, such as by chemical vapor deposition or physical vapor deposition. In some embodiments, the first work function layer 103H' is substantially the same as the high work function layer 103H in the semiconductor structure described above, which is not repeated here. In some embodiments, the method 20 can further include forming the barrier layer 104 on the first work function layer 103H' by any suitable deposition method, such as by chemical vapor deposition or physical vapor deposition, after forming the first work function layer 103H'. In some embodiments, the barrier layer 104 is substantially the same as the barrier layer 104 in the semiconductor structure described above, which is not repeated here.

[0044] Referring to Figure 6Operation 21 also includes forming a second work function layer 103L' over the first work function layer 103H' in the trench 201 of the substrate 101. In some embodiments, the second work function layer 103L' becomes substantially the same as the low work function layer 103L in the semiconductor structure described above after performing the subsequent operation 22. In some embodiments, forming the second work function layer 103L' includes using a precursor gas, where the precursor gas forms the second work function layer 103L' by reaction. In some embodiments, the precursor gas includes silane, disilane, dichlorosilane, or a combination thereof. In some embodiments, the flow rate of the precursor gas is preferably 200 sccm to 1000 sccm, such as 200 sccm, 400 sccm, 600 sccm, 800 sccm, or 1000 sccm. In some embodiments, forming the second work function layer 103L' is preferably performed at a pressure of 10 Torr to 100 Torr, such as 10 Torr, 20 Torr, 40 Torr, 60 Torr, 80 Torr, or 100 Torr. In some embodiments, forming the second work function layer 103L' is preferably performed at a temperature of 500 °C to 900 °C, such as 500 °C, 600 °C, 700 °C, 800 °C, or 900 °C. The flow rate, pressure, and temperature can affect the grain size of the second work function layer 103L'.

[0045] In some embodiments, forming the second work function layer 103L' includes in-situ doping a dopant, where the dopant concentration is greater than 1 x 1019atoms / cm3and less than 1 x 1021atoms / cm3to improve the electrical performance of the word line formed after operation 22. In some embodiments, the dopant is an N-type dopant or a P-type dopant. In some embodiments, the barrier layer 104 is formed prior to forming the second work function layer 103L'. 20 atoms / cm 3 and less than 1 x 1021atoms / cm3. 22 atoms / cm 3

[0046] ​The second work function layer 103L' includes a lower portion P1' and an upper portion P2' on the lower portion P1'. In some embodiments, the lower portion P1' is substantially the same as the lower portion P1 in the semiconductor structure described above, which will not be repeated here. For example, the first average grain size S1 of the lower portion P1' is substantially the same as the average grain size GS1 of the lower portion P1 in the semiconductor structure described above. In some embodiments, after performing the subsequent operation 22, the upper portion P2' becomes substantially the same as the upper portion P2 in the semiconductor structure described above. In some embodiments, before performing the operation 22, the upper portion P2' has a second average grain size S2, and in some embodiments, the first average grain size S1 and the second average grain size S2 are substantially the same. In some embodiments, the thickness T1 of the lower portion P1' and the thickness T2 of the upper portion P2' are substantially the same as the thickness T1 of the lower portion P1 and the thickness T2 of the upper portion P2 in the semiconductor structure described above, and in some embodiments, the ratio of the thickness T1 of the lower portion P1' to the thickness T2 of the upper portion P2' is also preferably from 1:1 to 1:10, such as 1:1, 1:1.5, 1:2.5, 1:5, 1:7.5, or 1:10.

[0047] Referring to Figure 7 . The operation 22 includes annealing the upper portion P2' of the second work function layer 103L' by laser annealing to change the second average grain size S2 to a third average grain size S3, where the third average grain size S3 is greater than the first average grain size S1 and the second average grain size S2. By performing the annealing, the orientation of the crystallization can be rearranged in the upper portion P2' of the second work function layer 103L', thus changing the boundaries of the grains and forming a larger grain size. The advantages of having a smaller average grain size in the lower portion of the second work function layer (i.e., the low work function layer) and a larger average grain size in the upper portion of the second work function layer (i.e., the low work function layer) are described above. After performing the operation 22, the low work function layer 103L and the upper portion P2 in the semiconductor structure described above are formed. For example, after annealing the upper portion P2' of the second work function layer 103L', the average work function of the first work function layer 103H' is greater than the average work function of the second work function layer 103L', and the third average grain size S3 is substantially the same as the average grain size GS2 of the upper portion P2. In some embodiments, the intensity of the laser annealing is preferably from 250 mJ / cm 2 to 400 mJ / cm 2 , such as 250 mJ / cm 2 , 300 mJ / cm 2 , 350 mJ / cm 2 , or 400 mJ / cm 2 .

[0048] Referring to Figure 1In some embodiments, the method 20 can further include forming a dielectric layer 105 on the second work function layer 103L' after annealing the upper portion P2' of the second work function layer 103L'. In some embodiments, the dielectric layer 105 is substantially the same as the dielectric layer 105 in the semiconductor structure described above, which will not be repeated here. After forming the dielectric layer 105, the semiconductor structure as shown in FIG. 1C is formed. Figure 1

[0049] The semiconductor structure of the present application and the semiconductor structure formed by the method of the present application improve the performance of the word line, such as reducing current leakage, reducing gate-induced drain leakage, increasing dopant in the word line, reducing resistance, etc.

[0050] The present application has been described in considerable detail with specific reference to some embodiments thereof. Other embodiments can be possible, however, without departing from the scope and spirit of the present application. The description of the embodiments is intended to be illustrative, and not to limit the scope and spirit of the appended claims. Modifications and changes can be suggested to one skilled in the art, and incorporated into the present application, without departing from the scope and spirit of the present application. Such modifications and changes are intended to be within the scope and spirit of the present application, as defined by the appended claims.

[0051] SYMBOL DESCRIPTION

[0052] 20: method

[0053] 21: operation

[0054] 22: operation

[0055] 101: substrate

[0056] 102: dielectric layer

[0057] 103: word line

[0058] 103H: high work function layer

[0059] 103H': first work function layer

[0060] 103L: low work function layer

[0061] 103L': second work function layer

[0062] 104: barrier layer

[0063] 105: dielectric layer

[0064] 201: trench

[0065] GS1: average grain size

[0066] GS2: average grain size

[0067] P1: lower portion ​

[0068] P1': lower portion

[0069] P2: upper portion

[0070] P2': upper portion

[0071] S1 : first average grain size

[0072] S2: second average grain size

[0073] S3: third average grain size

[0074] T1 : thickness

[0075] T2: thickness.

Claims

1. A semiconductor structure, characterized in that, include: substrate; as well as The character line is embedded in the substrate. The character line includes a high power function layer and a low power function layer on the high power function layer. The average power function of the high power function layer is greater than the average power function of the low power function layer. The low power function layer includes a lower part and an upper part on the lower part. The average grain size of the lower part is smaller than the average grain size of the upper part.

2. The semiconductor structure according to claim 1, wherein the average grain size of the lower portion is 1 nm to 5 nm, and the average grain size of the upper portion is 5 nm to 20 nm.

3. The semiconductor structure according to claim 1, wherein the average work function of the lower part is greater than the average work function of the upper part.

4. The semiconductor structure according to claim 1, wherein the average work function of the high work function layer is greater than the average work function of the lower layer.

5. The semiconductor structure according to claim 1, wherein the concentration of the plurality of dopants in the lower and upper portions is greater than 1 x 10⁻⁶. 20 atoms / cm 3 .

6. The semiconductor structure according to claim 1, wherein the ratio of the thickness of the lower portion to the thickness of the upper portion is 1:1 to 1:

10.

7. The semiconductor structure according to claim 1, wherein the high work function layer is a metal layer and the low work function layer is a silicon-containing conductive layer.

8. The semiconductor structure according to claim 1, wherein, It also includes a dielectric layer between the character line and the substrate.

9. The semiconductor structure according to claim 1, wherein, It also includes a barrier layer between the high power function layer and the low power function layer.

10. The semiconductor structure according to claim 1, wherein, It also includes a dielectric layer on this low work function layer.

11. A method for forming a semiconductor structure, characterized in that, include: A first work function layer and a second work function layer are formed in a trench of a substrate. The second work function layer includes a lower portion and an upper portion above the lower portion. The lower portion has a first average grain size, and the upper portion has a second average grain size. as well as The upper part is annealed by laser annealing to change the second average grain size into a third average grain size, wherein the third average grain size is larger than the first average grain size.

12. The method of claim 11, wherein after the annealing of the upper portion, the average work function of the first work function layer is greater than the average work function of the second work function layer.

13. The method of claim 11, wherein the first average grain size and the second average grain size are the same.

14. The method of claim 11, wherein the laser annealing is at 250 mJ / cm 2 Up to 400mJ / cm 2 The intensity is carried out.

15. The method of claim 11, wherein the ratio of the thickness of the lower portion to the thickness of the upper portion is 1:1 to 1:

10.

16. The method of claim 11, wherein forming the second work function layer comprises in-situ doping with a dopant, and the concentration of the dopant is greater than 1 x 10⁻⁶. 20 atoms / cm 3 .

17. The method of claim 11, wherein forming the second work function layer comprises using a precursor gas, and the precursor gas comprises silane, silane, dichlorosilane, or a combination thereof.

18. The method according to claim 11, wherein, It also includes forming a dielectric layer on the sidewall of the trench before forming the first work function layer and the second work function layer.

19. The method according to claim 11, wherein, It also includes forming a barrier layer on the first work function layer after the first work function layer is formed and before the second work function layer is formed.

20. The method according to claim 11, wherein, It also includes forming a dielectric layer on the second work function layer after the upper part is annealed.

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