Three-dimensional storage and near storage computing architecture

Abstract

The invention provides a three-dimensional storage and near storage computing architecture which can be applied to the technical field of circuit design. The three-dimensional storage and near-storage computing architecture comprises a control layer, which comprises a gating module and a driving module; the plurality of storage layers are stacked on the surface of the control layer, and each storage layer comprises a plurality of storage units; wherein the gating module is used for controlling a target storage layer in the plurality of storage layers to be in a working state under the control of a gating signal; and the driving module is used for controlling the target storage unit in the target storage layer to execute read-write operation.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of circuit design, and more particularly to a three-dimensional storage and near-memory computing architecture. BACKGROUND

[0002] For the accelerator of storage-intensive large model applications, high-bandwidth memory or resistive random access memory is usually used to realize high-density storage, but the above-mentioned device manufacturing process is complex and has large process fluctuations, and the cost is high, and it is not enough to support the read and write operations of too much data. SUMMARY

[0003] In view of the above problems, the present disclosure provides a three-dimensional storage and near-memory computing architecture.

[0004] According to a first aspect of the present disclosure, a three-dimensional storage and near-memory computing architecture is provided, comprising: a control layer comprising a gating module and a driving module; a plurality of storage layers stacked on the surface of the control layer, the storage layer comprising a plurality of storage units; wherein the gating module is configured to control a target storage layer in the plurality of storage layers to be in a working state under the control of a gating signal; and the driving module is configured to control a target storage unit in the target storage layer to perform a read or write operation.

[0005] According to an embodiment of the present disclosure, the storage unit comprises a first transistor and a second transistor; the driving module comprises a first voltage driving module, a second voltage driving module and a third voltage driving module; wherein a first end of the first transistor is configured to access a voltage provided by the first voltage driving module; a second end of the first transistor and a control end of the second transistor are connected, and a control end of the first transistor is configured to access a voltage provided by the second voltage driving module; and a first end of the second transistor is configured to access a voltage provided by the third voltage driving module.

[0006] According to an embodiment of the present disclosure, the storage layer further comprises a plurality of first switches and a plurality of second switches, wherein the control ends of the plurality of first switches are connected to each other, and the control ends of the plurality of second switches are connected to each other; a first end of the first switch is electrically connected to a first end of at least one first transistor, and a second end of the first switch is connected to a second end of a first switch of each of the plurality of storage layers, and is configured to access a voltage provided by the first voltage driving module; a first end of the second switch is electrically connected to a control end of at least one first transistor, and a second end of the second switch is connected to a second end of a second switch of each of the plurality of storage layers, and is configured to access a voltage provided by the second voltage driving module.

[0007] According to an embodiment of the present disclosure, the gating module comprises a first multiplexer; the first multiplexer comprises a first input end, a first gating end and a plurality of first output ends, the first input end is used for accessing the working level signal, the first gating end is used for accessing the first gating signal, and the plurality of first output ends correspond to the plurality of storage layers respectively, and the first output end is electrically connected to the control end of the plurality of first switches and the control end of the plurality of second switches included in the corresponding storage layer; wherein, under the control of the first gating signal, the first multiplexer is used for providing the working level signal from the first input end to the control end of the plurality of first switches and the control end of the plurality of second switches included in the target storage layer, so as to turn on the plurality of first switches and the plurality of second switches included in the target storage layer, so that the target storage layer is in a data writing state.

[0008] According to an embodiment of the present disclosure, the first multiplexer is used for controlling the first switch and the second switch of the target storage unit to be in a turn-on state under the control of the gating signal; the first voltage driving module is used for providing the first voltage or the second voltage to the first end of the first transistor through the first switch in the turn-on state, wherein the voltage value of the first voltage is higher than the voltage value of the second voltage; the second voltage driving module is used for providing the first voltage to the control end of the first transistor through the second switch in the turn-on state; wherein the first transistor performs a write operation based on the first voltage and the second voltage.

[0009] According to an embodiment of the present disclosure, the three-dimensional storage and near-computing architecture further comprises a plurality of third switches; wherein the control ends of the plurality of third switches are connected to each other; the first end of the third switch is electrically connected to the first end of at least one second transistor, the second end of the third switch is connected to the second end of one third switch of each of the plurality of storage layers, and is used for accessing the voltage provided by the third voltage driving module.

[0010] According to an embodiment of the present disclosure, the gating module comprises a second multiplexer; the second multiplexer comprises a second input end, a second gating end and a plurality of second output ends, the second input end is used for accessing the working level signal, the second gating end is used for accessing the second gating signal, and the plurality of second output ends correspond to the plurality of storage layers respectively, and the second output end is electrically connected to the control end of the plurality of third switches included in the corresponding storage layer; wherein, under the control of the second gating signal, the second multiplexer is used for providing the working level signal from the second input end to the control end of the plurality of third switches included in the target storage layer, so as to turn on the plurality of third switches included in the target storage layer, so that the target storage layer is in a data reading state.

[0011] According to an embodiment of the present disclosure, the second multiplexer is configured to control the third switch of the target storage unit to be in a conductive state under the control of the gate signal; and the third voltage driving module is configured to provide the first voltage or the second voltage to the first end of the second transistor through the third switch in the conductive state, wherein the first voltage has a voltage value higher than that of the second voltage.

[0012] According to an embodiment of the present disclosure, the control layer further comprises a current sensitive amplifier connected to the second end of the second transistor.

[0013] According to an embodiment of the present disclosure, the three-dimensional storage and near-memory computing architecture further comprises a multiplier and an adder, both of which are connected to the current sensitive amplifier.

[0014] According to an embodiment of the present disclosure, a plurality of storage layers are stacked on the surface of the control layer, and under the control of the gate signal of the gating module of the control layer, a target storage layer in the plurality of storage layers is controlled to be in a working state, and the driving module of the control layer controls the target storage unit in the target storage layer to perform a read-write operation. Due to the stacked arrangement of the plurality of storage layers, the area utilization is improved, and the data storage density is effectively improved. Each layer of the storage layer is respectively provided with a first switch, a second switch and a third switch, and the driving module and the gating module are integrated in the control layer, so that the voltage driving module does not need to be arranged correspondingly in each layer, thereby effectively reducing the cost loss. BRIEF DESCRIPTION OF DRAWINGS

[0015] The above and other objects, features and advantages of the present disclosure will become more apparent from the following description of embodiments of the present disclosure taken in conjunction with the accompanying drawings, in which:

[0016] Figure 1 A structural block diagram of a three-dimensional storage and near-memory computing architecture according to an embodiment of the present disclosure is shown;

[0017] Figure 2 A schematic diagram of a first transistor and a second transistor according to an embodiment of the present disclosure is shown;

[0018] Figure 3 A three-dimensional schematic diagram of a switch according to an embodiment of the present disclosure is shown;

[0019] Figure 4 A two-dimensional schematic diagram of a switch according to an embodiment of the present disclosure is shown;

[0020] Figure 5 A schematic diagram of a three-dimensional storage and near-memory computing architecture according to an embodiment of the present disclosure is shown;

[0021] Figure 6 A read-write operation waveform diagram according to an embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0022] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. It is to be understood, however, that the description is merely exemplary and is not intended to limit the scope of the present disclosure. In the following detailed description of the embodiments of the present disclosure, numerous specific details are set forth in order to provide a thorough understanding of the embodiments of the present disclosure. It will be apparent, however, that one or more embodiments can be practiced without these specific details. In other instances, well-known structures and functions are not described in detail in order to avoid obscuring the concept of the present disclosure.

[0023] The terms used herein are merely used to describe specific embodiments and are not intended to limit the present disclosure. The terms "include", "comprise" and the like used herein indicate the presence of the described features, steps, operations, and / or components, but do not exclude the presence or addition of one or more other features, steps, operations, or components.

[0024] All terms used herein, including technical and scientific terms, have the same meanings as those generally understood by those skilled in the art unless otherwise defined. It should be noted that the terms used herein should be interpreted as having meanings consistent with the context of the present description, and should not be interpreted in an idealized or excessively formal manner.

[0025] In the case of using expressions similar to "at least one of A, B, and C, etc.", it should be generally interpreted as including one or more of the items enumerated in the list (e.g., "a system having at least one of A, B, and C" should include, but not be limited to, a system having A alone, a system having B alone, a system having C alone, a system having both A and B, a system having both A and C, a system having both B and C, and / or a system having A, B, and C, etc.).

[0026] Figure 1 A structural block diagram of a three-dimensional storage and near-memory computing architecture according to an embodiment of the present disclosure is shown.

[0027] According to a first aspect of the present disclosure, a three-dimensional storage and near-memory computing architecture is provided, as Figure 1 As shown, it includes a control layer 100 including a gating module 110 and a driving module 120; a plurality of storage layers 200 stacked on the surface of the control layer 100, the storage layer 200 including a plurality of storage units 210; wherein the gating module 110 is configured to control a target storage layer 200 in the plurality of storage layers 200 to be in an active state under the control of a gating signal; and the driving module 120 is configured to control a target storage unit 210 in the target storage layer 200 to perform a read / write operation.

[0028] According to an embodiment of the present disclosure, the control layer 100 is the bottom structure of the three-dimensional storage and near-memory computing architecture, which collects peripheral circuits including the gating module 110 and the driving module 120.

[0029] According to an embodiment of the present disclosure, the storage layer 200 is configured to store data, wherein the three-dimensional storage and near-memory computing architecture is provided with a plurality of storage layers 200, which are arranged in a three-dimensional stack on the control layer 100, thereby effectively improving the area utilization of the three-dimensional storage and near-memory computing architecture and realizing high-density data storage.

[0030] Each storage layer 200 includes at least one storage unit 210, which can be an IGZO-2T0C storage unit 210. In any one storage layer 200, a plurality of storage units 210 can be arranged in a two-dimensional matrix array, or the arrangement of a plurality of storage units 210 can be set according to actual needs, which is not limited here.

[0031] The gating module 110 is configured to select one storage layer 200 from the plurality of storage layers 200 under the control of a gate signal and make it a target storage layer 200 to be in a working state to perform read / write operations. In addition, two storage layers 200 can also be selected as target storage layers 200 to perform read and write operations in parallel, thereby improving the working efficiency of the three-dimensional storage and near-memory computing architecture.

[0032] The above-mentioned gate signal can be a signal input to the gating module 110 by an external input device, which is used to select the target storage layer 200. The gating module 110 can include a multiplexer, which selects a specified output end according to the above-mentioned gate signal to select the target storage layer 200 based on the specified output end.

[0033] The above-mentioned driving module 120 can include a voltage driving module 120, which can include a voltage driver and a voltage converter, configured to provide a voltage to the target storage layer 200 to control the target storage unit 210 in the target storage layer 200 to perform read / write operations.

[0034] According to an embodiment of the present disclosure, for the target storage layer 200 in the working state, the driving module 120 provides a voltage to the target storage unit 210. For the write operation, the driving module 120 provides different voltages to the target storage unit 210 to store data "0" or "1" in the target storage unit 210. For the read operation, the driving module 120 provides different voltages to the target storage unit 210, and then based on the difference between the data "0" and "1" stored in the target storage unit 210, the current flow in the target storage unit 210 is different, so that the data stored in the target storage unit 210 can be read based on the current change.

[0035] According to an embodiment of the present disclosure, a plurality of storage layers are stacked on the surface of the control layer, and under the control of the gate signal of the gate module of the control layer, a target storage layer in the plurality of storage layers is controlled to be in a working state, and the driving module of the control layer controls the target storage unit in the target storage layer to perform a read-write operation. Due to the stacked arrangement of the plurality of storage layers, the area utilization is improved, the data storage density is effectively improved, and the driving module and the gate module are integrated in the control layer, without the need to arrange a voltage driving module for each layer, thereby effectively reducing the cost loss.

[0036] Figure 2 A schematic diagram of a first transistor and a second transistor according to an embodiment of the present disclosure is shown.

[0037] According to an embodiment of the present disclosure, as shown in Figure 2 The storage unit includes a first transistor T1 and a second transistor T2; the driving module includes a first voltage driving module, a second voltage driving module, and a third voltage driving module; wherein the first end WBL of the first transistor T1 is used to access the voltage provided by the first voltage driving module; the second end of the first transistor T1 and the control end of the second transistor T2 are connected, and the control end WWL of the first transistor T1 is used to access the voltage provided by the second voltage driving module; the first end RWL of the second transistor T2 is used to access the voltage provided by the third voltage driving module; and the second end RBL of the second transistor T2 is used to access the voltage provided by the external driving module.

[0038] According to an embodiment of the present disclosure, the first voltage driving module provides a voltage to the first transistor T1, and the voltage is transmitted from the first end WBL of the first transistor T1 to the second end of the first transistor T1. According to the voltage value of the voltage, the data "0" or "1" is stored in the storage node SN.

[0039] The second voltage driving module provides a voltage to the control end WWL of the first transistor T1, and when the control end WWL of the first transistor T1 receives a high voltage, the first transistor T1 can be controlled to be turned on, so that the voltage provided by the first voltage driving module can be transmitted in the first transistor T1 to complete the storage of data.

[0040] According to an embodiment of the present disclosure, the third voltage driving module provides a voltage to the first end RWL of the second transistor T2, and the external voltage driving module provides a voltage to the second end RBL of the second transistor T2, so that the first end RWL and the second end of the second transistor T2 have a voltage difference, so that a current is formed between the first end RWL and the second end of the second transistor T2.

[0041] The control end of the second transistor T2 is connected with the second end of the first transistor T1, and the conduction state of the second transistor T2 is different based on different storage data, so that the current generated by the second transistor T2 is different, thereby being capable of distinguishing different storage data in the read operation.

[0042] According to an embodiment of the present disclosure, the storage layer further comprises a plurality of first switches and a plurality of second switches, wherein the control ends of the plurality of first switches are connected with each other, and the control ends of the plurality of second switches are connected with each other; the first end of the first switch is electrically connected to the first end of the at least one first transistor, and the second end of the first switch is connected with the second end of the first switch of each of the plurality of storage layers, for accessing the voltage provided by the first voltage driving module; the first end of the second switch is electrically connected to the control end of the at least one first transistor, and the second end of the second switch is connected with the second end of the second switch of each of the plurality of storage layers, and the second end of the second switch is used for accessing the voltage provided by the second voltage driving module.

[0043] Figure 3 A three-dimensional schematic diagram of a switch is shown according to an embodiment of the present disclosure; Figure 4 A two-dimensional schematic diagram of a switch is shown according to an embodiment of the present disclosure.

[0044] As shown in Figure 3 and Figure 4 Each of the storage layers (2T0C) comprises a plurality of first switches (WBL switches) and a plurality of second switches (WWL switches).

[0045] According to an embodiment of the present disclosure, the control ends of the plurality of first switches are connected in series, and when the target storage layer is selected, the plurality of first switches of the target storage layer can be turned on at the same time, so that each storage unit can receive the voltage provided by the first voltage driving module.

[0046] According to an embodiment of the present disclosure, the control ends of the plurality of second switches are connected in series, and when the target storage layer is selected, the plurality of second switches of the target storage layer can be turned on at the same time, so that each storage unit can receive the voltage provided by the second voltage driving module.

[0047] The control end of the first switch and the control end of the second switch are connected for the first switch and the second switch of the same storage layer.

[0048] According to an embodiment of the present disclosure, after the first switch is turned on, the voltage provided by the first driving module is transmitted to the second end of the first switch, and then transmitted to the first end of the first switch, and the voltage is provided from the first end of the first switch to the first end of the first transistor.

[0049] According to an embodiment of the present disclosure, after the second switch is turned on, the voltage provided by the second driving module is transmitted to the second end of the second switch, and then transmitted to the first end of the second switch, and the voltage is provided to the control end of the first transistor from the first end of the second switch.

[0050] According to an embodiment of the present disclosure, by setting the first switch and the second switch, the target storage layer can be selected for data write operation, and the stability of the storage structure during read and write operation can be ensured.

[0051] According to an embodiment of the present disclosure, the gating module includes a first multiplexer; the first multiplexer includes a first input end, a first gating end and a plurality of first output ends, the first input end is used for accessing a working level signal, the first gating end is used for accessing a first gating signal, the plurality of first output ends correspond to the plurality of storage layers respectively, and the first output end is electrically connected to the control ends of the plurality of first switches and the control ends of the plurality of second switches included in the corresponding storage layer; wherein, under the control of the first gating signal, the first multiplexer is used for providing the working level signal from the first input end to the control ends of the plurality of first switches and the control ends of the plurality of second switches included in the target storage layer, so as to turn on the plurality of first switches and the plurality of second switches included in the target storage layer, so that the target storage layer is in a data write state.

[0052] According to an embodiment of the present disclosure, when the first multiplexer receives the first gating signal, the first multiplexer determines a specified first output end based on the first gating signal, so as to output the working level signal received by the first input end to the target storage layer through the specified first output end; when the control ends of the plurality of first switches and the control ends of the plurality of second switches of the target storage layer receive the working level signal, the plurality of first switches and the plurality of second switches are in a turned-on state, so that the voltage provided by the first driving module and the second driving module can be input to the first transistor of the target storage layer, so that the target storage layer starts to perform data write operation, and the target storage layer is in a data write state.

[0053] According to an embodiment of the present disclosure, since the first multiplexer is set, which storage layer performs write operation can be controlled based on the gating signal, and the management efficiency of the three-dimensional storage and near storage computing architecture during write operation can be improved.

[0054] According to an embodiment of the present disclosure, the first multiplexer is configured to control the first switch and the second switch of the target storage unit to be in a conductive state under the control of the strobe signal; the first voltage driving module is configured to provide the first voltage or the second voltage to the first terminal of the first transistor through the first switch in the conductive state, wherein the voltage value of the first voltage is higher than the voltage value of the second voltage; the second voltage driving module is configured to provide the first voltage to the gate of the first transistor through the second switch in the conductive state; and the first transistor performs a write operation based on the first voltage and the second voltage.

[0055] According to an embodiment of the present disclosure, the first multiplexer determines the output terminal to be in a conductive state based on the strobe signal, and sends the control signal to the control terminals of the first switch and the second switch, so that the first switch and the second switch are in the conductive state.

[0056] According to an embodiment of the present disclosure, when the first switch and the second switch are in the conductive state, the first voltage or the second voltage provided by the first voltage driving module is transmitted to the second terminal of the first switch and then to the first terminal of the first switch, and the voltage is provided to the first terminal of the first transistor by the first terminal of the first switch. The first voltage provided by the second voltage driving module is transmitted to the second terminal of the second switch and then to the first terminal of the second switch, and the voltage is provided to the control terminal of the first transistor by the first terminal of the second switch.

[0057] The voltage value of the first voltage can be 1.8V, and the voltage value of the second voltage can be 0V.

[0058] According to an embodiment of the present disclosure, when the control terminal of the first transistor receives the first voltage, the first transistor is in a conductive state, and the first voltage or the second voltage received by the first terminal of the first transistor can be output to the second terminal of the first transistor, that is, to the storage node SN, so as to complete the writing of data, wherein when the first terminal of the first transistor receives the first voltage, the storage node SN writes 1, and when the first terminal of the first transistor receives the second voltage, the storage node SN writes 0.

[0059] According to an embodiment of the present disclosure, the three-dimensional storage and near-computing architecture further comprises a plurality of third switches; wherein the control terminals of the plurality of third switches are connected to each other; the first terminal of the third switch is electrically connected to the first terminal of at least one second transistor; the second terminal of the third switch is connected to the second terminal of one third switch of each of the plurality of storage layers, and is used to access the voltage provided by the third voltage driving module.

[0060] As shown in FIGS. Figure 3 and Figure 4 Each of the storage layers (2T0C) comprises a plurality of third switches (RWL switches).

[0061] According to an embodiment of the present disclosure, the control ends of the plurality of third switches are connected in series, and when a target storage layer is selected, the plurality of third switches of the target storage layer can be turned on at the same time, so that each storage unit can receive the voltage provided by the third voltage driving module.

[0062] According to an embodiment of the present disclosure, after the third switch is turned on, the voltage provided by the third driving module is transmitted to the second end of the third switch, and then transmitted to the first end of the third switch, and the voltage is provided from the first end of the third switch to the first end of the second transistor.

[0063] According to an embodiment of the present disclosure, by arranging the third switch, the target storage layer can be selected for data readout operation, avoiding simultaneous readout operation of multiple layers of data, and also avoiding simultaneous write operation, thereby ensuring the stability of the storage structure during read and write operations.

[0064] According to an embodiment of the present disclosure, the gating module includes a second multiplexer; the second multiplexer includes a second input end, a second gating end, and a plurality of second output ends, the second input end is used to access a working voltage signal, the second gating end is used to access a second gating signal, the plurality of second output ends correspond to the plurality of storage layers respectively, and the second output end is electrically connected to the control end of the plurality of third switches included in the corresponding storage layer; wherein, under the control of the second gating signal, the second multiplexer is used to provide the working voltage signal from the second input end to the control end of the plurality of third switches included in the target storage layer, so as to turn on the plurality of third switches included in the target storage layer, so that the target storage layer is in a data readout state.

[0065] According to an embodiment of the present disclosure, when the second multiplexer receives the second gating signal, the second multiplexer determines a specified first output end based on the second gating signal, so as to output the working voltage signal received by the first input end to the target storage layer through the specified first output end, and when the control end of the plurality of third switches of the target storage layer receives the working voltage signal, the plurality of third switches are in a turned-on state, so that the voltage provided by the third driving module can be input to the second transistor of the target storage layer, so that the target storage layer starts to perform data read operation, and the target storage layer is in a data readout state.

[0066] According to an embodiment of the present disclosure, since the second multiplexer is arranged, which layer of storage layer performs readout operation can be controlled based on the gating signal, thereby improving the management efficiency of the three-dimensional storage and near-storage computing architecture when performing readout operation.

[0067] According to an embodiment of the present disclosure, the second multiplexer is configured to control the third switch of the target storage unit to be in a conductive state under the control of the strobe signal; and the third voltage driving module is configured to provide the first voltage or the second voltage to the first terminal of the second transistor through the third switch in the conductive state, where the first voltage has a voltage value higher than that of the second voltage; and the second transistor is configured to perform a read operation based on the first voltage and the second voltage.

[0068] According to an embodiment of the present disclosure, the second multiplexer is configured to determine the output terminal to be in a conductive state based on the strobe signal, and send a control signal to the control terminal of the third switch so that the third switch is in the conductive state.

[0069] According to an embodiment of the present disclosure, when the third switch is in the conductive state, the first voltage or the second voltage provided by the third voltage driving module is transmitted to the second terminal of the third switch and then to the first terminal of the third switch, and the first terminal of the third switch provides a voltage to the first terminal of the second transistor.

[0070] The voltage value of the first voltage can be 1.8V, and the voltage value of the second voltage can be 0V.

[0071] According to an embodiment of the present disclosure, when the storage node SN writes 1, the control terminal of the second transistor receives the first voltage, the second transistor is in the conductive state, the first terminal of the second transistor receives the second voltage, the second terminal of the second transistor receives the first voltage, a voltage difference is generated between the first terminal of the second transistor and the second terminal of the second transistor, and the current signal of the second terminal of the second transistor changes, so that the data 1 can be read out from the change of the current signal of the second terminal of the second transistor; when the storage node SN writes 0, the control terminal of the second transistor receives the second voltage, the second transistor is not in the conductive state, and the current signal of the second terminal of the second transistor does not change or changes relatively small, so that the data 0 can be read out from the change of the current signal of the second terminal of the second transistor.

[0072] According to an embodiment of the present disclosure, before the read operation is performed, the first terminal and the second terminal of the second transistor both receive the first voltage, and the second voltage is input to the first terminal of the second transistor of the target storage layer only when the read operation is performed. Since the first terminal of the second transistor of each storage unit receives a high voltage before the read operation is performed, the crosstalk and leakage problems between the storage units can be avoided when the read operation is not performed, and the stability of the storage structure when performing the read and write operations is ensured.

[0073] According to an embodiment of the present disclosure, the control layer further comprises a current sensitive amplifier connected to the second terminal of the second transistor.

[0074] According to an embodiment of the present disclosure, the current sensitive amplifier can convert a very weak current signal into a measurable voltage signal while minimizing the noise of the signal.

[0075] According to an embodiment of the present disclosure, when the current of the second end of the second transistor changes, the current sensitive amplifier detects the change of the current signal to determine whether the read data is "0" or "1" according to the change of the current signal.

[0076] According to an embodiment of the present disclosure, the three-dimensional storage and near-memory computing architecture further comprises a multiplier and an adder; both the multiplier and the adder are connected with the current sensitive amplifier.

[0077] According to an embodiment of the present disclosure, the multiplier and the adder are arithmetic logic units in the three-dimensional storage and near-memory computing architecture, and are respectively used for performing multiplication and addition operations.

[0078] According to an embodiment of the present disclosure, after receiving the read data, the current sensitive amplifier sends the data to the multiplier and the adder, and the multiplier and the adder respectively perform multiplication and addition operations on the data to complete the calculation operation on the data.

[0079] Figure 5 A schematic diagram of a three-dimensional storage and near-memory computing architecture according to an embodiment of the present disclosure is shown; Figure 6 A read-write operation waveform diagram according to an embodiment of the present disclosure is shown.

[0080] According to an embodiment of the present disclosure, as Figure 5 shown, the first multiplexer and the second multiplexer of the present disclosure select one of the 2T0C storage layers to perform read-write operation, the first voltage driving module and the second voltage driving module provide voltages to the control end WBL of the first transistor and the first end WWL of the first transistor of the storage layer, and the third voltage driving module provides a voltage to the first end RWL of the second transistor of the storage layer, wherein the data is read by the current sensitive amplifier and output to the multiplier and the adder for data processing operation.

[0081] Specifically, the present disclosure transmits different voltages to the first transistor and the second transistor based on Table 1, so that the three-dimensional storage and near-memory computing architecture completes the read-write operation.

[0082]

[0083] Based on the above Table 1, the target storage unit in the target storage layer is controlled to perform read-write operation, wherein during the read-write operation, the waveform diagram of the read-write operation can be as Figure 6 shown.

[0084] For the storage layer of the 0th layer, based on the write 0 or write 1 in the write operation, the voltage is written to the WWL0 and WBL0 based on the above table 1 respectively, and the respective storage nodes SN0<00>, SN0<01>, SN0<10>, and SN0<11> of the four storage units of the storage layer of the 0th layer write 0 or 1 according to the voltage output to the WWL0 and WBL0. In the read operation, the control layer can read out the data of each layer of the storage layer row by row based on the selection signal, and in the read operation, the voltage is written to the RWL0 and RBL0 based on the above table 1 respectively, so as to read out 0 or 1 according to the current IRBL of the second end of the second transistor.

[0085] According to an embodiment of the present disclosure, in the simulation experiment, a plurality of types of networks are used for simulation experiment. Compared with the related art, the energy efficiency of the three-dimensional storage and near-memory computing architecture of the present disclosure on different types of networks is improved by 8748 times / 8057 times / 1772 times and 3.0 times / 3.0 times / 2.3 times respectively compared with the prior art. The three-dimensional storage and near-memory computing architecture of the present disclosure can achieve a storage density of 1598 Mb / mm2. Compared with the related art, the architecture has an improvement of 29.8 times and 1.87 times in storage density respectively.

[0086] Those skilled in the art can understand that the features described in various embodiments of the present disclosure can be combined and / or combined, even if such combinations or combinations are not explicitly described in the present disclosure. In particular, the features described in various embodiments of the present disclosure can be combined and / or combined without departing from the spirit and teachings of the present disclosure. All these combinations and / or combinations fall within the scope of the present disclosure.

[0087] The above describes embodiments of the present disclosure. However, these embodiments are only for illustrative purposes, and are not intended to limit the scope of the present disclosure. Although each embodiment is described above, this does not mean that the measures in each embodiment cannot be used advantageously in combination. Without departing from the scope of the present disclosure, those skilled in the art can make various alternatives and modifications, which should fall within the scope of the present disclosure.

Claims

1. A three-dimensional storage and near-memory computing architecture, comprising: The control layer includes a gating module and a driver module; Multiple storage layers are stacked on the surface of the control layer, and each storage layer includes multiple storage cells; The gating module is used to control the target storage layer among the multiple storage layers to be in a working state under the control of the gating signal; The driver module is used to control the target storage unit in the target storage layer to perform read and write operations.

2. The three-dimensional storage and near-memory computing architecture according to claim 1, wherein, The storage unit includes a first transistor and a second transistor; the driving module includes a first voltage driving module, a second voltage driving module, and a third voltage driving module. Wherein, the first terminal of the first transistor is used to receive the voltage provided by the first voltage driving module; the second terminal of the first transistor is connected to the control terminal of the second transistor, and the control terminal of the first transistor is used to receive the voltage provided by the second voltage driving module; The first terminal of the second transistor is used to connect to the voltage provided by the third voltage driving module; the second terminal of the second transistor is used to connect to the voltage provided by an external voltage driving module.

3. The three-dimensional storage and near-memory computing architecture according to claim 2, characterized in that, The storage layer also includes multiple first switches and multiple second switches. The control terminals of multiple first switches are interconnected, and the control terminals of multiple second switches are interconnected. The first terminal of the first switch is electrically connected to the first terminal of at least one of the first transistors, and the second terminal of the first switch is interconnected with the second terminal of a first switch of each of the plurality of memory layers, for receiving the voltage provided by the first voltage driving module. The first terminal of the second switch is electrically connected to the control terminal of at least one of the first transistors, and the second terminal of the second switch is interconnected with the second terminal of a second switch of each of the plurality of memory layers. The second terminal of the second switch is used to receive the voltage provided by the second voltage driving module.

4. The three-dimensional storage and near-memory computing architecture according to claim 3, characterized in that, The gating module includes a first multiplexer; the first multiplexer includes a first input terminal, a first gating terminal and multiple first output terminals, the first input terminal is used to receive a working level signal, the first gating terminal is used to receive a first gating signal, the multiple first output terminals correspond to multiple storage layers respectively, and the first output terminals are electrically connected to the control terminals of multiple first switches and multiple second switches included in the corresponding storage layer; Under the control of the first strobe signal, the first multiplexer is used to provide the working level signal from the first input terminal to the control terminals of the multiple first switches and the multiple second switches included in the target storage layer, so as to turn on the multiple first switches and the multiple second switches included in the target storage layer, so that the target storage layer is in a data writing state.

5. The three-dimensional storage and near-memory computing architecture according to claim 4, characterized in that, The first multiplexer is used to control both the first switch and the second switch of the target storage unit to be in the on state under the control of the gating signal; The first voltage driving module is used to provide a first voltage or a second voltage to the first terminal of the first transistor through a first switch in the on state, wherein the voltage value of the first voltage is higher than the voltage value of the second voltage. The second voltage driving module is used to provide a first voltage to the control terminal of the first transistor through a second switch in the on state; The first transistor performs the write operation based on a first voltage and a second voltage.

6. The three-dimensional storage and near-memory computing architecture according to claim 2, characterized in that, The three-dimensional storage and near-memory computing architecture also includes multiple third switches; The control terminals of the multiple third switches are interconnected. The first terminal of the third switch is electrically connected to the first terminal of at least one of the second transistors, and the second terminal of the third switch is interconnected with the second terminal of a third switch of each of the plurality of memory layers for receiving voltage provided by the third voltage drive module.

7. The three-dimensional storage and near-memory computing architecture according to claim 6, characterized in that, The gating module includes a second multiplexer; the second multiplexer includes a second input terminal, a second gating terminal and multiple second output terminals, the second input terminal is used to receive a working level signal, the second gating terminal is used to receive a second gating signal, the multiple second output terminals correspond to multiple memory layers respectively, and the second output terminals are electrically connected to the control terminals of multiple third switches included in the corresponding memory layer; Under the control of the second strobe signal, the second multiplexer provides the working level signal from the second input terminal to the control terminal of the plurality of third switches included in the target storage layer, so as to turn on the plurality of third switches included in the target storage layer, so that the target storage layer is in a data readout state.

8. The three-dimensional storage and near-memory computing architecture according to claim 7, characterized in that, The second multiplexer is used to control the third switch of the target storage unit to be in the on state under the control of the strobe signal; The third voltage driving module is used to provide a first voltage or a second voltage to the first terminal of the second transistor through a third switch in the on state, wherein the voltage value of the first voltage is higher than the voltage value of the second voltage. The second transistor performs the read operation based on a first voltage and a second voltage.

9. The three-dimensional storage and near-memory computing architecture according to claim 8, characterized in that, The control layer also includes a current-sensitive amplifier, which is connected to the second terminal of the second transistor.

10. The three-dimensional storage and near-memory computing architecture according to claim 1, characterized in that, The three-dimensional storage and near-memory computing architecture also includes multipliers and adders; both the multipliers and the adders are connected to the current-sensitive amplifier.

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