Array substrate and preparation method thereof

Abstract

The invention relates to an array substrate and a preparation method thereof. The array substrate comprises a display area and a frame area which are arranged adjacently; the array substrate comprises a substrate; the shifting register is arranged on one side of the substrate and located in the frame area; the shift register comprises a first transistor, wherein the first transistor comprises a first active layer; the pixel circuit is arranged on one side of the substrate and located in the display area; the pixel circuit comprises a second transistor, and the second transistor comprises a second active layer; the carrier mobility of at least part of the first active layer is greater than that of the second active layer, and the material of the first active layer comprises a polycrystalline oxide semiconductor. Therefore, according to the array substrate and the preparation method thereof provided by the invention, the performance of the array substrate and the display panel can be improved.

Description

Array substrate and its fabrication method Technical Field

[0001] This application relates to the field of display technology, and in particular to an array substrate and a method for fabricating the same. Background Technology

[0002] Organic Light Emitting Diode (OLED) display technology is considered the most promising next-generation flat panel display technology. Compared with liquid crystal display technology, OLED display technology has advantages such as low energy consumption, low cost, self-emissiveness, wide viewing angle, and fast response speed.

[0003] In related technologies, the display panel includes a shift register and pixel circuitry, with the shift register used to input gate scan signals to the pixel circuitry. However, the performance of the aforementioned display panel needs improvement. Summary of the Invention

[0004] Therefore, it is necessary to provide an array substrate and its fabrication method, which can improve the performance of the array substrate and the display panel.

[0005] In a first aspect, embodiments of this application provide an array substrate, the array substrate including an adjacent display area and a border area: the array substrate includes:

[0006] substrate;

[0007] A shift register is disposed on one side of the substrate and located in the border area; the shift register includes a first transistor, and the first transistor includes a first active layer;

[0008] A pixel circuit is disposed on one side of a substrate and located in the display area; the pixel circuit includes a second transistor, and the second transistor includes a second active layer;

[0009] In this process, the carrier mobility of at least a portion of the first active layer is greater than that of the second active layer.

[0010] In one embodiment, the material of the first active layer includes a polycrystalline oxide semiconductor;

[0011] In one embodiment, the polycrystalline oxide semiconductor includes at least one of indium oxide, indium gallium oxide, and indium tin gallium oxide;

[0012] In one embodiment, the material of the second active layer includes an amorphous oxide semiconductor; the carrier mobility of the polycrystalline oxide semiconductor is greater than that of the amorphous oxide semiconductor, and the amorphous oxide semiconductor includes indium gallium zinc oxide.

[0013] In one embodiment, the first transistor includes a first gate and a second gate, which are located on opposite sides of the first active layer along the thickness direction of the substrate.

[0014] Preferably, the first active layer and the second active layer are configured on the same layer;

[0015] Preferably, the polycrystalline oxide semiconductor includes at least one of indium oxide, indium gallium oxide, and indium tin gallium oxide;

[0016] Preferably, the amorphous oxide semiconductor includes indium gallium zinc oxide.

[0017] In one embodiment, the second transistor is configured as either a driving transistor or a switching transistor;

[0018] Preferably, the pixel circuit includes a third transistor, the second transistor is configured as a switching transistor, the third transistor is configured as a driving transistor, and the driving transistor includes a third active layer; the carrier mobility of the second active layer is less than or equal to the carrier mobility of the third active layer.

[0019] Preferably, the material of the third active layer includes amorphous oxide semiconductor or polycrystalline oxide semiconductor;

[0020] Preferably, the first active layer and the third active layer are set on the same layer.

[0021] In one embodiment, the driving transistor is a single-gate transistor, and the driving transistor includes a third gate located between the third active layer and the substrate.

[0022] Preferably, the switching transistor is a single-gate transistor, and the switching transistor includes a fourth gate, which is located on the side of the second active layer of the switching transistor away from the substrate.

[0023] In one embodiment, the driving transistor includes a first gate dielectric layer located between a third active layer and a third gate, and the switching transistor includes a second gate dielectric layer located between a second active layer and a fourth gate of the switching transistor.

[0024] The thickness of the first gate dielectric layer is greater than the thickness of the second gate dielectric layer;

[0025] Preferably, the thickness of the first gate dielectric layer is in the range of 3000 angstroms to 5000 angstroms;

[0026] Preferably, the thickness of the second gate dielectric layer is in the range of 900 angstroms to 1500 angstroms.

[0027] In one embodiment, the first active layer includes a first sub-active layer and a second sub-active layer stacked along a direction away from the substrate, wherein the carrier mobility of the first sub-active layer is greater than that of the second sub-active layer.

[0028] Preferably, the material of the first sub-active layer includes a polycrystalline oxide semiconductor, and the material of the second sub-active layer includes an amorphous oxide semiconductor.

[0029] Preferably, the first active layer includes a third sub-active layer, the third sub-active layer is located on the side of the first sub-active layer facing the substrate, and the carrier mobility of the first sub-active layer is greater than that of the third sub-active layer.

[0030] Preferably, the material of the third active layer includes amorphous oxide semiconductor.

[0031] In one embodiment, the shift register includes a fourth transistor, the fourth transistor including a fourth active layer, and the carrier mobility of at least a portion of the first active layer is greater than the carrier mobility of the fourth active layer.

[0032] Preferably, the material of the fourth active layer includes an amorphous oxide semiconductor;

[0033] Preferably, the first active layer and the fourth active layer are set on the same layer.

[0034] Secondly, embodiments of this application provide a method for fabricating an array substrate, the array substrate including an adjacent display area and a border area: the fabrication method includes:

[0035] Provide substrate;

[0036] A shift register and a pixel circuit are formed on one side of a substrate; the shift register is located in the border area and includes a first transistor, the first transistor including a first active layer; the pixel circuit is located in the display area and includes a second transistor, the second transistor including a second active layer; wherein, at least a portion of the carrier mobility of the first active layer is greater than the carrier mobility of the second active layer, and the material of the first active layer includes a polycrystalline oxide semiconductor.

[0037] In one embodiment, a shift register and pixel circuitry are formed on one side of the substrate, including:

[0038] An amorphous material first active material layer is formed on one side of the substrate, and the first active material layer is located in the border area and the display area;

[0039] The first active material layer is subjected to a first patterning and annealing process; the retained first active material layer is at least constructed as at least a portion of the first active layer, and the annealing process transforms the first active material layer from an amorphous material into a polycrystalline material;

[0040] A second active material layer of amorphous material is formed on one side of the substrate, and the second active material layer is located in the border area and the display area;

[0041] The second active material layer is subjected to a second patterning process; the retained second active material layer is at least constructed as a second active layer; the etching reagent for the second patterning process is a first etching reagent, and in the first etching reagent, the etching rate of the second active material layer is greater than the etching rate of the first active material layer after annealing.

[0042] Preferably, in the first etching reagent, the ratio of the etching rate of the second active material layer to the etching rate of the first active material layer after annealing is greater than or equal to 10.

[0043] Preferably, the annealing temperature range is 300℃-500℃.

[0044] Thirdly, embodiments of this application provide a display panel, including an array substrate as described in the first aspect, or an array substrate obtained by the method for preparing the array substrate as described in the second aspect.

[0045] The array substrate and its fabrication method provided in this application embodiment have a carrier mobility of at least a portion of the first active layer that is greater than that of the second active layer. Thus, the first active layer is made of a material with high carrier mobility (i.e., a high-mobility material), which makes the carrier migration path smooth, enables a fast response to the drive signal, improves the signal transmission speed to achieve a high refresh rate, and reduces the device size of the first transistor, thereby reducing the size of the shift register and achieving a narrow bezel. In addition, the second active layer is made of a material with low carrier mobility (i.e., a low-mobility material), which makes the second active layer more stable, reduces the impact of environmental and electrical stress on the second crystal, and makes the threshold voltage drift of the second crystal smaller, resulting in better reliability of the display panel and improved lifespan of the second transistor and the display panel. Attached Figure Description

[0046] To more clearly illustrate the technical solutions in the embodiments or exemplary embodiments of this application, the drawings used in the description of the embodiments or exemplary embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0047] Figure 1 is a top view of the array substrate provided in an embodiment of this application.

[0048] Figure 2 is a cross-sectional view along line AA of Figure 1.

[0049] Figure 3 is a cross-sectional view of the array substrate provided in an embodiment of this application.

[0050] Figure 4 is another cross-sectional view of the array substrate provided in an embodiment of this application.

[0051] Figure 5 is another cross-sectional view of the array substrate provided in an embodiment of this application.

[0052] Figure 6 is another cross-sectional view of the array substrate provided in an embodiment of this application.

[0053] Figure 7 is another cross-sectional view of the array substrate provided in an embodiment of this application.

[0054] Figure 8 is another cross-sectional view of the array substrate provided in an embodiment of this application.

[0055] Figure 9 is another cross-sectional view of the array substrate provided in an embodiment of this application.

[0056] Figure 10 is another cross-sectional view of the array substrate provided in an embodiment of this application.

[0057] Figure 11 is a schematic flowchart of the method for fabricating an array substrate provided in an embodiment of this application.

[0058] Figure 12 is a schematic diagram of the structure after the first patterning process provided in the embodiment of this application.

[0059] Figure 13 is a schematic diagram of the structure after the second patterning process provided in the embodiment of this application.

[0060] Figure 14 is a schematic diagram of the structure during ion implantation provided in an embodiment of this application.

[0061] Figure 15 is a schematic diagram of the structure after ion implantation provided in the embodiment of this application.

[0062] Figure 16 is a schematic diagram of the structure after the formation of the first and second poles provided in the embodiment of this application.

[0063] Explanation of reference numerals in the attached figures:

[0064] 100, Array substrate; 100a, Display area; 100b, Bezel area; 101, Shift register; 102, Pixel circuit; 110, First transistor; 111, First active layer; 111e, First active material layer; 1111, First sub-active layer; 1112, Second sub-active layer; 1113, Third sub-active layer; 1141, First gate; 1142, Second gate; 120, Second transistor; STFT, Switching transistor; 122, Second active layer; 122e, Second active material layer; 1232, Second gate dielectric layer; 1234, Fourth gate; 130, Third transistor; DTFT, Driving transistor; 1311, First gate Dielectric layer; 1313, Third gate; 133, Third active layer; 140, Fourth transistor; 1415, Fifth gate; 1416, Sixth gate; 144, Fourth active layer; 150, Substrate; 161, First insulating layer; 162, Second insulating layer; 163, Third insulating layer; 164, Fourth insulating layer; 171, First conductive layer; 1711, First conductive portion; 172, Second conductive layer; 1722, Second conductive portion; 173, Third conductive layer; 1731, First electrode; 181, First conductor region; 182, Second conductor region; 183, Channel region; K1, First via; K2, Second via; S, First electrode; D, Second electrode. Detailed Implementation

[0065] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings. Preferred embodiments of this application are shown in the drawings. However, this application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a thorough and complete understanding of the disclosure of this application.

[0066] It should be understood that although the terms “first,” “second,” etc., may be used herein to describe various elements, this does not indicate any order, quantity, or importance, but is merely used to distinguish different components. These terms are used only to distinguish one element from another. For example, without departing from the scope of this application, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element. Words such as “comprising” or “including” mean that the element or object preceding the word covers the element or object listed after the word and its equivalents, without excluding other elements or objects.

[0067] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the specification of this application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0068] In the process of developing this application, the inventors discovered the following problems in the related technology: The display panel includes a shift register and a pixel circuit, with the shift register used to input a gate scan signal to the pixel circuit. The shift register includes a first transistor, and the pixel circuit includes a second transistor. Both the first and second transistors can be oxide thin-film transistors (Oxide-TFTs), meaning the active layers of the first and second transistors are oxide semiconductor materials. For example, the active layers of the first and second transistors can be high-mobility oxide semiconductor materials to achieve narrow bezels and high refresh rates in the display panel. Alternatively, the active layers of the first and second transistors can be low-mobility oxide semiconductor materials to improve transistor stability.

[0069] However, if both the first and second transistors use high-mobility oxide semiconductor materials, while the size of the first transistor can be reduced, which is beneficial for achieving narrow bezels and high refresh rates in the display panel, it will simultaneously reduce the stability and lifespan of the second transistor. Conversely, if both the first and second transistors use low-mobility oxide semiconductor materials, while the stability and lifespan of the second transistor can be improved, the size of the first transistor will be larger, making it impossible to achieve narrow bezels and high refresh rates in the display panel. Therefore, when both the first and second transistors use oxide semiconductor materials, how to achieve narrow bezels and high refresh rates while also meeting the requirements for long lifespan and stability of the display panel becomes a pressing problem to be solved.

[0070] In view of at least one of the above problems, embodiments of this application provide an array substrate and a method for fabricating the same, which can improve the performance of the array substrate and the display panel.

[0071] The array substrate and its fabrication method provided in the embodiments of this application will be described below with reference to Figures 1-16.

[0072] Referring to Figure 1, this application embodiment provides an array substrate 100, which includes a display area 100a and a border area 100b disposed adjacently. Exemplarily, the border area 100b is located on the outer periphery of the display area 100a. The display area 100a can be used to display an image. The border area 100b can be located on at least one side of the display area 100a. For example, the border area 100b can surround the outer periphery of the display area 100a, and the border area 100b can form a "black border" surrounding the outer periphery of the display area 100a.

[0073] Referring to Figure 2, the array substrate 100 includes a substrate 150, which provides support for subsequent layers of film. In some examples, the substrate 150 may be a rigid substrate, for example, the material of the substrate 150 may be glass. In other examples, the substrate 150 may be a flexible substrate, and the material of the substrate 150 may include at least one selected from polyimide (PI), polyethylene terephthalate, polyethylene naphthalate, polyethylene, polyacrylate, polyetherimide, polycarbonate, polyarylate, and polyethersulfone.

[0074] Referring to Figures 1 and 2, the array substrate 100 includes a shift register 101 and a pixel circuit 102. The shift register 101 is disposed on one side of the substrate 150 and is located in the border area 100b. The shift register 101 includes a first transistor 110, which includes a first active layer 111. The pixel circuit 102 is disposed on one side of the substrate 150 and is located in the display area 100a. The pixel circuit 102 includes a second transistor 120, which includes a second active layer 122. The shift register 101 is used to input a gate scan signal to the pixel circuit 102. The carrier mobility of at least a portion of the first active layer 111 is greater than that of the second active layer 122. Thus, the first active layer 111 is at least partially made of a material with higher carrier mobility (i.e., a high-mobility material), which makes the carrier migration path smoother (e.g., it can achieve nearly double the mobility improvement), enabling fast response to drive signals, improving signal transmission speed to achieve a high refresh rate, and reducing the device size of the first transistor 110, thereby reducing the size of the shift register 101 and achieving a narrow bezel. In addition, the second active layer 122 is made of a material with lower carrier mobility (i.e., a low-mobility material), which makes the second active layer 122 more stable, reduces the impact of environmental and electrical stress on the second transistor 120, and makes the threshold voltage drift of the second transistor 120 smaller, resulting in better reliability of the display panel and improving the lifespan of the second transistor 120 and the display panel.

[0075] In this case, at least some of the transistors in the pixel circuit 102 have higher stability requirements than the transistors in the shift register 101, and the stability of some of the transistors in the pixel circuit 102 is more likely to affect the screen life than the stability of the transistors in the shift register 101.

[0076] Referring to Figure 1, in some embodiments, the first transistor 110 includes a first gate 1141 and a second gate 1142. The first gate 1141 and the second gate 1142 are respectively located on both sides of the first active layer 111 along the thickness direction of the substrate 150. That is, the first transistor 110 adopts a top-bottom dual-gate structure. The top-bottom dual-gate structure can enhance electric field control, make full use of the high mobility of the first active layer 111, reduce threshold voltage drift, and help compensate for the instability of high mobility materials.

[0077] In some embodiments, the first active layer 111 is at least partially made of polycrystalline oxide semiconductor, and the second active layer 122 is made of amorphous oxide semiconductor. The carrier mobility of the polycrystalline oxide semiconductor is greater than that of the amorphous oxide semiconductor. Thus, on the one hand, among the same high mobility materials, the stability of the polycrystalline material is better than that of the amorphous material. In addition, polycrystalline oxide semiconductors are easier to achieve high mobility characteristics, which is beneficial for achieving narrow bezels and high refresh rates. On the other hand, amorphous oxide semiconductors are easier to achieve low mobility characteristics, which is beneficial for improving the stability of the second transistor 120 and the lifespan of the display panel. Furthermore, by utilizing the difference in etching selectivity between polycrystalline oxide semiconductors and amorphous oxide semiconductors, precise patterning of both on the same layer can be achieved without complex stacking processes, thereby simplifying the manufacturing process.

[0078] In some embodiments, the first active layer 111 and the second active layer 122 are disposed on the same layer. This co-location eliminates the need for the first active layer 111 and the second active layer 122 to interconnect by holes, avoiding the hole structure from occupying the area of ​​the display panel and facilitating the achievement of high pixel density (high PPI) requirements.

[0079] For example, polycrystalline oxide semiconductors include at least one of indium oxide (InO), indium gallium oxide (IGO), and indium tin gallium oxide (ITGO).

[0080] For example, amorphous oxide semiconductors include at least one of indium gallium zinc oxide (IGZO), indium zinc oxide (IZO), and zinc tin oxide (ZTO).

[0081] In some embodiments, the second transistor 120 is configured as either a driving transistor (DTFT) or a switching transistor (STFT). For example, the second transistor 120 is configured as a driving transistor (DTFT), and the active layer of the driving transistor (DTFT) may be made of a low-mobility amorphous oxide semiconductor. As another example, referring to FIG2, the second transistor 120 is configured as a switching transistor (STFT), and the active layer of the switching transistor (STFT) may be made of a low-mobility amorphous oxide semiconductor. This application will describe an embodiment where the second transistor 120 is configured as a switching transistor (STFT).

[0082] Referring to Figure 2, in some embodiments, the pixel circuit 102 includes a third transistor 130, the second transistor 120 is configured as a switching transistor STFT, and the third transistor 130 is configured as a driving transistor DTFT. The driving transistor DTFT includes a third active layer 133. The carrier mobility of the second active layer 122 is equal to the carrier mobility of the third active layer 133. Thus, both the second active layer 122 and the third active layer 133 use low mobility materials, which can better improve the lifespan of the pixel circuit 102 and the display panel. In addition, the second active layer 122 and the third active layer 133 can be fabricated in the same layer with the same material to fabricate the second active layer 122 and the third active layer 133 at the same time, thereby simplifying the fabrication process and reducing the fabrication cost.

[0083] In this application's embodiments, "same layer, same material" refers to a base film layer formed from the same material. After patterning and / or other processing of the base film layer, different parts of the base film layer are formed into various structural film layers. The processing techniques for the different structural film layers can be the same or different, and the different structural film layers can have the same or different thicknesses, and can also be on the same horizontal plane or different horizontal planes.

[0084] In embodiments where the third active layer 133 employs a low-mobility material, the material of the third active layer 133 includes amorphous oxide semiconductors. Amorphous oxide semiconductors are easier to achieve low-mobility characteristics, which is beneficial for improving the lifespan of the third transistor 130 and the display panel.

[0085] Referring to Figure 3, in some embodiments, the carrier mobility of the second active layer 122 is lower than that of the third active layer 133. The third active layer 133 is made of a high-mobility material, while the second active layer 122 is made of a low-mobility material. This results in higher stability of the switching transistor STFT, which is beneficial to improving the lifespan of the switching transistor STFT and the display panel. In addition, the active layer of the driving transistor DTFT is made of a high-mobility material, which makes the carrier transport speed of the driving transistor DTFT faster. The high mobility allows the driving transistor DTFT to output a larger driving current under the same gate voltage, or to shorten the conduction time under the same current demand. This allows the light-emitting device to obtain more sufficient energy supply, thereby improving the brightness of the light-emitting device and improving the brightness of the display panel.

[0086] In an embodiment where the third active layer 133 uses a high mobility material, the material of the third active layer 133 includes a polycrystalline oxide semiconductor. Polycrystalline oxide semiconductors are easier to achieve high mobility characteristics, which is beneficial to improving the brightness of the light-emitting device, thereby improving the brightness of the display panel.

[0087] It should be noted that in the pixel circuit 102, which may include multiple transistors, the stability, reliability, and lifespan of the pixel circuit 102 can be improved to some extent if the active layer of even one transistor uses a low-mobility material, without all transistors needing to use low-mobility materials. Similarly, in the shift register 101, which includes multiple transistors, the bezel width and refresh rate issues can be improved to some extent if the active layer of even one transistor uses a high-mobility material, without all transistors needing to use low-mobility materials. This application can balance various performance parameters of the display panel according to actual needs.

[0088] Referring to Figure 3, in some embodiments, the first active layer 111 and the third active layer 133 are arranged on the same layer. In this way, the first active layer 111 and the third active layer 133 do not need to be interconnected by holes, avoiding the hole structure from occupying the area of ​​the display panel, which is conducive to achieving the requirement of high pixel density (high PPI).

[0089] Referring to Figure 10, in some embodiments, the driving transistor DTFT is a single-gate transistor. The driving transistor DTFT includes a third gate 1313, which is located between the third active layer 133 and the substrate 150. Thus, the driving transistor DTFT adopts a bottom gate structure.

[0090] Referring to Figures 8 and 9, in some embodiments, the switching transistor STFT is a single-gate transistor. The switching transistor STFT includes a fourth gate 1234, which is located on the side of the second active layer 122 of the switching transistor STFT away from the substrate 150. Thus, the switching transistor STFT adopts a top-gate structure.

[0091] Referring to Figure 2, in some embodiments, the driving transistor DTFT includes a first gate dielectric layer 1311 located between the third active layer 133 and the third gate 1313. The switching transistor STFT includes a second gate dielectric layer 1232 located between the second active layer 122 and the fourth gate 1234 of the switching transistor STFT. The thickness of the first gate dielectric layer 1311 is greater than the thickness of the second gate dielectric layer 1232. Thus, by setting the thickness of the first gate dielectric layer 1311 to be larger, the driving transistor DT using a bottom gate structure is made more efficient. The larger FT subthreshold swing (SS) allows the driving current of the DTFT to change more smoothly with the gate voltage, enabling precise control of the luminous brightness corresponding to different gray levels, avoiding gray level breaks, improving display detail, and facilitating gray level expansion of the display panel. In addition, by setting the thickness of the second gate dielectric layer 1232 to be smaller, the thinner second gate dielectric layer 1232 allows the top-gate structure of the STFT to enhance the electric field control of the channel region by the fourth gate 1234, reducing the subthreshold swing (SS) and allowing the STFT to turn on or off quickly to ensure fast data writing.

[0092] For example, the thickness of the first gate dielectric layer 1311 is in the range of 3000 angstroms to 5000 angstroms. This makes the thickness of the first gate dielectric layer 1311 relatively large, so that the driving transistor DTFT of the bottom gate structure can obtain a larger subthreshold swing (SS), which is beneficial to the grayscale expansion of the display panel. At the same time, it can avoid the first gate dielectric layer 1311 being too thick, so as to avoid weakening the electric field control capability of the third gate 1313 in the channel region and causing carrier response delay.

[0093] For example, the thickness of the first gate dielectric layer 1311 can be 3000 angstroms, 3500 angstroms, 4000 angstroms, 4500 angstroms, 5000 angstroms or any value between 3000 angstroms and 5000 angstroms.

[0094] For example, the thickness of the second gate dielectric layer 1232 is in the range of 900 angstroms to 1500 angstroms. This makes the second gate dielectric layer 1232 thinner, which allows the switching transistor STFT to be turned on or off quickly, ensuring fast data writing. At the same time, it can avoid the second gate dielectric layer 1232 being too thin, thereby avoiding the increase in leakage current caused by an excessively thin second gate dielectric layer 1232.

[0095] For example, the thickness of the second gate dielectric layer 1232 can be 900 angstroms, 1000 angstroms, 1100 angstroms, 1300 angstroms, 1500 angstroms or any value between 900 angstroms and 1500 angstroms.

[0096] Referring to Figure 4, in some embodiments, the first active layer 111 includes a first sub-active layer 1111 and a second sub-active layer 1112 stacked along the direction away from the substrate 150. The carrier mobility of the first sub-active layer 1111 is greater than that of the second sub-active layer 1112. Thus, by using a high-mobility material in the first sub-active layer 1111, it is beneficial to achieve a narrow bezel and a high refresh rate. In addition, by disposing of the second sub-active layer 1112 on the side of the first sub-active layer 1111 away from the substrate 150 and using a low-mobility material, the second sub-active layer 1112 can protect the first sub-active layer 1111, preventing the elements of the second insulating layer 162 from diffusing into the first sub-active layer 1111. Furthermore, the second sub-active layer 1112 can block ambient light from illuminating the first sub-active layer 1111, thereby enhancing the resistance of the first transistor 110 to ambient light and improving the stability of the first transistor 110.

[0097] For example, the material of the first sub-active layer 1111 includes a polycrystalline oxide semiconductor, and the material of the second sub-active layer 1112 includes an amorphous oxide semiconductor. In this way, the polycrystalline oxide semiconductor can more easily achieve high mobility characteristics, which is beneficial for achieving narrow bezels and high refresh rates. In addition, the amorphous oxide semiconductor can more easily achieve low mobility characteristics, which is beneficial for enhancing the resistance of the first transistor 110 to external light and improving the stability of the first transistor 110.

[0098] Referring to Figure 5, in some embodiments, the first active layer 111 includes a third sub-active layer 1113. The third sub-active layer 1113 is located on the side of the first sub-active layer 1111 facing the substrate 150. The carrier mobility of the first sub-active layer 1111 is greater than that of the third sub-active layer 1113. Thus, by disposing of the third sub-active layer 1113 on the side of the first sub-active layer 1111 facing the substrate 150 and using a low-mobility material, the third sub-active layer 1113 can protect the first sub-active layer 1111 and prevent the elements of the first insulating layer 161 from diffusing into the first sub-active layer 1111.

[0099] For example, the material of the third sub-active layer 1113 includes amorphous oxide semiconductor, which is easier to achieve low mobility characteristics, thus improving the stability of the first transistor 110.

[0100] Referring to Figure 3, in some embodiments, the first active layer 111 includes only a single layer of high mobility material (e.g., polycrystalline oxide semiconductor) and does not include low mobility material (e.g., amorphous oxide semiconductor), which can make the electrical performance of the first transistor 110 better.

[0101] Referring to Figure 6, in some embodiments, the shift register 101 includes a fourth transistor 140, which includes a fourth active layer 144. The carrier mobility of at least a portion of the first active layer 111 is greater than that of the fourth active layer 144. Thus, the fourth active layer 144 is fabricated using a low-mobility material, resulting in higher stability and reducing the impact of electrical stress on the fourth transistor 140. This allows the fourth transistor 140 to be suitable for scenarios with a large voltage difference between its first electrode (S) and its gate (fifth gate 1415 and / or sixth gate 1416), thereby improving the stability of the shift register 101. In this case, when the shift register 101 is in operation, the voltage difference between the first electrode (S) and the gate of the fourth transistor 140 is greater than the voltage difference between the first electrode (S) and the gate of the first transistor 110.

[0102] For example, when the voltage difference between the first terminal S of the fourth transistor 140 and the gate of the fourth transistor 140 is large, the first terminal S of the fourth transistor 140 may be connected to a first power supply signal (VGL) and the gate may be connected to a clock signal (CLK); or, the first terminal S of the fourth transistor 140 may be connected to a clock signal (CLK) and the gate may be connected to a second power supply signal (VGH).

[0103] In this embodiment, the array substrate 100 includes a plurality of transistors, including at least one of a first transistor 110, a second transistor 120, a third transistor 130, and a fourth transistor 140. For example, the plurality of transistors includes the first transistor 110, the second transistor 120, the third transistor 130, and the fourth transistor 140. Referring to Figures 6 and 16, in the same transistor, the transistor includes a first electrode S and a second electrode D, one of which is the source and the other is the drain. The active layer of the transistor includes a channel region 183, a first conductive region 181, and a second conductive region 182. The first conductive region 181 and the second conductive region 182 are located on opposite sides of the channel region 183. The first electrode S and the first conductive region 181 are in contact, and the second electrode D and the second conductive region 182 are in contact.

[0104] For example, the material of the fourth active layer 144 includes amorphous oxide semiconductor. Thus, amorphous oxide semiconductor is more likely to achieve low mobility characteristics, making the fourth transistor 140 suitable for scenarios with a large voltage difference between the first electrode S and the gate, thereby improving the stability of the fourth transistor 140 under high voltage differences.

[0105] For example, in an embodiment where the fourth active layer 144 uses a low mobility material, when the shift register is in operation, the voltage difference between the first terminal S of the fourth transistor 140 and the gate of the fourth transistor 140 is greater than or equal to 12V, that is, the fourth transistor 140 can be used in scenarios where the voltage difference is greater than 12V.

[0106] In some embodiments, the first active layer 111 and the fourth active layer 144 are arranged on the same layer. This arrangement eliminates the need for the first active layer 111 and the fourth active layer 144 to be interconnected by holes, thus avoiding the hole structure from occupying the area of ​​the display panel and facilitating the achievement of high pixel density (high PPI) requirements.

[0107] In some embodiments, the first active layer 111, the second active layer 122, the third active layer 133, and the fourth active layer 144 are all disposed on the same layer. This disposal on the same layer means that the active layers of any two transistors do not need to be interconnected by holes, thus avoiding the hole structure from occupying the area of ​​the display panel and making it easier to achieve the requirements of high pixel density (high PPI).

[0108] Referring to Figure 6, in some embodiments, the fourth transistor 140 may include a fifth gate 1415 and a sixth gate 1416, which are located on opposite sides of the fourth active layer 144 along the thickness direction of the substrate 150. The fourth transistor 140 may be a top-bottom dual-gate transistor. The fifth gate 1415 and the sixth gate 1416 may be electrically connected.

[0109] Referring to Figure 6, in the embodiment where the fourth active layer 144 is prepared using a low-mobility material, the first active layer 111 can be made of a single layer of high-mobility material.

[0110] Referring to Figures 4, 5 and 7, in another embodiment where the fourth active layer 144 is prepared using a low-mobility material, the first active layer 111 can be prepared by stacking high-mobility and low-mobility materials.

[0111] It should be noted that in any one of the first transistor 110, the second transistor 120, the third transistor 130, and the fourth transistor 140, the transistor can adopt a top-gate structure, a bottom-gate structure, or a top-bottom dual-gate structure. That is, the first transistor 110 can adopt a top-gate structure, a bottom-gate structure, or a top-bottom dual-gate structure. The second transistor 120 can adopt a top-gate structure, a bottom-gate structure, or a top-bottom dual-gate structure. The third transistor 130 can adopt a top-gate structure, a bottom-gate structure, or a top-bottom dual-gate structure. The fourth transistor 140 can adopt a top-gate structure, a bottom-gate structure, or a top-bottom dual-gate structure. In the top-bottom dual-gate structure, the top gate and the bottom gate can be electrically connected.

[0112] Referring to Figure 6, in some embodiments, the array substrate 100 may include a first conductive layer 171, and the bottom gate of the transistor may be located on the first conductive layer 171. For example, the first gate 1141, the third gate 1313, and the fifth gate 1415 are located on the first conductive layer 171. Exemplarily, the first conductive layer 171 may also include a first conductive portion 1711, which is located between the active layer of the switching transistor STFT and the substrate 150. When the switching transistor STFT is a top-gate structure, the first conductive portion 1711 may be electrically connected to the first terminal S of the switching transistor STFT. When the switching transistor STFT is a top-bottom dual-gate structure, the first conductive portion 1711 may be electrically connected to the fourth gate 1234.

[0113] Referring to Figure 6, in some embodiments, the array substrate 100 may include a second conductive layer 172, and the top gate of the transistor may be located on the second conductive layer 172. For example, the second gate 1142, the fourth gate 1234, and the sixth gate 1416 may be located on the second conductive layer 172. Exemplarily, the second conductive layer 172 may include a second conductive portion 1722, which is located on the side of the active layer of the driving transistor DTFT that faces away from the substrate. When the driving transistor DTFT is a bottom-gate structure, the second conductive portion 1722 may be electrically connected to the first terminal S of the driving transistor DTFT. When the driving transistor DTFT is a top-bottom dual-gate structure, the second conductive portion 1722 may be electrically connected to the third gate 1313.

[0114] Referring to FIG6, in some embodiments, the array substrate 100 may include a first insulating layer 161 located between the first conductive layer 171 and the active layer of the transistor. In the same transistor, when the transistor includes a bottom gate, the first insulating layer 161 located between the active layer and the bottom gate is configured as a bottom gate dielectric layer.

[0115] Referring to FIG6, in some embodiments, the array substrate 100 may include a second insulating layer 162 located between the second conductive layer 172 and the active layer of the transistor. In the same transistor, when the transistor includes a top gate, the second insulating layer 162 located between the active layer and the top gate is configured as a top gate dielectric layer.

[0116] Referring to FIG6, in some embodiments, the array substrate 100 may include a third insulating layer 163, which is located on the side of the second conductive layer 172 away from the substrate 150. In the same transistor, the first electrode S of the transistor is located on the side of the third insulating layer 163 away from the substrate 150, and the first electrode S contacts the first conductive region 181 (FIG. 15) through a first via K1 penetrating the second insulating layer 162 and the third insulating layer 163. The second electrode D of the transistor is located on the side of the third insulating layer 163 away from the substrate 150, and the second electrode D contacts the second conductive region 182 (FIG. 15) through a second via K2 penetrating the second insulating layer 162 and the third insulating layer 163.

[0117] Referring to Figure 6, in some embodiments, the array substrate 100 may include a fourth insulating layer 164, which is located on the side of the first electrode S and the second electrode D opposite to the substrate 150. The fourth insulating layer 164 may be a planarization layer.

[0118] Referring to Figure 6, in some embodiments, the array substrate 100 may include a third conductive layer 173. The third conductive layer 173 is located in the border region 100b and the display region 100a. The third conductive layer 173 in the border region 100b has a light-shielding function, which can reduce the adverse effects of external light on the oxide semiconductor. The third conductive layer 173 in the border region 100b may be provided with holes to prevent the gas generated in the planarization layer during the high-temperature process from failing to release and causing the third conductive layer 173 in the border region 100b to bulge.

[0119] For example, the third conductive layer 173 located in the display area 100a may include a plurality of first electrodes 1731.

[0120] The following describes the fabrication method of the array substrate 100 provided in the embodiments of this application.

[0121] This application provides a method for fabricating an array substrate 100, used to fabricate the array substrate 100 described in the above embodiments. The array substrate 100 includes a display area 100a and a border area 100b disposed adjacently. Referring to FIG11, the fabrication method includes:

[0122] Step S100: Provide a substrate.

[0123] Referring to Figure 12, a substrate 150 is provided.

[0124] Step S200: A shift register and a pixel circuit are formed on one side of the substrate; the shift register is located in the border area and includes a first transistor, the first transistor including a first active layer; the pixel circuit is located in the display area and includes a second transistor, the second transistor including a second active layer; wherein, at least a portion of the carrier mobility of the first active layer is greater than the carrier mobility of the second active layer, and the material of the first active layer includes a polycrystalline oxide semiconductor.

[0125] Referring to Figure 2, a shift register 101 and a pixel circuit 102 are formed on one side of the substrate 150. The shift register 101 is located in the border area 100b and includes a first transistor 110, which includes a first active layer 111. The pixel circuit 102 is located in the display area 100a and includes a second transistor 120, which includes a second active layer 122. The carrier mobility of at least a portion of the first active layer 111 is greater than that of the second active layer 122. Thus, the first active layer 111 is at least partially made of a material with higher carrier mobility (i.e., a high-mobility material). This ensures a smooth carrier migration path (e.g., achieving nearly double the mobility improvement), enabling rapid response to drive signals, increasing signal transmission speed for high refresh rates, and reducing the device size of the first transistor 110, thereby reducing the size of the shift register 101 and achieving a narrow bezel. In addition, the second active layer 122 uses a material with low carrier mobility (i.e., low mobility material), making the second active layer 122 more stable and reducing the impact of environmental and electrical stress on the second transistor 120. The threshold voltage drift of the second transistor 120 is small, resulting in better reliability of the display panel and improving the lifespan of the second transistor 120 and the display panel. The first transistor 110 includes a first gate 1141 and a second gate 1142. The first gate 1141 and the second gate 1142 are located on both sides of the first active layer 111 along the thickness direction of the substrate 150, respectively. That is, the first transistor 110 adopts a top-bottom dual-gate structure. The top-bottom dual-gate structure can enhance electric field control, make full use of the high mobility of the first active layer 111, reduce threshold voltage drift, and help compensate for the instability of high mobility materials. The first active layer 111 and the second active layer 122 are arranged in the same layer. In this way, the first active layer 111 and the second active layer 122 do not need to be interconnected by holes, avoiding the area occupied by hole structures on the display panel, which is conducive to achieving the requirements of high pixel density (high PPI).

[0126] The shift register 101 and pixel circuit 102 are formed on one side of the substrate 150 in a detailed manner.

[0127] Referring to FIG12, after providing the substrate 150, a first conductive layer 171 may be formed on one side of the substrate 150, and then the first conductive layer 171 may be patterned, wherein the remaining first conductive layer 171 forms at least one of a first gate 1141, a third gate 1313, a fifth gate 1415 (FIG. 5), and a first conductive portion 1711.

[0128] Referring to Figure 12, after patterning the first conductive layer 171, a first insulating layer 161 may be formed.

[0129] Referring to FIG. 12, after forming the first insulating layer 161, a first active material layer 111e of amorphous material may be formed on one side of the substrate 150. The first active material layer 111e is located in the border region 100b and the display region 100a. Then, the first active material layer 111e is subjected to a first patterning and annealing process; the retained first active material layer 111e is at least configured as at least a portion of the first active layer 111, and the annealing process transforms the first active material layer 111e from an amorphous material into a polycrystalline material. Referring to FIG. 13, a second active material layer 122e of amorphous material is then formed on one side of the substrate 150. The second active material layer 122e is located in the border region 100b and the display region 100a. Then, the second active material layer 122e is subjected to a second patterning process; the retained second active material layer 122e is at least configured as the second active layer 122. The etching reagent for the second patterning process is the first etching reagent. Thus, through annealing, the first active material layer 111e is transformed from an amorphous material into a polycrystalline material. This improves the resistance of the crystallized first active material layer 111e to corrosion by the first etching reagent. When performing the second patterning process on the second active material layer 122e, since the second active material layer 122e is amorphous, the first etching reagent can etch it relatively quickly. However, the etching rate of the first etching reagent on the crystallized first active material layer 111e is slower or almost negligible, allowing for selective etching of the second active material layer 122e and reducing damage to the first active material layer 111e during the second patterning process. While conventional acidic etching solutions can etch the second active material layer 122e, the polycrystalline first active material layer 111e can resist this acidic etching solution, a property that amorphous high-mobility materials cannot achieve. That is, in the first etching reagent, the etching rate of the second active material layer 122e is greater than the etching rate of the first active material layer 111e after annealing.

[0130] For example, in the first etching reagent, the ratio of the etching rate of the second active material layer 122e to the etching rate of the annealed first active material layer 111e is greater than or equal to 10. This allows the first etching reagent to etch the second active material layer 122e relatively quickly, while the etching of the annealed first active material layer 111e is very slow (or almost not etched), thus giving a greater choice in the etching of the second active material layer 122e and the annealed first active material layer 111e.

[0131] For example, the first etching agent may include at least one of oxalic acid and acetic acid.

[0132] For example, the annealing temperature range is 300℃-500℃, which can avoid the annealing temperature being too low and ensure that the first active material layer 111e crystallizes after annealing. In addition, it can also avoid the annealing temperature being too high, thereby reducing the adverse effects of high temperature on the array substrate 100.

[0133] For example, the annealing temperature can be 300℃, 350℃, 400℃, 450℃, 500℃, or any value between 300℃ and 500℃.

[0134] For example, performing a first patterning and annealing treatment on the first active material layer 111e may include first patterning the first active material layer 111e with a first etching reagent, and then annealing the first active material layer 111e. Alternatively, performing a first patterning and annealing treatment on the first active material layer 111e may include first annealing the first active material layer 111e, and then using a second etching reagent to perform a first patterning treatment on the first active material layer 111e. For example, the second etching reagent may include aqua regia solution, which has strong corrosiveness and can etch the crystallized first active material layer 111e.

[0135] For example, the thickness of the first active material layer 111e ranges from 20 angstroms to 300 angstroms.

[0136] In embodiments where at least a portion of the active layer (i.e., the third active layer) of the third transistor 130 and the active layer (i.e., the first active layer) of the first transistor 110 are made of high-mobility materials, the retained first active material layer 111e may also form the active layer of the third transistor 130.

[0137] In embodiments where both the active layer of the third transistor 130 and the active layer of the second transistor 120 are made of low-mobility materials, the retained second active material layer 122e can also form the active layer of the third transistor 130.

[0138] In embodiments where both the active layer of the fourth transistor 140 and the active layer of the second transistor 120 are made of low-mobility materials, the retained second active material layer 122e can also form the active layer of the fourth transistor 140.

[0139] In embodiments where the first active layer 111 includes a first sub-active layer 1111 and a second sub-active layer 1112, the reserved first active material layer 111e can be used to form the first sub-active layer 1111, and the reserved second active material layer 122e can be used to form the second sub-active layer 1112.

[0140] In embodiments where the first active layer 111 includes a first sub-active layer 1111, a second sub-active layer 1112, and a third sub-active layer 1113, before forming the first active material layer 111e of amorphous material, the third active material layer of amorphous material may be formed. During the first patterning process of the first active material layer 111e, the third active material layer may also be patterned, and the retained third active material layer forms the third sub-active layer 1113.

[0141] Referring to FIG14, after performing a second patterning process on the second active material layer 122e, a second insulating layer 162 may be formed on the side of the first active layer 111 and the second active layer 122 that is away from the substrate 150.

[0142] Referring to FIG14, after forming the second insulating layer 162, a second conductive layer 172 may be formed on the side of the second insulating layer 162 opposite to the substrate 150. Then, the second conductive layer 172 is patterned, and the remaining second conductive layer 172 is used to form at least one of the second gate 1142, the fourth gate 1234, the sixth gate 1416, and the second conductive portion 1722.

[0143] Referring to Figures 14 and 15, after patterning the second conductive layer 172, ion implantation may be performed on the first and second sub-regions on both sides of the channel region 183 of the first active layer 111, the second active layer 122, the third active layer 133, and the fourth active layer 144 (Figure 5), using the retained second conductive layer 172 as a mask. This process involves doping the first sub-region to form a first conductive region 181 and doping the second sub-region to form a second conductive region 182. In the same transistor, both the first and second sub-regions on both sides of the channel region 183 of the active layer are conductiveized by ion implantation. The second gate 1142 and the channel region 183 of the first active layer 111 may at least partially overlap along the thickness direction of the substrate 150. The second conductive portion 1722 and the channel region 183 of the third active layer 133 may at least partially overlap along the thickness direction of the substrate 150. The fourth gate 1234 and the channel region 183 of the second active layer 122 may at least partially overlap along the thickness direction of the substrate 150. Referring to Figure 6, the sixth gate 1416 and the channel region 183 of the fourth active layer 144 may at least partially overlap along the thickness direction of the substrate 150. Since all transistors are doped using the same ion implantation, the uniformity of each transistor can be improved.

[0144] Referring to FIG16, after ion implantation, a third insulating layer 163 may be formed on the side of the second conductive layer 172 facing away from the substrate 150. Then, a first via K1 and a second via K2 are formed in the second insulating layer 162 and the third insulating layer 163. Then, a first electrode S and a second electrode D are formed on the side of the third insulating layer 163 facing away from the substrate 150. The first electrode S contacts the first conductive region 181 through the first via K1, and the second electrode D contacts the second conductive region 182 through the second via K2. Then, referring to FIG2, a fourth insulating layer 164 is formed on the side of the first electrode S and the second electrode D facing away from the substrate 150. Then, the third conductive layer 173 is formed on the side of the fourth insulating layer 164 facing away from the substrate 150.

[0145] The following describes the display panel provided in the embodiments of this application.

[0146] This application provides a display panel, which includes the array substrate 100 of the above embodiments, or the array substrate 100 obtained by the preparation method of the array substrate 100 of the above embodiments.

[0147] In some embodiments, the display panel may include an array substrate 100, a light-emitting functional part, and a second electrode. The light-emitting functional part is located on the array substrate 100, and the second electrode is located on the side of the light-emitting functional part facing away from the substrate 150. A first electrode 1731, the light-emitting functional part, and the second electrode are collectively constructed as a light-emitting device, meaning the light-emitting device may include a first electrode 1731, the light-emitting functional part, and the second electrode sequentially stacked along a direction away from the substrate 150. The first electrode 1731 may be located on the side of the light-emitting functional part facing the substrate 150. Pixel circuitry 102 is used to drive the light-emitting device to emit light.

[0148] In some embodiments, one of the first electrode 1731 and the second electrode can be an anode, and the other can be a cathode. This application embodiment uses the example of the first electrode 1731 being the anode and the second electrode being the cathode. The first electrode 1731 can be electrically connected to the pixel circuit 102; for example, the first electrode 1731 can be electrically connected to the first electrode S of the driving transistor DTFT.

[0149] In some embodiments, the light-emitting functional unit includes a hole injection layer HIL, a hole transport layer HTL, an electron blocking layer EBL, a light-emitting material layer EML, a hole blocking layer HBL, an electron transport layer ETL, and an electron injection layer EIL stacked along a direction away from the array substrate 100. The light-emitting functional unit may include a single light-emitting material layer EML, or a stacked light-emitting structure including multiple light-emitting material layers EML.

[0150] In some embodiments, there may be multiple light-emitting devices, which may be arranged in an array. The multiple light-emitting devices may include a first light-emitting device, a second light-emitting device, and a third light-emitting device that emit different colors. The multiple light-emitting devices include, but are not limited to, red, green, and blue light-emitting devices. In other examples, the multiple light-emitting devices may also include white light-emitting devices.

[0151] The following describes the display device provided in the embodiments of this application.

[0152] This application provides a display device, which may include a display panel. The display device can be an electronic paper device, mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, smart bracelet, smartwatch, supercomputer, navigator, wireless device, personal digital assistant (PDA), handheld or portable computer, GPS receiver / navigator, camera, MP4 video player, camcorder, game console, clock, calculator, television monitor, computer monitor, automotive display (e.g., odometer display), cockpit controller and / or display, camera view display (e.g., display of a rearview camera in a vehicle), electronic billboard or sign, projector, and other mobile or fixed terminals.

[0153] For example, the display panel can be an Organic Light-Emitting Diode (OLED) display panel, a Micro Organic Light-Emitting Diode (Micro OLED) display panel, a Light Emitting Diode (LED) display panel, a Quantum Dot Light Emitting Diode (QLED) display panel, a Mini Light Emitting Diode (MiniLED) display panel, a Micro Light Emitting Diode (Micro LED) display panel, or a Liquid Crystal Display (LCD) display panel, etc. This application uses an OLED display panel as an example for illustration.

[0154] When using the terms “including,” “having,” and “comprising” as described herein, another component may be added unless explicitly qualifying terms such as “only,” “consisting of,” etc. are used. Unless otherwise stated, singular terms may include plural forms and should not be construed as having a quantity of one.

[0155] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0156] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. An array substrate, characterized in that, The array substrate includes an adjacent display area and a border area. The array substrate includes: a substrate; a shift register disposed on one side of the substrate and located in the border area; the shift register includes a first transistor, the first transistor including a first active layer; a pixel circuit disposed on one side of the substrate and located in the display area; the pixel circuit includes a second transistor, the second transistor including a second active layer; wherein, at least a portion of the carrier mobility of the first active layer is greater than the carrier mobility of the second active layer, and the material of the first active layer includes a polycrystalline oxide semiconductor.

2. The array substrate according to claim 1, characterized in that, The polycrystalline oxide semiconductor includes at least one of indium oxide, indium gallium oxide, and indium tin gallium oxide.

3. The array substrate according to claim 1, characterized in that, The material of the second active layer includes an amorphous oxide semiconductor; the carrier mobility of the polycrystalline oxide semiconductor is greater than that of the amorphous oxide semiconductor, and the amorphous oxide semiconductor includes indium gallium zinc oxide.

4. The array substrate according to claim 1, characterized in that, The first transistor includes a first gate and a second gate, which are respectively located on both sides of the first active layer along the thickness direction of the substrate; preferably, the first active layer and the second active layer are disposed in the same layer.

5. The array substrate according to claim 1 or 2, characterized in that, The second transistor is configured as either a driving transistor or a switching transistor; preferably, the pixel circuit includes a third transistor, the second transistor being configured as a switching transistor and the third transistor being configured as a driving transistor, the driving transistor including a third active layer; the carrier mobility of the second active layer is less than or equal to the carrier mobility of the third active layer; preferably, the material of the third active layer includes amorphous oxide semiconductor or polycrystalline oxide semiconductor; preferably, the first active layer and the third active layer are disposed in the same layer.

6. The array substrate according to claim 5, characterized in that, The driving transistor is a single-gate transistor, and the driving transistor includes a third gate located between the third active layer and the substrate; preferably, the switching transistor is a single-gate transistor, and the switching transistor includes a fourth gate located on the side of the second active layer of the switching transistor away from the substrate.

7. The array substrate according to claim 6, characterized in that, The driving transistor includes a first gate dielectric layer located between the third active layer and the third gate; the switching transistor includes a second gate dielectric layer located between the second active layer and the fourth gate; the thickness of the first gate dielectric layer is greater than the thickness of the second gate dielectric layer; preferably, the thickness of the first gate dielectric layer is in the range of 3000 angstroms to 5000 angstroms; preferably, the thickness of the second gate dielectric layer is in the range of 900 angstroms to 1500 angstroms.

8. The array substrate according to claim 1 or 2, characterized in that, The first active layer includes a first sub-active layer and a second sub-active layer stacked along a direction away from the substrate, wherein the carrier mobility of the first sub-active layer is greater than that of the second sub-active layer; preferably, the material of the first sub-active layer includes a polycrystalline oxide semiconductor, and the material of the second sub-active layer includes an amorphous oxide semiconductor; preferably, the first active layer includes a third sub-active layer, wherein the third sub-active layer is located on the side of the first sub-active layer facing the substrate, and the carrier mobility of the first sub-active layer is greater than that of the third sub-active layer; preferably, the material of the third sub-active layer includes an amorphous oxide semiconductor.

9. The array substrate according to claim 1 or 2, characterized in that, The shift register includes a fourth transistor, the fourth transistor includes a fourth active layer, and the carrier mobility of at least a portion of the first active layer is greater than the carrier mobility of the fourth active layer; preferably, when the shift register is in operation, the voltage difference between the first electrode and the gate of the fourth transistor is greater than the voltage difference between the first electrode and the gate of the first transistor; preferably, the material of the fourth active layer includes amorphous oxide semiconductor; preferably, the first active layer and the fourth active layer are disposed in the same layer.

10. A method for fabricating an array substrate, characterized in that, The array substrate includes an adjacent display area and a border area. The fabrication method includes: providing a substrate; forming a shift register and a pixel circuit on one side of the substrate; the shift register is located in the border area and includes a first transistor, the first transistor including a first active layer; the pixel circuit is located in the display area and includes a second transistor, the second transistor including a second active layer; wherein, at least a portion of the carrier mobility of the first active layer is greater than the carrier mobility of the second active layer, and the material of the first active layer includes a polycrystalline oxide semiconductor.

11. The method for fabricating an array substrate according to claim 10, characterized in that, The method of forming a shift register and pixel circuit on one side of the substrate includes: forming a first active material layer of amorphous material on one side of the substrate, the first active material layer being located in the border area and the display area; performing a first patterning and annealing process on the first active material layer; retaining the first active material layer being at least a portion of the first active layer, the annealing process causing the first active material layer to be transformed from an amorphous material to a polycrystalline material; and forming a second active material layer of amorphous material on one side of the substrate, the second active material layer being located in the border area and the display area. The second active material layer is subjected to a second patterning process; the retained second active material layer is at least configured as a second active layer; the etching reagent for the second patterning process is a first etching reagent, wherein the etching rate of the second active material layer in the first etching reagent is greater than the etching rate of the first active material layer after annealing; preferably, the ratio of the etching rate of the second active material layer to the etching rate of the first active material layer after annealing in the first etching reagent is greater than or equal to 10; preferably, the annealing temperature range is 300℃-500℃.

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