Wafer-level radio frequency integrated circuit structure and preparation method thereof

Abstract

According to the wafer-level radio frequency integrated circuit structure and the preparation method thereof, the acoustic wave filter and other functional devices are integrated on the same wafer at the same time, miniaturization of a radio frequency front-end module is achieved, the area utilization rate of a chip is greatly increased, the requirement of a mobile terminal for the device size is met, and the manufacturing cost is reduced. Electrical connection among different devices is achieved through the metal interconnection lines in the chip, compared with a traditional packaging mode that a ceramic substrate and an organic substrate are used for electrical interconnection, the interconnection distance is greatly shortened, signal loss and delay caused by parasitic inductance, capacitance and resistance are effectively reduced, and the reliability of the chip is improved. Compared with a traditional substrate interconnection packaging technology, the manufacturing method of the radio frequency front-end module is simple and can be compatible with a standard technology such as a silicon-based CMOS technology, so that the area utilization rate of a chip is increased, and the production cost is reduced.

Description

Wafer-level radio frequency integrated circuit structure and its fabrication method Technical Field

[0001] This invention relates to the technical field of semiconductor chip packaging, and in particular to a wafer-level radio frequency integrated circuit structure and its fabrication method. Background Technology

[0002] With the commercial deployment of fifth-generation (5G) mobile communication technology and the evolution of future communication technologies, the number of frequency bands that mobile communication terminals need to support continues to increase, placing higher demands on the performance and integration of radio frequency (RF) front-end modules. To meet the needs of multi-frequency and multi-mode operation, the number of RF front-end modules integrated in a single terminal has increased significantly, making the development of RF front-end modules towards higher frequencies, greater integration, and miniaturization an inevitable trend.

[0003] Traditional RF front-end module integration solutions commonly employ lateral stacking and System-in-Package (SiP) technologies. This technology horizontally integrates chips with different functions, such as acoustic filters, power amplifiers, low-noise amplifiers, switches, and controllers, onto an organic or ceramic substrate via wire bonding or flip-chip bonding. However, this integration method requires each functional chip to be manufactured separately before assembly, resulting in a complex process, a large package area, and difficulty in meeting the miniaturization requirements of terminal devices. Furthermore, the interconnecting wires between chips introduce additional parasitic inductance and resistance, leading to increased signal loss and performance degradation in high-frequency operating environments, thus limiting the overall performance improvement of the module. With the continuous increase in functional requirements and the growing number of chips, reducing the chip area of ​​the front-end module becomes increasingly difficult, and traditional lateral stacking technology is gradually reaching its bottleneck.

[0004] Therefore, there is an urgent need for a new integrated structure and fabrication method that can integrate acoustic filters and other functional modules on the same wafer chip without sacrificing the performance of each device, thereby truly realizing the miniaturization, high performance and low cost manufacturing of RF front-end modules.

[0005] It should be noted that the above introduction to the technical background is only for the purpose of providing a clear and complete explanation of the technical solutions of this application and facilitating understanding by those skilled in the art. It should not be assumed that these technical solutions are known to those skilled in the art simply because they have been described in the background section of this application. Summary of the Invention

[0006] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a wafer-level radio frequency integrated circuit structure and its fabrication method, which solves the problems of complex process flow, large packaging area, increased loss and performance degradation in traditional radio frequency front-end module integration schemes.

[0007] To achieve the above and other related objectives, the present invention provides a method for fabricating a wafer-level radio frequency integrated circuit structure, comprising the following steps:

[0008] A first temporary substrate is provided, the first temporary substrate including a first side and a second side disposed opposite to each other, and a piezoelectric layer is formed on the first side of the first temporary substrate, the piezoelectric layer including at least one piezoelectric thin film layer;

[0009] The piezoelectric layer is patterned to form a first region, a second region, and a third region, and a patterned first electrode layer is formed on the piezoelectric layer in the second region and the third region;

[0010] A first dielectric layer is formed on the first temporary substrate, and the first dielectric layer is patterned to form a cavity or Bragg mirror structure in the third region.

[0011] A second substrate wafer is provided, and the first dielectric layer is bonded to the second substrate wafer and the first temporary substrate is removed;

[0012] A patterned second electrode layer is formed on the piezoelectric layer in the first region, the second region, and the third region;

[0013] Contact vias that expose the first electrode layer are formed in the second region and the third region, and electrode pads are formed in the contact vias to form the first device, the second device and the third device, respectively;

[0014] An interconnect structure is formed on the piezoelectric layer to enable effective electrical connection between the first device, the second device, and the third device.

[0015] Optionally, the piezoelectric layer includes a first piezoelectric thin film layer and a second piezoelectric thin film layer stacked sequentially from the first temporary substrate, and the first piezoelectric thin film layer and the second piezoelectric thin film layer have opposite polarities.

[0016] Optionally, the materials forming the first piezoelectric thin film layer and the second piezoelectric thin film layer include at least three nitrides formed from Al, Ga, In, Sc, B, Y, N or As.

[0017] Optionally, the Bragg reflector structure includes multiple stacked low acoustic impedance layers and high acoustic impedance layers, and the low acoustic impedance layers and the high acoustic impedance layers are stacked sequentially from bottom to top.

[0018] Optionally, the material of the low acoustic impedance layer includes one or more of polyimide, AlN, Si3N4 and SiO2, and the material of the high acoustic impedance layer includes one or more of Ta2O5, W, Mo, Pt, Au, Ni and Ir.

[0019] Optionally, the first device is an acoustic wave filtering device, the second device includes one of a passive device, a diode, or a field-effect transistor, and the third device includes one of a passive device, a diode, or a field-effect transistor.

[0020] Optionally, the width of the cavity or the Bragg reflector structure is greater than or equal to the width of the first electrode layer.

[0021] The present invention also provides a wafer-level radio frequency integrated circuit structure, the wafer-level radio frequency integrated circuit structure comprising:

[0022] A second substrate wafer is provided on the second substrate wafer, and the first dielectric layer includes a first region, a second region and a third region;

[0023] An acoustic wave filtering device is located in the first region. The acoustic wave filtering device includes a first electrode layer, a piezoelectric layer, a cavity structure or a Bragg mirror structure, and a second electrode layer arranged sequentially from top to bottom.

[0024] The second device is located in the second region, and the first device and the second device are insulated from each other by the first dielectric layer;

[0025] A third device is located in the third region, and the second device and the third device are insulated from each other by the first dielectric layer.

[0026] A contact via is located in the first device and the second device and is filled with a metal layer, the metal layer being electrically connected to the first electrode layer.

[0027] Electrode pads and interconnect structures are provided, wherein the electrode pads are electrically connected to a metal layer in the contact via, and the interconnect structures are connected to the electrode pads to form an electrical connection between the first device, the second device, and the third device.

[0028] Optionally, the second device includes one of a passive device, a diode, or a field-effect transistor, and the third device includes one of a passive device, a diode, or a field-effect transistor.

[0029] Optionally, the piezoelectric layer includes a first piezoelectric thin film layer and a second piezoelectric thin film layer stacked sequentially from the first temporary substrate, and the first piezoelectric thin film layer and the second piezoelectric thin film layer have opposite polarities.

[0030] As described above, the wafer-level radio frequency integrated circuit structure and its fabrication method of the present invention have the following advantages compared with the prior art: by simultaneously integrating acoustic wave filtering devices and other functional devices on the same wafer, the miniaturization of the radio frequency front-end module is achieved, greatly improving the chip area utilization rate and meeting the device size requirements of mobile terminals. The electrical connection between different devices is achieved through the metal interconnects inside the chip. Compared with the traditional packaging using ceramic substrates and organic substrates for electrical interconnection, the interconnection distance is greatly shortened, effectively reducing signal loss and delay caused by parasitic inductance, capacitance and resistance, thereby improving the working efficiency and signal integrity of the radio frequency front-end module. Moreover, compared with the traditional substrate interconnection packaging process, the fabrication method of the present invention is simple and can be compatible with standardized processes such as silicon-based CMOS processes, thereby improving the chip area utilization rate and reducing production costs. Attached Figure Description

[0031] Figure 1 shows a process flow diagram of the fabrication method of the wafer-level radio frequency integrated circuit structure provided in an embodiment of the present invention.

[0032] Figure 2 shows a cross-sectional schematic diagram of the first temporary substrate provided in an embodiment of the present invention.

[0033] Figure 3 shows a cross-sectional schematic diagram of a piezoelectric layer formed on a first temporary substrate in an embodiment of the present invention.

[0034] Figure 4 shows a cross-sectional schematic diagram after the formation of the first region, the second region, and the third region in an embodiment of the present invention.

[0035] Figure 5 shows a cross-sectional schematic diagram after the formation of the first electrode layer in an embodiment of the present invention.

[0036] Figure 6 shows a cross-sectional schematic diagram after the formation of the first dielectric layer in an embodiment of the present invention.

[0037] Figure 7 shows a cross-sectional schematic diagram of the Bragg reflector structure formed in an embodiment of the present invention.

[0038] Figure 8 shows a cross-sectional schematic diagram of the cavity structure after it has been formed in another embodiment of the present invention.

[0039] Figure 9 shows a cross-sectional schematic diagram of the second substrate wafer provided in an embodiment of the present invention.

[0040] Figure 10 shows a schematic diagram of the first dielectric layer bonded to the second substrate wafer in an embodiment of the present invention.

[0041] Figure 11 shows a schematic diagram of removing the first temporary substrate in an embodiment of the present invention.

[0042] Figure 12 shows a cross-sectional schematic diagram after the patterned second electrode layer is formed in an embodiment of the present invention.

[0043] Figure 13 shows a cross-sectional schematic diagram after the contact vias and electrode pads are formed in an embodiment of the present invention.

[0044] Figure 14 shows a cross-sectional schematic diagram after the interconnection structure is formed in an embodiment of the present invention.

[0045] Figure 15 shows a cross-sectional schematic diagram of another wafer-level radio frequency integrated circuit structure provided in an embodiment of the present invention.

[0046] Component designation explanation

[0047] 10. First temporary substrate; 101. First surface; 102. Second surface; 11. Piezoelectric layer; 111. First piezoelectric thin film layer; 112. Second piezoelectric thin film layer; 12. Opening; 121. First region; 122. Second region; 123. Third region; 13. First electrode layer; 14. First dielectric layer; 15. Bragg reflector structure; 151. Low acoustic impedance layer; 152. High acoustic impedance layer; 16. Cavity structure; 17. Second substrate wafer; 19. Second electrode layer; 20. Contact via; 21. Electrode pad; 22. Interconnect structure; 210. First device; 310. Second device; 410. Third device; S1~S7: Steps. Detailed Implementation

[0048] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0049] For ease of description, spatial relation terms such as “below,” “under,” “lower than,” “below,” “above,” and “upper” may be used herein to describe the relationship between one element or feature shown in the accompanying drawings and other elements or features. It will be understood that these spatial relation terms are intended to include directions other than those depicted in the drawings for devices in use or operation. Furthermore, when a layer is referred to as being “between” two layers, it may be the only layer between the two layers, or there may be one or more layers in between.

[0050] In the context of this application, the structure described above the first feature may include embodiments in which the first and second features are in direct contact, or embodiments in which additional features are formed between the first and second features, such that the first and second features may not be in direct contact.

[0051] Please refer to Figures 1 to 15. It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the illustrations only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0052] Example 1

[0053] This invention provides a method for fabricating a wafer-level radio frequency integrated circuit structure, as shown in Figure 1, which is a process flow diagram of the fabrication method, including the following steps:

[0054] S1: A first temporary substrate 10 is provided. The first temporary substrate 10 includes a first surface 101 and a second surface 102 disposed opposite to each other. A piezoelectric layer 11 is formed on the first surface 101 of the first temporary substrate 10. The piezoelectric layer 11 includes at least one piezoelectric thin film layer.

[0055] S2: The piezoelectric layer 11 is patterned to form a first region 121, a second region 122 and a third region 123, and a patterned first electrode layer 13 is formed on the piezoelectric layer 11 in the second region 122 and the third region 123.

[0056] S3: A first dielectric layer 14 is formed on the first temporary substrate 10, and the first dielectric layer 14 is patterned to form a cavity or Bragg mirror structure 15 in the third region 123.

[0057] S4: Provide a second substrate wafer 17, bond the second substrate wafer 17 to the first dielectric layer 14 and remove the first temporary substrate 10;

[0058] S5: A patterned second electrode layer 19 is formed on the piezoelectric layer 11 of the first region 121, the second region 122 and the third region 123;

[0059] S6: Form contact vias 20 in the second region 122 and the third region 123 to expose the first electrode layer 13, and form electrode pads 21 in the contact vias 20 to form the first device 210, the second device 310 and the third device 410 respectively.

[0060] S7: An interconnection structure 22 is formed on the piezoelectric layer 11 to achieve effective electrical connection between the first device 210, the second device 310 and the third device 410.

[0061] The fabrication method of the wafer-level radio frequency integrated circuit structure is further described below with reference to the accompanying drawings:

[0062] Please refer to Figures 2 and 3. Perform step S1: Provide a first temporary substrate 10, which includes a first surface 101 and a second surface 102 disposed opposite to each other. Form a piezoelectric layer 11 on the first surface 101 of the first temporary substrate 10. The piezoelectric layer 11 includes at least one piezoelectric thin film layer.

[0063] Specifically, as shown in Figure 2, which is a cross-sectional structural diagram of the first temporary substrate 10, the first temporary substrate 10 includes a first surface 101 and a second surface 102 disposed opposite to each other. The material of the first temporary substrate 10 includes, but is not limited to, single crystal silicon, SOI substrate, silicon carbide, sapphire or gallium nitride, etc. In this embodiment, the first temporary substrate 10 is preferably a single crystal silicon substrate.

[0064] As an example, the piezoelectric layer 11 includes a first piezoelectric thin film layer 111 and a second piezoelectric thin film layer 112 stacked sequentially from the first temporary substrate 10, and the first piezoelectric thin film layer 111 and the second piezoelectric thin film layer 112 have opposite polarities.

[0065] As an example, the materials forming the first piezoelectric thin film layer 111 and the second piezoelectric thin film layer 112 include at least three nitrides formed from Al, Ga, In, Sc, B, Y, N or As.

[0066] Specifically, a piezoelectric layer 11 is formed on the first surface 101 of the first temporary substrate 10 using physical vapor deposition, chemical vapor deposition, spin coating, or other suitable methods. The piezoelectric layer 11 includes at least one piezoelectric thin film layer. In this embodiment, as shown in FIG3, the piezoelectric layer 11 includes a first piezoelectric thin film layer 111 and a second piezoelectric thin film layer 112 stacked sequentially from the first temporary substrate 10. The first piezoelectric thin film layer 111 and the second piezoelectric thin film layer 112 are thin film layers with piezoelectric properties. The materials forming the first piezoelectric thin film layer 111 and the second piezoelectric thin film layer 112 are nitrides formed from Al, Ga, and In.

[0067] Specifically, the first piezoelectric thin film layer 111 and the second piezoelectric thin film layer 112 have opposite polarities, resulting in a 180° phase difference in the piezoelectric response to the electrical signal. The inverse piezoelectric effect causes one of the adjacent first piezoelectric thin film layers 111 and the second piezoelectric thin film layer 112 to be subjected to compressive stress, while the other layer is subjected to tensile stress. This suppresses the first-order asymmetric thickness expansion mode and excites a higher-order thickness expansion mode with a corresponding higher frequency.

[0068] In another example, the piezoelectric layer 11 can also consist of a three-layer structure. By adjusting the thickness of the piezoelectric layer 11, the first electrode layer 13, and the second electrode layer 19, the third-order thickness extension mode can be suppressed, and the fourth-order overtone thickness mode can be excited. When the number of layers in the piezoelectric layer 11 is N, the polarities of adjacent first piezoelectric thin film layers 111 and second piezoelectric thin film layers 112 are opposite, thereby exciting an Nth-order thickness extension mode or an N+1th-order overtone thickness mode, thus improving the operating frequency band.

[0069] Next, referring to Figures 4 and 5, step S2 is performed: the piezoelectric layer 11 is patterned to form a first region 121, a second region 122 and a third region 123, and a patterned first electrode layer 13 is formed on the piezoelectric layer 11 in the second region 122 and the third region 123.

[0070] Specifically, as shown in Figure 4, a patterned first photoresist layer is formed on the piezoelectric layer 11 using a spin coating process. The thickness of the patterned first photoresist layer is not less than 10 micrometers. The patterned first photoresist layer is used as a masking layer to perform photolithography processes such as exposure and development on the piezoelectric layer 11 to form a plurality of openings 12 in the piezoelectric layer 11. The openings 12 expose the first temporary substrate 10. The plurality of openings 12 divide the piezoelectric layer 11 into a first region 121, a second region 122, and a third region 123. A first device 210 is formed in the first region 121, a second device 310 is formed in the second region 122, and a third device 410 is formed in the third region 123.

[0071] As an example, as shown in FIG5, after forming a first electrode layer 13 on the piezoelectric layer 11 in the second region 122 and the third region 123 and then patterning it, the first electrode layer 13 is obtained. The material of the first electrode layer 13 includes one or more of Au, Ag, Ru, W, Mo, Ir, Al, Pt, Nb, and Hf, and the thickness of the first electrode layer 13 does not exceed 0.3 μm. Specifically, in this embodiment, the first electrode layer 13 is a Mo metal layer.

[0072] Next, referring to Figures 6 to 8, step S3 is performed: a first dielectric layer 14 is formed on the first temporary substrate 10, and the first dielectric layer 14 is patterned to form a cavity or Bragg mirror structure 15 in the third region 123.

[0073] As an example, as shown in FIG6, a first dielectric layer 14 is formed on the first temporary substrate 10. The first dielectric layer 14 includes, but is not limited to, materials such as Si, SiO2, SiN, Al2O3, or organic polymers. The first dielectric layer 14 can protect the piezoelectric layer 11 and the subsequently formed Bragg reflector structure 15 from oxidation, and can also protect the piezoelectric layer 11 from damage during subsequent bonding with the second substrate wafer 17. In addition, after forming the first dielectric layer 14, the surface of the first dielectric layer 14 is planarized to make the surface of the first dielectric layer 14 flat, thereby improving the bonding success rate with the second substrate wafer 17.

[0074] As an example, as shown in FIG7, the first dielectric layer 14 is patterned to form a Bragg mirror structure 15 in the third region 123. Specifically, a patterned second photoresist layer is formed on the first dielectric layer 14 using a spin coating process. The patterned second photoresist layer is used as a masking layer to perform photolithography processes such as exposure and development on the first dielectric layer 14 to form a groove in the first dielectric layer 14. The bottom of the groove exposes the first electrode layer 13. The width of the groove is greater than or equal to the second electrode layer 19 so that the width of the Bragg mirror structure 15 is greater than or equal to the second electrode layer 19. The width of electrode layer 19 forms a low acoustic impedance layer 151 covering the first electrode layer 13 in the groove. The surface of the low acoustic impedance layer 151 is planarized by grinding, polishing, etc., and a high acoustic impedance layer 152 is formed on the planarized low acoustic impedance layer 151. The low acoustic impedance layer 151 and the high acoustic impedance layer 152 constitute the Bragg reflector structure 15. The Bragg reflector structure 15 includes multiple stacked low acoustic impedance layers 151 and high acoustic impedance layers 152. In this embodiment, the low acoustic impedance layers 151 and high acoustic impedance layers 152 are stacked alternately twice. The Bragg reflector structure 15 is used to confine sound waves in the piezoelectric layer 11, preventing sound waves from leaking to the second substrate wafer 17 after bonding with the second substrate wafer 17, thereby reducing energy loss, improving the performance of the acoustic filter, and helping to achieve a high Q value and low insertion loss.

[0075] As an example, the material of the low acoustic impedance layer 151 includes one or more of polyimide, AlN, Si3N4 and SiO2, and the material of the high acoustic impedance layer 152 includes one or more of Ta2O5, W, Mo, Pt, Au, Ni and Ir. The thickness of each layer in the Bragg reflector structure 15 is 1 / 4 or 3 / 4 of the wavelength of the sound wave corresponding to the resonant frequency of the resonator.

[0076] It should be noted that this embodiment only illustrates the case where the low acoustic impedance layer 151 and the high acoustic impedance layer 152 are stacked alternately twice. In other embodiments, the low acoustic impedance layer 151 and the high acoustic impedance layer 152 can also be stacked alternately once or more than twice as required, and are not limited to this embodiment.

[0077] In another example, as shown in FIG8, the first dielectric layer 14 is patterned to form a cavity structure 16 in the third region 123. Specifically, a patterned second photoresist layer is formed on the first dielectric layer 14 using a spin coating process. The patterned second photoresist layer is used as a masking layer to perform photolithography processes such as exposure and development on the first dielectric layer 14 to form a groove in the first dielectric layer 14. The bottom of the groove exposes the first electrode layer 13. The width of the groove is greater than or equal to that of the second electrode layer 19 to form the cavity structure. The width of the first electrode layer 13 is greater than or equal to the width of the second electrode layer 19. Through subsequent bonding with the second substrate wafer 17, a cavity structure 16 can be formed as shown in FIG. 15, which is surrounded by the first electrode layer 13, the second substrate wafer 17 and the first dielectric layer 14. The cavity structure 16 serves as an acoustic mirror structure to confine sound waves within the piezoelectric layer 11, preventing sound waves from leaking to the second substrate wafer 17 after bonding with it, thereby reducing energy loss, improving the performance of the acoustic filter, and helping to achieve a high Q value and low insertion loss.

[0078] Next, referring to Figures 9 to 11, step S4 is performed: a second substrate wafer 17 is provided, and the second substrate wafer 17 is bonded to the first dielectric layer 14 to remove the first temporary substrate 10.

[0079] As an example, as shown in FIG9, the material of the second substrate wafer 17 includes, but is not limited to, single crystal silicon, silicon carbide, germanium, sapphire or gallium nitride, etc. As shown in FIG10, the structure forming the first dielectric layer 14 is inverted so that the first dielectric layer 14 and the second substrate wafer 17 are bonded together. Optionally, in order to improve the bonding effect, a second dielectric layer can also be formed on the second substrate wafer 17.

[0080] As an example, as shown in FIG11, the second substrate wafer 17 is bonded to the first dielectric layer 14 and the first temporary substrate 10 is removed. The method for removing the first temporary substrate 10 includes, but is not limited to, one or more of ion implantation stripping, mechanical polishing, polishing, wet etching, and dry etching.

[0081] As an example, after removing the first temporary substrate 10, the bottom surface of the piezoelectric layer 11 is exposed. During the removal of the first temporary substrate 10, the quality of the bottom surface of the piezoelectric layer 11 will be damaged to a certain extent. Please refer to Figure 9. After removing the first temporary substrate 10, a step of thinning the bottom surface of the piezoelectric layer 11 is also included to remove the piezoelectric layer 11 with poor quality. The method of thinning the piezoelectric layer 11 includes etching, polishing or other suitable methods.

[0082] As an example, referring to Figure 3, when forming the piezoelectric layer 11, the initial thickness of the first piezoelectric thin film layer 111 is appropriately increased, so that even if the first temporary substrate 10 is removed in step S4 and the bottom surface of the piezoelectric layer 11 is thinned, the thickness of the first piezoelectric thin film layer 111 will not differ too much from that of the second piezoelectric thin film layer 112, thereby improving the thickness uniformity of the piezoelectric layer 11. Furthermore, a thicker piezoelectric layer 11 can significantly improve manufacturing yield and manufacturing stability.

[0083] Next, referring to Figure 12, step S5 is performed: a patterned second electrode layer 19 is formed on the piezoelectric layer 11 of the first region 121, the second region 122 and the third region 123.

[0084] As an example, a second electrode material layer is formed and patterned on the side of the piezoelectric layer 11 away from the second substrate wafer 17 to obtain the second electrode layer 19. The material of the second electrode layer 19 includes one or more of Au, Ag, Ru, W, Mo, Ir, Al, Pt, Nb, and Hf. Specifically, in this embodiment, the second electrode layer 19 is a Mo metal layer.

[0085] Next, referring to FIG13, step S6 is performed: a contact via 20 is formed in the second region 122 and the third region 123 to expose the first electrode layer 13, and an electrode pad 21 is formed in the contact via 20 to form the first device 210, the second device 310 and the third device 410 respectively.

[0086] As an example, as shown in FIG13, before forming the electrode pad 21, a contact via 20 is formed in the piezoelectric layer 11 in the second region 122 and the third region 123, penetrating the piezoelectric layer 11, and the bottom of the contact via 20 exposes the first electrode layer 13.

[0087] As an example, the electrode pad 21 extends into the contact via 20 and is electrically connected to the first electrode layer 13. The electrode pad 21 is used to lead out electrodes from the first electrode layer 13, thereby forming a first device 210 in the first region 121, a second device 310 in the second region 122, and a third device 410 in the third region 123. Specifically, in this embodiment, the first device 210 is an acoustic wave filter device, the second device 310 includes one of a passive device, a diode, or a field-effect transistor, and the third device 410 includes one of a passive device, a diode, or a field-effect transistor.

[0088] Next, referring to Figure 14, step S7 is performed: an interconnect structure 22 is formed on the piezoelectric layer 11 to achieve effective electrical connection between the first device 210, the second device 310 and the third device 410.

[0089] As an example, an interconnect structure 22 is formed on the piezoelectric layer 11. The material of the interconnect structure 22 includes one or more of Au, Ag, Ru, W, Mo, Ir, Al, Pt, Nb, and Hf. Specifically, as shown in FIG14, in this embodiment, the interconnect structure 22 is made of Cu metal. The interconnect structure 22 is connected to the metal pad and the second electrode layer 19 in the third device 410, respectively, so that the first device 210, the second device 310 and the third device 410 are effectively electrically connected.

[0090] This embodiment achieves miniaturization of the RF front-end module by simultaneously integrating acoustic filters and other functional devices on the same wafer, greatly improving the chip area utilization and meeting the device size requirements of mobile terminals. Electrical connections between different devices are achieved through metal interconnects inside the chip. Compared with traditional packaging using ceramic substrates or organic substrates for electrical interconnection, the interconnection distance is greatly shortened, effectively reducing signal loss and delay caused by parasitic inductance, capacitance, and resistance, thereby improving the working efficiency and signal integrity of the RF front-end module.

[0091] Example 2

[0092] Based on the same inventive concept, this embodiment also provides a wafer-level radio frequency integrated circuit structure, which is fabricated using the preparation method described in Embodiment 1 or other suitable similar methods. For details regarding the fabrication method, materials, and structure of the wafer-level radio frequency integrated circuit structure, please refer to Embodiment 1. In this embodiment, as shown in Figure 14, which is a cross-sectional schematic diagram of the wafer-level radio frequency integrated circuit structure, the wafer-level radio frequency integrated circuit structure includes:

[0093] The wafer-level radio frequency integrated circuit structure includes: a second substrate wafer 17, on which a first dielectric layer 14 is disposed, the first dielectric layer 14 including a first region 121, a second region 122, and a third region 123; an acoustic wave filter device, the acoustic wave filter device being located in the first region 121, the acoustic wave filter device including a first electrode layer 13, a piezoelectric layer 11, a Bragg reflector structure 15, and a second electrode layer 19 arranged sequentially from top to bottom; a second device 310, the second device 310 being located in the second region 122, and the first device 210 and the second device 310 being insulated from each other by the first dielectric layer 14; and a third device. The device 410 is located in the third region 123, and the second device 310 and the third device 410 are insulated from each other by the first dielectric layer 14. A contact via 20 is located in the first device 210 and the second device 310, and the contact via 20 is filled with a metal layer, which is electrically connected to the first electrode layer 13. An electrode pad 21 and an interconnect structure 22 are also included, where the electrode pad 21 is electrically connected to the metal layer in the contact via 20, and the interconnect structure 22 is connected to the electrode pad 21 to form an electrical connection between the first device 210, the second device 310, and the third device 410.

[0094] As an example, the piezoelectric layer 11 includes a first piezoelectric thin film layer 111 and a second piezoelectric thin film layer 112 stacked sequentially from the first temporary substrate 10, and the first piezoelectric thin film layer 111 and the second piezoelectric thin film layer 112 have opposite polarities.

[0095] Specifically, the first piezoelectric thin film layer 111 and the second piezoelectric thin film layer 112 have opposite polarities, resulting in a 180° phase difference in the piezoelectric response to the electrical signal. The inverse piezoelectric effect causes one of the adjacent first piezoelectric thin film layers 111 and the second piezoelectric thin film layer 112 to be subjected to compressive stress, while the other is subjected to tensile stress, suppressing the first-order asymmetric thickness expansion mode and exciting higher-order thickness expansion modes with corresponding higher frequencies.

[0096] As an example, the second device 310 includes one of a passive device, a diode, or a field-effect transistor, and the third device 410 includes one of a passive device, a diode, or a field-effect transistor.

[0097] Example 3

[0098] This embodiment also provides another wafer-level radio frequency integrated circuit structure, as shown in Figure 15. In the wafer-level radio frequency integrated circuit structure of this embodiment, the acoustic wave filtering device includes a first electrode layer 13, a piezoelectric layer 11, a cavity structure 16, and a second electrode layer 19 arranged sequentially from top to bottom. The remaining structures can be referred to Embodiment 2, and will not be described in detail here.

[0099] In summary, the wafer-level RF integrated circuit structure and its fabrication method of the present invention have the following advantages compared with the prior art: By simultaneously integrating acoustic wave filtering devices and other functional devices on the same wafer, the miniaturization of the RF front-end module is achieved, greatly improving the chip area utilization rate and meeting the device size requirements of mobile terminals. Electrical connections between different devices are achieved through internal metal interconnects, significantly shortening the interconnection distance compared to traditional packaging using ceramic or organic substrates for electrical interconnection. This effectively reduces signal loss and delay caused by parasitic inductance, capacitance, and resistance, thereby improving the working efficiency and signal integrity of the RF front-end module. Furthermore, compared to traditional substrate interconnection packaging processes, the fabrication method of the present invention is simpler and compatible with standardized processes such as silicon-based CMOS processes, thereby improving chip area utilization and reducing production costs. Therefore, the present invention effectively overcomes the various shortcomings of the prior art and has high industrial applicability.

[0100] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A method for fabricating a wafer-level radio frequency integrated circuit structure, characterized in that, Includes the following steps: A first temporary substrate is provided, the first temporary substrate including a first surface and a second surface disposed opposite to each other, a piezoelectric layer is formed on the first surface of the first temporary substrate, the piezoelectric layer including at least one piezoelectric thin film layer; the piezoelectric layer is patterned to form a first region, a second region and a third region, and a patterned first electrode layer is formed on the piezoelectric layer in the second region and the third region; A first dielectric layer is formed on the first temporary substrate, and the first dielectric layer is patterned to form a cavity structure or a Bragg mirror structure in the third region. A second substrate wafer is provided, the second substrate wafer is bonded to the first dielectric layer and the first temporary substrate is removed; a patterned second electrode layer is formed on the piezoelectric layer in the first region, the second region and the third region; contact vias are formed in the second region and the third region to expose the first electrode layer, and electrode pads are formed in the contact vias to form a first device, a second device and a third device respectively; an interconnect structure is formed on the piezoelectric layer to achieve effective electrical connection between the first device, the second device and the third device.

2. The method for fabricating a wafer-level radio frequency integrated circuit structure according to claim 1, characterized in that: The piezoelectric layer includes a first piezoelectric thin film layer and a second piezoelectric thin film layer stacked sequentially from the first temporary substrate, and the first piezoelectric thin film layer and the second piezoelectric thin film layer have opposite polarities.

3. The method for fabricating a wafer-level radio frequency integrated circuit structure according to claim 2, characterized in that: The materials forming the first piezoelectric thin film layer and the second piezoelectric thin film layer include at least three nitrides formed from Al, Ga, In, Sc, B, Y, N or As.

4. The method for fabricating a wafer-level radio frequency integrated circuit structure according to claim 1, characterized in that: The Bragg reflector structure includes multiple stacked low acoustic impedance layers and high acoustic impedance layers, and the low acoustic impedance layers and the high acoustic impedance layers are stacked sequentially from bottom to top.

5. The method for fabricating a wafer-level radio frequency integrated circuit structure according to claim 4, characterized in that: The material of the low acoustic impedance layer includes one or more of polyimide, AlN, Si3N4 and SiO2, and the material of the high acoustic impedance layer includes one or more of Ta2O5, W, Mo, Pt, Au, Ni and Ir.

6. The method for fabricating a wafer-level radio frequency integrated circuit structure according to claim 1, characterized in that: The first device is an acoustic wave filtering device, the second device includes one of a passive device, a diode or a field-effect transistor, and the third device includes one of a passive device, a diode or a field-effect transistor.

7. The method for fabricating a wafer-level radio frequency integrated circuit structure according to claim 1, characterized in that: The width of the cavity structure or the Bragg reflector structure is greater than or equal to the width of the second electrode layer.

8. A wafer-level radio frequency integrated circuit structure, characterized in that, The wafer-level radio frequency integrated circuit structure includes: a second substrate wafer on which a first dielectric layer is disposed, the first dielectric layer including a first region, a second region, and a third region; an acoustic wave filter device located in the first region, the acoustic wave filter device including a first electrode layer, a piezoelectric layer, a cavity structure or a Bragg mirror structure arranged sequentially from top to bottom, and a second electrode layer; a second device located in the second region, and the first device and the second device are insulated from each other by the first dielectric layer; a third device located in the third region, and the second device and the third device are insulated from each other by the first dielectric layer; a contact via located in the first device and the second device, the contact via being filled with a metal layer, the metal layer being electrically connected to the first electrode layer; electrode pads and interconnect structures, the electrode pads being electrically connected to the metal layer in the contact vias, and the interconnect structures being connected to the electrode pads to form an electrical connection between the first device, the second device, and the third device.

9. The wafer-level radio frequency integrated circuit structure according to claim 8, characterized in that: The second device includes one of a passive device, a diode, or a field-effect transistor, and the third device includes one of a passive device, a diode, or a field-effect transistor.

10. The wafer-level radio frequency integrated circuit structure according to claim 8, characterized in that: The piezoelectric layer includes a first piezoelectric thin film layer and a second piezoelectric thin film layer stacked sequentially, and the first piezoelectric thin film layer and the second piezoelectric thin film layer have opposite polarities.

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