Structure and method for improving reliability of high-resistance region in metal gate process

Abstract

The invention discloses a structure for improving the reliability of a high-resistance region in a metal gate process. High resistance is formed at the top of shallow trench isolation with a metal gate. A first transverse distance is formed between the high resistor and the adjacent pseudo active region, and the first transverse distance is used for adjusting the pattern density of the pseudo active region and enabling the height and the uniformity of shallow trench isolation to meet the requirements. The interlayer film has a first thickness and the first thickness satisfies a process requirement of a contact hole passing through the interlayer film. The interlayer film is divided into a first interlayer sub-film and a second interlayer sub-film. The high resistance is between the first and second interlayer sub-films, the first interlayer sub-film having a second thickness. And the second thickness is used for adjusting a second longitudinal distance between the high resistor and the adjacent pseudo active region, so that the minimum distance between the high resistor and the adjacent pseudo active region meets the voltage withstanding requirement under the condition that the first transverse distance is not increased. The invention also discloses a method for improving the reliability of the high-resistance region in the metal gate process.

Description

Technical Field

[0001] This invention relates to the field of semiconductor integrated circuit manufacturing, and in particular to a structure for improving the reliability of high-resistivity regions in metal gate processes. This invention also relates to a method for improving the reliability of high-resistivity regions in metal gate processes. Background Technology

[0002] Currently, 28nm and above nanometers use metal as the gate, i.e., metal gate (MG). This cannot provide the resistance of conventional polysilicon resistors. For circuit use, titanium nitride (TiN) is used alone as a high-resistivity material (HiR) in the metal gate process. After the metal gate is formed, a dielectric layer is grown, and then titanium nitride is deposited to provide high resistance. In practice, this resistor needs to be placed above the metal gate to prevent instability in the length of the titanium nitride caused by the depressions after grinding the interlayer dielectric layer.

[0003] When using this resistor extensively in the outer protection area, a challenge is ensuring sufficient active region density to guarantee proper chemical mechanical polishing (CMP) of the shallow trench isolation (STI) region. Currently, a pseudo-active region pattern is inserted around this high-resistance area. The closer the pseudo-active region is to the high resistor, the higher its pattern density, which benefits the active region's processing and the height and uniformity of the shallow trench isolation area beneath the high-resistance region. In the input / output ESD protection circuits, titanium nitride resistors are used to provide RC delay. In this region, during mechanical discharge mode, transient high voltages as high as 200V can occur, leading to leakage or even breakdown between the adjacent active region and the high resistor. Existing methods, to address this issue, require increasing the distance between the active region's dummy pattern and the high resistor. This creates a conflict between the closer active region dummy pattern required for CMP in the shallow trench isolation region and the further active region dummy pattern needed to prevent leakage in the high-resistance region.

[0004] like Figure 1 The diagram shown is a layout of the existing high-resistivity region; as shown... Figure 2 As shown, this is the existing high-resistivity region along... Figure 1 A schematic diagram of the cross-sectional structure at line AA'; the existing high-resistivity region structure includes: Multiple shallow trench isolations 102 formed in a semiconductor substrate 101 and multiple pseudo-active regions located between the shallow trench isolations 102. Figure 2 In the pseudo-active region, a P-type doped region 103 is formed on the surface region, and the pattern of the pseudo-active region is the same as the pattern of the doped region 103.

[0005] A metal gate 105 is formed on the top of the shallow trench isolation 102, and a high-resistivity 107 composed of a TiN layer is formed on the top of the metal gate 105.

[0006] At least a portion of the periphery of the shallow trench isolation 102 at the bottom of the high resistance 107 has the pseudo-active region. Figure 1 As shown, each of the high-resistance 107 has the pseudo-active region on three sides.

[0007] Interlayer membrane 106 covers the top of each of the shallow trench isolation 102 and each of the pseudo-active regions; interlayer membrane 106 covers the metal gate 105, and the high resistance 107 is inserted into the interlayer membrane 106 on top of the metal gate 105.

[0008] like Figure 1 As shown, each of the high-resistance 107 has a strip-shaped structure.

[0009] Back Figure 2 As shown, first contact holes 108a are formed at the top of both ends of the high resistance 107.

[0010] like Figure 1 As shown, it also includes a substrate lead-out region 104. The substrate lead-out region 104 has a ring structure, and each of the high-resistance 107 is located inside the ring region of the substrate lead-out region 104.

[0011] Back Figure 2 As shown, the semiconductor substrate 101 is P-type doped, the substrate lead-out region 104 is heavily P-type doped, and a second contact hole 108b is formed on the top of the substrate lead-out region 104, passing through the interlayer film 106.

[0012] The high resistance 107 is located directly above the metal gate 105, and the high resistance 107 also extends to the outside of the metal gate 105.

[0013] like Figure 2 As shown, since the high resistance region is surrounded by a high voltage region, and high voltage devices are formed in the high voltage region, the high voltage in the high voltage region can easily cause a breakdown as shown by mark 201 between the high resistance 107 and the adjacent pseudo-active region, and form a leakage path as shown by dashed line 202.

[0014] To address the breakdown problem corresponding to marker 201, existing methods require increasing the spacing between the high-resistance 107 and the adjacent pseudo-active region. In other words, the width of the shallow trench isolation 102 located outside the high-resistance 107 needs to be increased. However, this is not conducive to reducing the pattern density of the shallow trench isolation 102 in the high-resistance region, and therefore is not conducive to optimizing the grinding load of the chemical mechanical polishing process of the shallow trench isolation 102. Summary of the Invention

[0015] The technical problem to be solved by this invention is to provide a structure that improves the reliability of high-resistivity regions in metal gate processes. This structure increases the breakdown voltage of high resistance without increasing the lateral spacing between high resistance and pseudo-active regions within the high-resistivity region. This ensures the pattern density of the pseudo-active region, meets the requirements for the height and uniformity of shallow trench isolation, and simultaneously meets the breakdown voltage requirements of the high resistance. To this end, this invention also provides a method for improving the reliability of high-resistivity regions in metal gate processes.

[0016] To address the aforementioned technical problems, this invention provides a structure for improving the reliability of high-resistivity regions in metal gate processes. The structure of the high-resistivity region includes: Multiple shallow trench isolations formed in a semiconductor substrate and multiple pseudo-active regions located between the shallow trench isolations; a metal gate is formed on top of a portion of the shallow trench isolations and a high-resistivity TiN layer is formed on top of the metal gate.

[0017] At least a portion of the periphery of the shallow trench isolation at the bottom of the high resistance has the pseudo-active region. There is a first lateral spacing between the high resistance and the adjacent pseudo-active region. The smaller the first lateral spacing, the greater the pattern density of the pseudo-active region and the larger the area ratio of the pseudo-active region and the shallow trench isolation in each region of the high resistance. The area ratio of the pseudo-active region and the shallow trench isolation must ensure that the height and uniformity of the shallow trench isolation meet the requirements.

[0018] An interlayer membrane covers the top of each of the shallow trench isolations and each of the pseudo-active regions; the interlayer membrane has a first thickness; on top of the shallow trench isolations where the high resistance is formed, the interlayer membrane is divided into a first interlayer sub-membrane and a second interlayer sub-membrane.

[0019] The first interlayer submembrane covers the metal grid, and outside the metal grid, the first interlayer submembrane has a second thickness.

[0020] The second interlayer membrane covers the high resistance. Outside the high resistance, the second interlayer membrane has a third thickness, and the first thickness is the sum of the second thickness and the third thickness. The first thickness satisfies the process requirements for forming contact holes through the interlayer membrane.

[0021] The second thickness is used to adjust the second longitudinal spacing between the high resistance and the adjacent pseudo-active region. Under the condition that the first lateral spacing does not increase, the second longitudinal spacing is increased by increasing the second thickness, so that the minimum spacing between the high resistance and the adjacent pseudo-active region meets the withstand voltage requirement.

[0022] A further improvement is that each of the high-resistance components has a strip-shaped structure, and a first contact hole passing through the second interlayer membrane is formed at each end of the high-resistance component.

[0023] A further improvement includes a substrate lead-out region.

[0024] The substrate lead-out area has a ring structure, and each of the high resistances is located inside the ring region of the substrate lead-out area.

[0025] The semiconductor substrate is doped with a second conductivity type, the substrate lead-out region is heavily doped with a second conductivity type, and a second contact hole is formed at the top of the substrate lead-out region, penetrating the interlayer film.

[0026] A further improvement is that a gate dielectric layer is formed at the bottom of the metal gate.

[0027] A further improvement is that the material of the gate dielectric layer includes a high dielectric constant material (HK).

[0028] A further improvement is that the high resistance is located directly above the metal gate, and the high resistance also extends to the outside of the metal gate.

[0029] A further improvement is that the high-resistivity region is located outside the device cell region, in which the metal gate is formed on the surface of the semiconductor substrate, and a third contact hole through the interlayer film is formed on top of the metal gate.

[0030] To address the aforementioned technical problems, the present invention provides a method for improving the reliability of high-resistivity regions in metal gate processes, comprising the following steps: Shallow trench isolation is formed in the semiconductor substrate, and the semiconductor substrate surrounded by the shallow trench isolation constitutes an active region; in the high-resistivity region, the active region between the shallow trench isolations is a pseudo-active region; the shallow trench isolation is formed by etching and filling the shallow trenches and chemical mechanical polishing; in the high-resistivity region, the pseudo-active region is used to adjust the pattern density in the high-resistivity region. The greater the pattern density of the pseudo-active region, the greater the area ratio of the pseudo-active region and the shallow trench isolation in each region of the high-resistivity region. The area ratio of the pseudo-active region and the shallow trench isolation meets the chemical mechanical polishing load requirements and thus ensures that the height and uniformity of the shallow trench isolation meet the requirements.

[0031] A metal gate is formed; in the high-resistivity region, the metal gate is formed on a surface that will form a high-resistivity shallow trench isolation on top.

[0032] A first interlayer membrane is formed, which covers the top of each of the shallow trench isolations and each of the pseudo-active regions and covers the metal gate; outside the metal gate, the first interlayer membrane has a second thickness.

[0033] A high-resistance layer composed of TiN is formed, the high-resistance being located on top of the corresponding metal gate; at least a portion of the periphery isolated by the shallow trench at the bottom of the high-resistance has the pseudo-active region, a first lateral spacing is provided between the high-resistance and the adjacent pseudo-active region, the first lateral spacing being used to adjust the pattern density of the pseudo-active region, the smaller the first lateral spacing, the greater the pattern density of the pseudo-active region; a second thickness is used to adjust the second longitudinal spacing between the high-resistance and the adjacent pseudo-active region, the second longitudinal spacing is increased by increasing the second thickness while ensuring that the first lateral spacing does not increase, thereby making the minimum spacing between the high-resistance and the adjacent pseudo-active region meet the withstand voltage requirement.

[0034] A second interlayer membrane is formed by stacking the first and second interlayer membranes; the second interlayer membrane covers the high resistance, and outside the high resistance, the second interlayer membrane has a third thickness, the first thickness being the sum of the second thickness and the third thickness; the first thickness satisfies the process requirements for forming a contact hole through the interlayer membrane.

[0035] Further improvements include: A contact hole is formed; each of the high resistances is in the form of a strip structure, and the contact hole includes a first contact hole located at both ends of the high resistance, the first contact hole passing through the second interlayer membrane.

[0036] A further improvement includes a substrate lead-out region.

[0037] The substrate lead-out area has a ring structure, and each of the high resistances is located inside the ring region of the substrate lead-out area.

[0038] The semiconductor substrate is doped with a second conductivity type, the substrate lead-out region is heavily doped with a second conductivity type, and a second contact hole is formed at the top of the substrate lead-out region, penetrating the interlayer film.

[0039] A further improvement is that a gate dielectric layer is formed at the bottom of the metal gate.

[0040] A further improvement is that the material of the gate dielectric layer includes a high dielectric constant material.

[0041] A further improvement is that the high resistance is located directly above the metal gate, and the high resistance also extends to the outside of the metal gate.

[0042] A further improvement is that the high-resistivity region is located outside the device cell region, in which the metal gate is formed on the surface of the semiconductor substrate, and a third contact hole through the interlayer film is formed on top of the metal gate.

[0043] This invention adjusts the thickness of the interlayer film at the top and bottom of a high-resistivity region. While keeping the total thickness of the interlayer film (the first thickness) constant, the thickness of the bottom portion of the interlayer film (the first interlayer sub-film, the second thickness) is increased to increase the longitudinal spacing (the second longitudinal spacing) between the high-resistivity region and the adjacent pseudo-active region. This increases the total spacing between the high-resistivity region and the pseudo-active region while keeping the lateral spacing (the first lateral spacing) constant. Consequently, the withstand voltage between the high-resistivity region and the pseudo-active region is increased, thus improving the reliability of the device.

[0044] Since the first lateral spacing is not limited by the withstand voltage of the high resistance, the pattern density of the pseudo-active region can be increased by reducing the first lateral spacing. This ensures the load of chemical mechanical polishing for forming shallow trench isolation, thereby enabling the height and uniformity of the shallow trench isolation in the high resistance region to meet the requirements and thus improve the performance of the device.

[0045] Furthermore, since the total thickness of the interlayer film of the present invention does not change, it will not affect the process structure of the contact hole, such as the size of the contact hole, nor will it affect the etching process and the filling process. Attached Figure Description

[0046] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments: Figure 1 It is a layout of the existing high-resistivity region structure; Figure 2 It is along the existing high-resistivity region Figure 1 A schematic diagram of the cross-sectional structure at line AA' in the middle; Figure 3 This invention provides a structural improvement for the reliability of high-resistivity regions in metal gate processes. Figure 1 A schematic diagram of the cross-sectional structure at line AA' in the middle; Figure 4 This is a schematic diagram of the cross-sectional structure of the device after forming high resistance in the method for improving the reliability of high resistance regions in metal gate processes according to an embodiment of the present invention. Detailed Implementation

[0047] Please also refer to the layout structure of the structure that improves the reliability of the high-resistivity region in the metal gate 105 process according to the embodiments of the present invention. Figure 1 As shown, Figure 3 As shown, this is an embodiment of the present invention illustrating the structure for improving the reliability of the high-resistivity region in the metal gate 105 process. Figure 1 A schematic diagram of the cross-sectional structure at line AA' in the diagram; a structure of the present invention that improves the reliability of the high-resistivity region in the metal gate 105 process. Figure 3 In the diagram, the high-resistivity region is located within the dashed box 301. The structure of the high-resistivity region includes: Multiple shallow trench isolations 102 formed in a semiconductor substrate 101 and multiple pseudo-active regions located between the shallow trench isolations 102. Figure 3 In the pseudo-active region, a doped region 103 of a second conductivity type is formed in the surface region of the pseudo-active region, and the pattern of the pseudo-active region is the same as the pattern of the doped region 103.

[0048] A metal gate 105 is formed on the top of the shallow trench isolation 102, and a high-resistivity 107 composed of a TiN layer is formed on the top of the metal gate 105.

[0049] At least a portion of the periphery of the shallow trench isolation 102 at the bottom of the high-resistivity 107 has the pseudo-active region. A first lateral spacing exists between the high-resistivity 107 and the adjacent pseudo-active region. The smaller the first lateral spacing, the greater the pattern density of the pseudo-active region and the larger the area ratio of the pseudo-active region to the shallow trench isolation 102 in each region of the high-resistivity region. The area ratio of the pseudo-active region to the shallow trench isolation 102 must ensure that the height and uniformity of the shallow trench isolation 102 meet the requirements. After dielectric filling, the shallow trench isolation 102 needs to be planarized using chemical mechanical polishing (CMP). However, CMP has a loading effect. If the area of ​​the shallow trench isolation 102 in the high-resistivity region is too large, the corresponding pattern density of the shallow trench isolation 102 increases, which is equivalent to an increase in the pattern density of the shallow trench isolation 103 in the device unit region outside the high-resistivity region. This will result in different polishing loads in different regions, thus causing differences in the height and uniformity of the shallow trench isolation 102. To address this, embodiments of the present invention provide a pseudo-active region to reduce the area of ​​the shallow trench isolation 102. By increasing the area of ​​the pseudo-active region, under the condition that the area of ​​the high-resistivity region is equal, the pattern density of the pseudo-active region increases after the area of ​​the pseudo-active region increases, and correspondingly, the pattern density of the shallow trench isolation 103 decreases. This allows adjustment of the grinding load of the shallow trench isolation 103 in the high-resistivity region and makes the grinding load of the shallow trench isolation 103 in the high-resistivity region and the grinding load of the shallow trench isolation 103 outside the high-resistivity region tend to be consistent, thereby ensuring that the height and uniformity of the shallow trench isolation 102 meet the requirements.

[0050] Interlayer membrane 106 covers the top of each of the shallow trench isolation 102 and each of the pseudo-active regions; the interlayer membrane 106 has a first thickness d1; on the top of the shallow trench isolation 102 where the high resistance 107 is formed, the interlayer membrane 106 is divided into a first interlayer sub-membrane 106a and a second interlayer sub-membrane 106b.

[0051] The first interlayer sub-film 106a covers the metal gate 105, and outside the metal gate 105, the first interlayer sub-film 106a has a second thickness d2.

[0052] The second interlayer membrane 106b covers the high resistance 107. Outside the high resistance 107, the second interlayer membrane 106b has a third thickness d3. The first thickness d1 is the sum of the second thickness d2 and the third thickness d3. The first thickness d1 satisfies the process requirements for forming a contact hole through the interlayer membrane 106.

[0053] The second thickness d2 is used to adjust the second longitudinal spacing between the high resistor 107 and the adjacent pseudo-active region. Under the condition that the first lateral spacing does not increase, the second longitudinal spacing is increased by increasing the second thickness d2, so that the minimum spacing l1 between the high resistor 107 and the adjacent pseudo-active region meets the withstand voltage requirement.

[0054] like Figure 1 As shown in the embodiment of the present invention, each of the high-resistance 107 has a strip-shaped structure.

[0055] Back Figure 3 As shown, first contact holes 108a are formed at both ends of the high resistance 107, passing through the second interlayer membrane 106b.

[0056] like Figure 1 As shown, it also includes: substrate lead-out region 104.

[0057] The substrate lead-out region 104 has a ring structure, and each of the high resistances 107 is located inside the ring region of the substrate lead-out region 104.

[0058] Back Figure 3 As shown, the semiconductor substrate 101 is doped with a second conductivity type, and the substrate lead-out region 104 is heavily doped with the second conductivity type. A second contact hole 108b is formed on the top of the substrate lead-out region 104, penetrating the interlayer film 106. In some embodiments, the second conductivity type is P-type, that is, the semiconductor substrate 101 is P-type doped, the doped region 103 is also P-type doped, and the doping concentration of the doped region 103 is greater than that of the semiconductor substrate 101.

[0059] In this embodiment of the invention, a gate dielectric layer is further formed at the bottom of the metal gate 105. The material of the gate dielectric layer includes a high dielectric constant material. The gate dielectric layer and the metal gate 105 are stacked to form an HKMG.

[0060] The high resistance 107 is located directly above the metal gate 105, and the high resistance 107 also extends to the outside of the metal gate 105.

[0061] The high-resistivity region is located outside the device cell region. Figure 3 The diagram also shows the structure of a portion of the device cell region, with the structure located outside the dashed frame 301 representing the structure of the device cell region. In the device cell region, a metal gate 105 is formed on the surface of the semiconductor substrate 101, and a third contact hole 108c is formed on top of the metal gate 105, penetrating the interlayer film 106.

[0062] Compared with the existing structure, in this embodiment of the invention, the height h1 of the first contact hole 108a is reduced, but the distance h4 between the metal gate 105 and the high resistance 107 at the top is increased, and the increase in distance h4 corresponds to the increase in d2.

[0063] However, since the total thickness d1 of the interlayer film 106 remains unchanged, the height h2 of the second contact hole 108b and the height h3 of the third contact hole 108c will also remain unchanged.

[0064] In this embodiment of the invention, the thickness of the interlayer film 106 at the top and bottom of the high resistance 107 is adjusted. While keeping the total thickness of the interlayer film 106, i.e., the first thickness d1, constant, the thickness of the bottom portion of the interlayer film 106, i.e., the first interlayer sub-film 106a, i.e., the second thickness d2, is increased to increase the longitudinal spacing between the high resistance 107 and the adjacent pseudo-active region, i.e., the second longitudinal spacing. This allows the total spacing between the high resistance 107 and the pseudo-active region to be increased while keeping the lateral spacing between the high resistance 107 and the pseudo-active region in the high resistance region constant, i.e., the first lateral spacing. This increases the withstand voltage between the high resistance 107 and the pseudo-active region, thereby increasing the reliability of the device. Figure 3 In the diagram, the leakage path corresponding to the dashed line 302 is broken, indicating that there is no breakdown between the high resistance 107 and the adjacent pseudo-active region, and therefore no leakage.

[0065] Since the first lateral spacing is not limited by the withstand voltage of the high resistance 107, the pattern density of the pseudo-active region can be increased by reducing the first lateral spacing. This ensures the load of chemical mechanical polishing for forming the shallow trench isolation 102, thereby enabling the height and uniformity of the shallow trench isolation 102 in the high resistance region to meet the requirements and thus improve the performance of the device.

[0066] Furthermore, since the total thickness of the interlayer film 106 in this embodiment of the invention does not change, it will not affect the process structure of the contact hole, such as the size of the contact hole, nor will it affect the etching process and the filling process.

[0067] like Figure 4 The diagram shown is a schematic cross-sectional view of the device after forming a high resistance region in the method for improving the reliability of the high resistance region in the metal gate process according to an embodiment of the present invention. The method for improving the reliability of the high resistance region in the metal gate 105 process according to an embodiment of the present invention includes the following steps: like Figure 4 As shown, shallow trench isolation 102 is formed in the semiconductor substrate 101, and the semiconductor substrate 101 surrounded by the shallow trench isolation 102 constitutes an active region; in the high-resistivity region, the active region between the shallow trench isolation 102 is a pseudo-active region; the shallow trench isolation 102 is formed by etching and filling the shallow trenches and chemical mechanical polishing; in the high-resistivity region, the pseudo-active region is used to adjust the pattern density in the high-resistivity region. The greater the pattern density of the pseudo-active region, the greater the area ratio of the pseudo-active region and the shallow trench isolation 102 in each region of the high-resistivity region. The area ratio of the pseudo-active region and the shallow trench isolation 102 meets the chemical mechanical polishing load requirements and thus ensures that the height and uniformity of the shallow trench isolation 102 meet the requirements.

[0068] like Figure 4 As shown, a metal gate 105 is formed; in the high-resistivity region, the metal gate 105 is formed on the surface of the shallow trench isolation 102, which will form a high-resistivity 107 on top.

[0069] In the method of this embodiment of the invention, a gate dielectric layer is also formed at the bottom of the metal gate 105.

[0070] The material of the gate dielectric layer includes a high dielectric constant material.

[0071] The high resistance 107 is located directly above the metal gate 105, and the high resistance 107 also extends to the outside of the metal gate.

[0072] like Figure 4 As shown, a first interlayer sub-membrane 106a is formed, which covers the top of each of the shallow trench isolation 102 and each of the pseudo-active regions and covers the metal gate; outside the metal gate 105, the first interlayer sub-membrane 106a has a second thickness d2.

[0073] like Figure 4As shown, a high-resistivity 107 composed of a TiN layer is formed, and the high-resistivity 107 is located on top of the corresponding metal gate 105. By placing the high-resistivity 107 on top of the metal gate 105, since the metal gate 105 has an upwardly convex structure relative to the outside of the metal gate 105, the high-resistivity 107 can be avoided from being located in a recessed area, thereby ensuring the length of the high-resistivity 107. At least a portion of the periphery of the shallow trench isolation 102 at the bottom of the high resistor 107 has the pseudo-active region. There is a first lateral spacing between the high resistor 107 and the adjacent pseudo-active region. The first lateral spacing is used to adjust the pattern density of the pseudo-active region. The smaller the first lateral spacing, the greater the pattern density of the pseudo-active region. The second thickness d2 is used to adjust the second longitudinal spacing between the high resistor 107 and the adjacent pseudo-active region. Under the condition that the first lateral spacing does not increase, the second longitudinal spacing is increased by increasing the second thickness d2, so that the minimum spacing l1 between the high resistor 107 and the adjacent pseudo-active region meets the withstand voltage requirement.

[0074] like Figure 3 As shown, a second interlayer membrane 106b is formed by stacking the first interlayer membrane 106a and the second interlayer membrane 106b; the second interlayer membrane 106b covers the high resistance 107, and outside the high resistance 107, the second interlayer membrane 106b has a third thickness d3, and the first thickness d1 is the sum of the second thickness d2 and the third thickness d3; the first thickness d1 satisfies the process requirements for forming a contact hole through the interlayer membrane 106.

[0075] The following also includes: A contact hole is formed; the contact hole opening is formed by etching, followed by metal filling, and the metal filling the contact hole opening constitutes the contact hole. Each of the high resistance 107 has a strip-shaped structure, and the contact hole includes a first contact hole 108a located at both ends of the high resistance 107, the first contact hole 108a passing through the second interlayer membrane 106b.

[0076] The method in this embodiment of the invention also includes a substrate lead-out region 104.

[0077] The substrate lead-out region 104 has a ring structure, and each of the high-resistance regions 107 is located inside the ring region of the substrate lead-out region 104. The semiconductor substrate 101 is doped with a second conductivity type, the substrate lead-out region 104 is heavily doped with a second conductivity type, and a second contact hole 108b is formed at the top of the substrate lead-out region 104, penetrating the interlayer film 106.

[0078] The high-resistivity region is located outside the device cell region. In the device cell region, the metal gate 105 is formed on the surface of the semiconductor substrate 101, and a third contact hole 108c is formed on the top of the metal gate 105, passing through the interlayer film 106.

[0079] The present invention has been described in detail above through specific embodiments, but these are not intended to limit the invention. Many modifications and improvements can be made by those skilled in the art without departing from the principles of the invention, and these should also be considered within the scope of protection of the present invention.

Claims

1. A structure for improving the reliability of high-resistivity regions in metal gate processes, characterized in that, The structure of the high-resistivity region includes: Multiple shallow trench isolations formed in a semiconductor substrate and multiple pseudo-active regions located between the shallow trench isolations; a metal gate is formed on top of a portion of the shallow trench isolations and a high-resistivity TiN layer is formed on top of the metal gate; At least a portion of the periphery of the shallow trench isolation at the bottom of the high resistance has the pseudo-active region. There is a first lateral spacing between the high resistance and the adjacent pseudo-active region. The smaller the first lateral spacing, the greater the pattern density of the pseudo-active region and the larger the area ratio of the pseudo-active region and the shallow trench isolation in each region of the high resistance. The area ratio of the pseudo-active region and the shallow trench isolation must ensure that the height and uniformity of the shallow trench isolation meet the requirements. An interlayer membrane covers the top of each of the shallow trench isolations and each of the pseudo-active regions; the interlayer membrane has a first thickness; on the top of the shallow trench isolations where the high resistance is formed, the interlayer membrane is divided into a first interlayer sub-membrane and a second interlayer sub-membrane; The first interlayer membrane covers the metal grid, and outside the metal grid, the first interlayer membrane has a second thickness; The second interlayer membrane covers the high resistance, and outside the high resistance, the second interlayer membrane has a third thickness, the first thickness being the sum of the second thickness and the third thickness; the first thickness satisfies the process requirements for forming contact holes through the interlayer membrane; The second thickness is used to adjust the second longitudinal spacing between the high resistance and the adjacent pseudo-active region. Under the condition that the first lateral spacing does not increase, the second longitudinal spacing is increased by increasing the second thickness, so that the minimum spacing between the high resistance and the adjacent pseudo-active region meets the withstand voltage requirement.

2. The structure for improving the reliability of high-resistivity regions in metal gate processes as described in claim 1, characterized in that: Each of the high-resistivity components has a strip-shaped structure, and a first contact hole passing through the second interlayer membrane is formed at each end of the high-resistivity component.

3. The structure for improving the reliability of the high-resistivity region in metal gate processing as described in claim 2, characterized in that, Also includes: Substrate lead-out area; The substrate lead-out area has a ring structure, and each of the high resistances is located inside the ring region of the substrate lead-out area; The semiconductor substrate is doped with a second conductivity type, the substrate lead-out region is heavily doped with a second conductivity type, and a second contact hole is formed at the top of the substrate lead-out region, penetrating the interlayer film.

4. The structure for improving the reliability of high-resistivity regions in metal gate processes as described in claim 1, characterized in that: A gate dielectric layer is also formed at the bottom of the metal gate.

5. The structure for improving the reliability of the high-resistivity region in metal gate processing as described in claim 4, characterized in that: The material of the gate dielectric layer includes a high dielectric constant material.

6. The structure for improving the reliability of the high-resistivity region in metal gate processing as described in claim 2, characterized in that: The high resistance is located directly above the metal gate, and the high resistance also extends to the outside of the metal gate.

7. The structure for improving the reliability of high-resistivity regions in metal gate processes as described in claim 2, characterized in that: The high-resistivity region is located outside the device cell region. In the device cell region, the metal gate is formed on the surface of the semiconductor substrate, and a third contact hole is formed on the top of the metal gate, passing through the interlayer film.

8. A method for improving the reliability of high-resistivity regions in metal gate processes, characterized in that, Includes the following steps: Shallow trench isolation is formed in the semiconductor substrate, and the semiconductor substrate surrounded by the shallow trench isolation constitutes an active region; in the high-resistivity region, the active region between the shallow trench isolations is a pseudo-active region; The shallow trench isolation is formed by etching and filling shallow trenches and chemical mechanical polishing; in the high-resistivity region, the pseudo-active region is used to adjust the pattern density in the high-resistivity region. The greater the pattern density of the pseudo-active region, the greater the area ratio of the pseudo-active region and the shallow trench isolation in each region of the high-resistivity region. The area ratio of the pseudo-active region and the shallow trench isolation meets the chemical mechanical polishing load requirements and thus ensures that the height and uniformity of the shallow trench isolation meet the requirements. Form a metal grid; In the high-resistivity region, the metal gate is formed on the surface of the shallow trench isolation that forms a high-resistivity layer on top; A first interphase membrane is formed, which covers the top of each of the shallow trench isolations and each of the pseudo-active regions and covers the metal gate; the first interphase membrane has a second thickness outside the metal gate; A high-resistance layer composed of TiN is formed, the high-resistance layer being located on top of the corresponding metal gate; at least a portion of the periphery isolated by the shallow trench at the bottom of the high-resistance layer has the pseudo-active region; a first lateral spacing is provided between the high-resistance layer and the adjacent pseudo-active region, the first lateral spacing being used to adjust the pattern density of the pseudo-active region, the smaller the first lateral spacing, the greater the pattern density of the pseudo-active region; a second thickness is used to adjust the second longitudinal spacing between the high-resistance layer and the adjacent pseudo-active region, the second longitudinal spacing being increased by increasing the second thickness while ensuring that the first lateral spacing does not increase, thereby making the minimum spacing between the high-resistance layer and the adjacent pseudo-active region meet the withstand voltage requirement; A second interlayer membrane is formed by stacking the first and second interlayer membranes; the second interlayer membrane covers the high resistance, and outside the high resistance, the second interlayer membrane has a third thickness, the first thickness being the sum of the second thickness and the third thickness; the first thickness satisfies the process requirements for forming a contact hole through the interlayer membrane.

9. The method for improving the reliability of high-resistivity regions in metal gate processes as described in claim 8, characterized in that, The following also includes: A contact hole is formed; each of the high resistances is in the form of a strip structure, and the contact hole includes a first contact hole located at both ends of the high resistance, the first contact hole passing through the second interlayer membrane.

10. The method for improving the reliability of high-resistivity regions in metal gate processes as described in claim 10, characterized in that, Also includes: Substrate lead-out area; The substrate lead-out area has a ring structure, and each of the high resistances is located inside the ring region of the substrate lead-out area; The semiconductor substrate is doped with a second conductivity type, the substrate lead-out region is heavily doped with a second conductivity type, and a second contact hole is formed at the top of the substrate lead-out region, penetrating the interlayer film.

11. The method for improving the reliability of high-resistivity regions in metal gate processes as described in claim 8, characterized in that: A gate dielectric layer is also formed at the bottom of the metal gate.

12. The method for improving the reliability of high-resistivity regions in metal gate processes as described in claim 11, characterized in that: The material of the gate dielectric layer includes a high dielectric constant material.

13. The method for improving the reliability of high-resistivity regions in metal gate processes as described in claim 9, characterized in that: The high resistance is located directly above the metal gate, and the high resistance also extends to the outside of the metal gate.

14. The method for improving the reliability of high-resistivity regions in metal gate processes as described in claim 9, characterized in that: The high-resistivity region is located outside the device cell region. In the device cell region, the metal gate is formed on the surface of the semiconductor substrate, and a third contact hole is formed on the top of the metal gate, passing through the interlayer film.

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