A microstrip line impedance matching method and via structure

Abstract

This invention discloses a microstrip line impedance matching method and via structure. The microstrip line impedance matching method includes the following steps: when the impedance at the via is too high, the parasitic inductance is reduced by widening the transmission line at the via, and the capacitance is increased by increasing the reference ground below the corresponding transmission line at the via, thus reducing the impedance. The via structure includes a signal via, a first transmission line, a second transmission line, and four reference layers are provided in the insulating dielectric layer. Each reference layer has an anti-pad. The signal via connects to the three upper reference layers and is located at the center of each anti-pad. The diameter of the signal via and each anti-pad is provided with a pad. The signal via connects to the first transmission line, which has a first line segment with a linewidth larger than the diameter of the signal via. The second transmission line connects to the lowermost anti-pad. This via structure, using the above method, can achieve impedance matching at the via, effectively improving signal integrity problems caused by via impedance mismatch.

Description

Technical Field

[0001] This invention belongs to the field of PCB technology, specifically relating to a microstrip line impedance matching method and via structure. Background Technology

[0002] Currently, in high-speed, high-frequency PCB design, vias are a key structure for achieving electrical connections between different signal layers. However, traditional vias (such as through-holes, blind vias, and buried vias) introduce a series of signal integrity problems. The copper pillars, pads, and anti-pad structures at the via location generate parasitic inductance and capacitance, altering the characteristic impedance of the transmission line, causing signal reflection, degrading signal quality, filtering out high-frequency components, causing signal rise time degradation, and increasing propagation delay. Existing solutions include back-drilling, adjusting anti-pad size, and adjusting pad size, but these have limitations for transmitting high-frequency, high-speed signals. The limitations and shortcomings of the aforementioned existing technologies, and the reasons for these shortcomings, are discussed below. Back drilling: can reduce the impact of residual piles in the hole, but back drilling technology is costly, inefficient, and has alignment accuracy problems, which may result in insufficient drilling depth or over-drilling, and cannot solve the impedance problem of the hole body and connection. Adjusting the antipad size: For example, when the impedance at the via is too low, increasing the antipad size can only reduce the capacitance to a certain extent to increase the impedance. High-frequency return current tends to flow on the reference plane below the signal line. A large antipad will force the return current to take a longer route, increasing the return loop area, which may cause signal distortion.

[0003] Adjusting pad size: For example, when the impedance at the via is too low, reducing the pad size can only reduce the capacitance to a certain extent to increase the impedance, but smaller pads require higher drilling accuracy and alignment accuracy; The aforementioned existing technologies are insufficient to effectively improve via impedance continuity without significantly increasing costs and process complexity.

[0004] Therefore, a new technology is needed to address the problems of high cost and complex processes in improving via impedance continuity in existing technologies. Summary of the Invention

[0005] To address the aforementioned problems in the prior art, this invention provides a microstrip line impedance matching method and via structure, which can effectively improve via impedance continuity without increasing cost or process complexity.

[0006] The present invention adopts the following technical solution: A microstrip line impedance matching method includes the following steps: when the impedance at a via is too high, the parasitic inductance is reduced by widening the transmission line width at the via, and the capacitance is increased by increasing the reference ground under the corresponding transmission line at the via, thereby reducing the impedance and achieving impedance matching at the via. The characteristic impedance Z0 = . A via structure for high-frequency, high-speed signals is disposed on a multilayer board with transmission lines covering an insulating dielectric layer on the top and bottom. It employs the microstrip line impedance matching method described above. The via includes signal vias. Four reference layers are arranged from top to bottom in the insulating dielectric layer. Each reference layer has an anti-pad. The signal via passes through the insulating dielectric layer and connects to the three reference layers located above it. The signal via is located at the center of each anti-pad. A pad is provided at the connection node between the signal via and each anti-pad. A first transmission line and a second transmission line are provided on the insulating dielectric layer. The signal via connects to the first transmission line. The first transmission line has a first segment, the linewidth of which is larger than the diameter of the signal via. The second transmission line also has a second segment, which connects to the bottommost anti-pad.

[0007] As a further improvement to the technical solution of the present invention, the four reference layers are arranged from top to bottom as a first reference layer, a second reference layer, a third reference layer and a fourth reference layer. The first reference layer is provided with a coaxial first anti-pad and a first pad. The second reference layer is provided with a coaxial second anti-pad and a second pad. The third reference layer is provided with a coaxial third anti-pad and a third pad. The fourth reference layer is provided with a fourth anti-pad. The signal via passes through the insulating dielectric layer and sequentially passes through the first anti-pad, the second anti-pad, and the third anti-pad from top to bottom, and is coaxially arranged with each of the anti-pads.

[0008] As a further improvement to the technical solution of the present invention, the first transmission line is located on the third reference layer, the width of the first line segment is smaller than the diameter of the third anti-pad and the diameter of the third pad, and the diameter of the third anti-pad is larger than the diameter of the third pad.

[0009] As a further improvement to the technical solution of the present invention, the first line segment is located at the end of the first transmission line, and the width of the first line segment is greater than the width of the main body of the first transmission line.

[0010] As a further improvement to the technical solution of the present invention, the diameter of the second anti-solder pad is larger than that of the second solder pad.

[0011] As a further improvement to the technical solution of the present invention, the diameter of the first anti-pad is larger than the diameter of the first pad, and the diameter of the first pad is larger than the diameter of the second pad.

[0012] As a further improvement to the technical solution of the present invention, the second transmission line is located on the fourth reference layer, and the end of the second transmission line is provided with a second line segment. The second line segment is connected to the fourth anti-pad and its width is smaller than the diameter of the fourth anti-pad.

[0013] Compared with the prior art, the beneficial effects of the present invention are as follows: This solution reduces parasitic inductance by widening the transmission line width at the via and increases capacitance by adding a reference ground under the transmission line at the via, thus achieving impedance matching at the via and effectively improving signal integrity issues caused by via impedance mismatch. Attached Figure Description

[0014] The technology of the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments: Figure 1 This is a schematic diagram of the via structure of the present invention.

[0015] Figure label: 1-First reference layer; 11-First anti-pad; 12-First pad; 2-Second reference layer; 21-Second anti-pad; 22-Second pad; 3-Third reference layer; 31-Third anti-pad; 32-Third pad; 4 - Fourth reference layer; 41 - Fourth anti-pad; 5-Signal via; 6-First transmission line; 61-First line segment; 7-Second transmission line; 71-Second segment. Detailed Implementation

[0016] The following will provide a clear and complete description of the concept, specific structure, and technical effects of the present invention in conjunction with embodiments and accompanying drawings, so as to fully understand the purpose, solution, and effects of the present invention. It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. The same reference numerals used throughout the accompanying drawings indicate the same or similar parts.

[0017] It should be noted that, unless otherwise specified, when a feature is referred to as "fixed" or "connected" to another feature, it can be directly fixed or connected to the other feature, or indirectly fixed or connected to the other feature. Furthermore, the descriptions of "up," "down," "left," and "right" used in this invention are only relative to the relative positional relationships of the various components of the invention in the accompanying drawings.

[0018] Reference Figure 1A microstrip line impedance matching method includes the following steps: when the impedance at a via is too high, the parasitic inductance is reduced by widening the transmission line width at the via, and the capacitance is increased by increasing the reference ground under the corresponding transmission line at the via, thereby reducing the impedance and achieving impedance matching at the via. The characteristic impedance Z0 = . Reference Figure 1 A via structure for high-frequency, high-speed signals is disposed on a multilayer board with transmission lines covering an insulating dielectric layer on the top and bottom. It employs the microstrip line impedance matching method described above. The structure includes a signal via 5. Four reference layers are arranged from top to bottom in the insulating dielectric layer. A reference ground is added below the transmission line corresponding to the via 5, which can increase capacitance and reduce impedance. Each reference layer has an anti-pad. The signal via 5 passes through the insulating dielectric layer and connects to the three reference layers above it. The signal via 5 is located at the center of each anti-pad. A pad is provided at the connection node between the signal via 5 and each anti-pad. A first transmission line 6 and a second transmission line 7 are provided on the insulating dielectric layer. The signal via 5 connects to the first transmission line 6. The first transmission line 6 has a first segment 61, the linewidth of which is larger than the diameter of the signal via 5. The second transmission line 7 also has a second segment 71, which connects to the bottommost anti-pad. When the impedance at the via is too high, and conventional impedance adjustment methods, even at their limits, cannot achieve impedance matching, the parasitic inductance is reduced by widening the transmission line width at the via, and the capacitance is increased by adding a reference ground beneath the corresponding transmission line at the via. This lowers the impedance and achieves impedance matching at the via. The structure is simple and can effectively improve the impedance continuity of vias without significantly increasing cost or manufacturing complexity. The characteristic impedance Z0 = .

[0019] Specifically, the four reference layers are, from top to bottom, a first reference layer 1, a second reference layer 2, a third reference layer 3, and a fourth reference layer 4. The first reference layer 1 has coaxial first anti-pad 11 and first pad 12; the second reference layer 2 has coaxial second anti-pad 21 and second pad 22; the third reference layer 3 has coaxial third anti-pad 31 and third pad 32; and the fourth reference layer 4 has a fourth anti-pad 41. The signal via 5 passes through the insulating dielectric layer, sequentially passing through the first anti-pad 11, the second anti-pad 21, and the third anti-pad 31 from top to bottom, and is coaxially arranged with each anti-pad.

[0020] Specifically, the first transmission line 6 is located on the third reference layer 3, the width of the first line segment 61 is smaller than the diameter of the third anti-pad 31 and the diameter of the third pad 32, and the diameter of the third anti-pad 31 is larger than the diameter of the third pad 32.

[0021] Specifically, the first line segment 61 is located at the end of the first transmission line 6, and the width of the first line segment 61 is greater than the width of the main body of the first transmission line 6. When the impedance at via 5 is too high, other conventional methods cannot solve the problem of high impedance. By widening the line width of the first line segment 61 at via 5, the parasitic inductance is reduced. In addition, this solution also adds a reference ground under the corresponding transmission line at via 5 to increase capacitance, thereby reducing impedance and achieving impedance matching at via 5. This can effectively improve the signal integrity problem caused by impedance mismatch at via 5. Furthermore, the via structure and manufacturing process optimized by this solution are simple and have low manufacturing costs.

[0022] Specifically, the diameter of the second anti-pad 21 is larger than that of the second pad 22, the diameter of the first anti-pad 11 is larger than that of the first pad 12, and the diameter of the first pad 12 is larger than that of the second pad 22. All anti-pads have the same diameter.

[0023] Specifically, the second transmission line 7 is located on the fourth reference layer 4, and the end of the second transmission line 7 is provided with a second line segment 71. The second line segment 71 is connected to the fourth anti-pad 41 and its width is smaller than the diameter of the fourth anti-pad 41.

[0024] When conventional solutions fail to address impedance matching issues, the high-frequency, high-speed signal via structure described in this solution can be used. By widening the transmission line width at via 5 and increasing the corresponding reference ground at via 5, the impedance matching problem of the via can be effectively improved.

[0025] Other aspects of the microstrip line impedance matching method and via structure described in this invention can be found in the prior art and will not be repeated here.

[0026] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention in any way. Therefore, any modifications, equivalent changes, and alterations made to the above embodiments based on the technical essence of the present invention without departing from the scope of the present invention shall still fall within the scope of the present invention.

Claims

1. A microstrip line impedance matching method, characterized in that: Includes the following steps: When the impedance at a via is too high, the parasitic inductance is reduced by widening the transmission line width at the via, and the capacitance is increased by increasing the reference ground under the corresponding transmission line at the via, thus lowering the impedance and achieving impedance matching at the via. The characteristic impedance Z0 = .

2. A via structure for high-frequency, high-speed signals, disposed on a multilayer board with transmission lines covering an insulating dielectric layer on both sides, employing the microstrip line impedance matching method as described in claim 1, characterized in that: The device includes signal vias. Four reference layers are arranged from top to bottom within an insulating dielectric layer. Each reference layer has an anti-pad. The signal vias pass through the insulating dielectric layer and connect to the three reference layers located above. The signal vias are located at the center of each anti-pad. A pad is provided at the connection point between the signal via and each anti-pad. A first transmission line and a second transmission line are provided on the insulating dielectric layer. The signal vias connect to the first transmission line. The first transmission line has a first segment, the linewidth of which is greater than the diameter of the signal via. The second transmission line also has a second segment, which connects to the lowest anti-pad.

3. The via structure for high-frequency, high-speed signals according to claim 2, characterized in that: The four reference layers are, from top to bottom, a first reference layer, a second reference layer, a third reference layer, and a fourth reference layer. The first reference layer has a coaxial first anti-pad and a first pad. The second reference layer has a coaxial second anti-pad and a second pad. The third reference layer has a coaxial third anti-pad and a third pad. The fourth reference layer has a fourth anti-pad. The signal via passes through the insulating dielectric layer and sequentially passes through the first anti-pad, the second anti-pad, and the third anti-pad from top to bottom, and is coaxially arranged with each of the anti-pads.

4. The via structure for high-frequency, high-speed signals according to claim 3, characterized in that: The first transmission line is located on the third reference layer. The width of the first line segment is smaller than the diameter of the third anti-pad and the diameter of the third pad. The diameter of the third anti-pad is larger than the diameter of the third pad.

5. The via structure for high-frequency, high-speed signals according to claim 4, characterized in that: The first line segment is located at the end of the first transmission line, and the width of the first line segment is greater than the width of the main body of the first transmission line.

6. The via structure for high-frequency, high-speed signals according to claim 5, characterized in that: The second anti-pad is larger than the diameter of the second pad.

7. The via structure for high-frequency, high-speed signals according to claim 6, characterized in that: The diameter of the first anti-pad is larger than the diameter of the first pad, and the diameter of the first pad is larger than the diameter of the second pad.

8. The via structure for high-frequency, high-speed signals according to claim 5, characterized in that: The second transmission line is located on the fourth reference layer, and the end of the second transmission line is provided with a second line segment. The second line segment is connected to the fourth anti-pad and its width is smaller than the diameter of the fourth anti-pad.

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