A hardware acceleration method, device and medium supporting mapping table compression

Abstract

The application discloses a hardware acceleration method and device supporting mapping table compression and a medium, and relates to the technical field of SSDs.The method comprises the following steps: if a read request is received, a target mapping shard index is determined according to a target logical address; a two-level mapping table in a resident memory is queried according to the target mapping shard index, and a corresponding target table item is obtained, wherein the target table item comprises a position indication field and an address field; if the value of the position indication field is a first value, it is indicated that the mapping shard is stored in a one-level mapping table cache in a non-compressed format, and the physical address corresponding to the target logical address is read from the one-level mapping table cache according to the address field; if the value of the position indication field is a second value, it is indicated that the mapping shard is stored in a compressed node in a compressed format, compressed mapping data is obtained from the compressed node according to the address field, and the corresponding physical address is calculated in combination with the target logical address; and the physical address is submitted to a read-write processing module to initiate data access.The application is compatible with linear mapping and compressed mapping hardware acceleration.

Description

Technical Field

[0001] This invention relates to the field of SSD technology, and in particular to a hardware acceleration method, device, and medium that supports mapping table compression. Background Technology

[0002] In NAND storage devices, due to memory capacity limitations, a two-level mapping strategy is typically used to manage the translation from logical addresses to physical addresses. The first-level mapping table records the storage location of user data; its large size prevents it from residing permanently in memory, so only a portion of it is cached in memory. The second-level mapping table tracks the storage location of these first-level mapped fragments within the NAND; its smaller size allows it to reside permanently in memory. The hardware acceleration engine queries the second-level mapping table; if the required first-level mapped fragment is already cached in memory, it can directly obtain the corresponding physical address, significantly reducing software processing overhead.

[0003] However, to further reduce memory overhead, existing technologies have introduced a mapping compression mechanism, which uses a starting logical address, a starting physical address, and a consecutive number of triples to describe contiguous address mappings, replacing traditional linear mapping entries. However, this compressed mapping representation is incompatible with the original linear cache structure, causing hardware acceleration engines to be unable to recognize and parse it, thus preventing accelerated access to compressed mappings. Summary of the Invention

[0004] This invention provides a hardware acceleration method, device, and medium that supports mapping table compression. The technical problem it aims to solve is: how to provide a hardware acceleration solution that is compatible with both linear mapping and compressed mapping.

[0005] In a first aspect, embodiments of the present invention provide a hardware acceleration method supporting mapping table compression, applied to a hardware acceleration engine, comprising: If a read request for a target logical address is received, the corresponding target mapping shard index is determined based on the target logical address; The target table entry corresponding to the target mapping shard index is obtained by querying the resident secondary mapping table according to the target mapping shard index. The target table entry includes a location indication field and an address field. If the value of the location indication field is a preset first value, then the physical address corresponding to the target logical address is read from the first-level mapping table cache according to the address field; wherein, the preset first value is used to indicate that the mapping shard corresponding to the target mapping shard index is stored in the first-level mapping table cache in an uncompressed format; If the value of the location indication field is a preset second value, then compressed mapping data is obtained from the compressed node according to the address field, and the physical address corresponding to the target logical address is calculated according to the compressed mapping data and the target logical address; wherein, the preset second value is used to indicate that the mapping fragment corresponding to the target mapping fragment index is stored in the compressed node in a compressed format; The physical address is submitted to the read / write processing module to initiate access to user data.

[0006] Optionally, each entry in the secondary mapping table includes the location indication field and the address field; wherein, when the value of the location indication field is a preset first value, the address field points to the cache unit in the primary mapping table cache that stores the mapping fragment; when the value of the location indication field is a preset second value, the address field points to the compression node that stores the compressed mapping data; when the value of the location indication field is a preset third value, the address field points to the storage address of the mapping fragment in the NAND, and the preset third value is used to indicate that the mapping fragment is not loaded into memory and is stored in the NAND.

[0007] Optionally, reading the physical address corresponding to the target logical address from the first-level mapping table cache based on the address field includes: The target cache unit in the first-level mapping table cache is determined based on the address field; Based on the offset of the target logical address within the target mapping segment, the physical address corresponding to the offset is read from the target cache unit.

[0008] Optionally, the step of obtaining compression mapping data from the compression node based on the address field, and calculating the physical address corresponding to the target logical address based on the compression mapping data and the target logical address, includes: The target compression node is determined based on the address field; Read compression mapping data from the target compression node, the compression mapping data including the starting logical address, the starting physical address, and the number of consecutive elements; The physical address corresponding to the target logical address is calculated based on the difference between the target logical address and the starting logical address, and the starting physical address.

[0009] Optionally, it also includes: If the value of the location indication field is a preset third value, then the mapping fragment corresponding to the target mapping fragment index is loaded from the NAND according to the address field; Determine whether the loaded mapping fragments meet the preset compression conditions; If the compression conditions are met, a compression node is allocated from the preset list of idle compression nodes. The mapped fragment is converted into compressed mapping data and stored in the allocated compression node. The target entry is updated to: the location indication field is set to the preset second value, and the address field points to the allocated compression node. If the compression conditions are not met, a cache unit is allocated from the first-level mapping table cache, the mapping fragment is stored in the allocated cache unit, and the target table entry is updated to: the location indication field is set to the preset first value, and the address field points to the allocated cache unit.

[0010] Optionally, the system may further include: during the system initialization phase, constructing the first-level mapping table cache, the second-level mapping table, the compressed node list, and the idle compressed node list in memory; wherein the compressed node list is used to store allocated compressed nodes, and the idle compressed node list is used to store unallocated compressed nodes.

[0011] Optionally, the read request is initiated by the host. Before receiving the read request for the target logical address, the read request is divided into at least one logical address according to a preset mapping unit size by the command preprocessing acceleration engine. The at least one logical address includes the target logical address.

[0012] Optionally, it also includes: If a write request for the target logical address is received, the write request is submitted to the read / write processing module to initiate the writing of user data.

[0013] Secondly, embodiments of the present invention also provide a computer device, which includes a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the above-described method.

[0014] Thirdly, embodiments of the present invention also provide a computer-readable storage medium storing a computer program that, when executed by a processor, can implement the above-described method.

[0015] This invention provides a hardware acceleration method, device, and medium supporting mapping table compression. The method includes: upon receiving a read request for a target logical address, determining a corresponding target mapping shard index based on the target logical address; querying a resident secondary mapping table based on the target mapping shard index to obtain a target table entry corresponding to the target mapping shard index, the target table entry including a location indicator field and an address field; if the value of the location indicator field is a preset first value, reading the physical address corresponding to the target logical address from a primary mapping table cache based on the address field; wherein the preset first value is used to instruct the mapping shard corresponding to the target mapping shard index to be stored in the primary mapping table cache in an uncompressed format; if the value of the location indicator field is a preset second value, obtaining compressed mapping data from a compression node based on the address field, and calculating the physical address corresponding to the target logical address based on the compressed mapping data and the target logical address; wherein the preset second value is used to instruct the mapping shard corresponding to the target mapping shard index to be stored in a compressed format in the compression node; and submitting the physical address to a read / write processing module to initiate access to user data. This invention enables the hardware acceleration path to accurately distinguish between the two storage formats of mapped fragments in memory by defining preset first and second values ​​in the location indicator field of the secondary mapping table. When the location indicator field is the preset first value, the hardware directly reads the physical address from the primary mapping table cache, maintaining the efficiency of traditional linear access. When the location indicator field is the preset second value, the hardware recognizes that the mapped fragment is stored in a compressed format and calculates the physical address by performing arithmetic operations on the triple data obtained from the compressed node, avoiding the additional overhead of leaving compressed mapping to software processing. Therefore, regardless of whether the mapped fragment exists in memory in an uncompressed or compressed format, the hardware acceleration engine can effectively process it, significantly expanding the coverage of hardware acceleration. For devices with limited memory resources, the memory savings brought by compressed mapping can be directly converted into accelerated access hit rates, thereby improving the random read performance of the device. Attached Figure Description

[0016] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the following description of the embodiments will be briefly introduced. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 A flowchart illustrating a hardware acceleration method supporting mapping table compression provided in an embodiment of the present invention; Figure 2This is a schematic block diagram of a computer device provided in an embodiment of the present invention. Detailed Implementation

[0018] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0019] It should be understood that, when used in this specification and the appended claims, the terms "comprising" and "including" indicate the presence of the described features, integrals, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components and / or collections thereof.

[0020] It should also be understood that the terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to limit the invention. As used in this specification and the appended claims, the singular forms “a,” “an,” and “the” are intended to include the plural forms unless the context clearly indicates otherwise.

[0021] It should also be further understood that the term "and / or" as used in this specification and the appended claims refers to any combination of one or more of the associated listed items and all possible combinations, and includes such combinations.

[0022] As used in this specification and the appended claims, the term "if" may be interpreted, depending on the context, as "when," "once," "in response to determination," or "in response to detection." Similarly, the phrase "if determined" or "if [described condition or event] is detected" may be interpreted, depending on the context, as "once determined," "in response to determination," "once [described condition or event] is detected," or "in response to detection of [described condition or event]."

[0023] Please see Figure 1 This invention provides a hardware acceleration method for supporting mapping table compression, applied to a hardware acceleration engine. The method includes the following steps: S1, if a read request for a target logical address is received, determine the corresponding target mapping shard index based on the target logical address.

[0024] In practice, in response to a read request targeting a logical address, the corresponding target mapping shard index is determined based on the logical address. Specifically, the read command initiated by the host includes the starting logical address and the length of data to be read. The logical address is a number in the linear address space used by the host to access the storage device, and each logical address corresponds to a minimum access unit of data.

[0025] Furthermore, the command preprocessing unit divides the read command into the smallest access unit and generates a series of independent read requests. Each read request corresponds to a logical address, which is the target logical address.

[0026] Furthermore, in NAND storage devices, the mapping table is divided into multiple fixed-size shards for management. Each shard is called a mapping shard, covering a continuous logical address range. The mapping shard index is a number used to uniquely identify each mapping shard.

[0027] Furthermore, based on the predefined mapping relationship, the target logical address is divided by the number of logical addresses contained in each mapping fragment, and the quotient is rounded down to obtain the target mapping fragment index. This target mapping fragment index is used to locate the corresponding entry in the secondary mapping table in subsequent steps.

[0028] S2, query the resident secondary mapping table according to the target mapping shard index to obtain the target table entry corresponding to the target mapping shard index. The target table entry includes a location indication field and an address field.

[0029] In practice, the target mapping shard index is used to query the resident secondary mapping table to obtain the target table entry corresponding to the target mapping shard index. The secondary mapping table is a data structure resident in memory, whose function is to track the current storage location and storage format of each mapping shard. The secondary mapping table is organized as an array, where the array index is the mapping shard index, and each element of the array is a table entry, with each table entry corresponding to a mapping shard index.

[0030] Furthermore, by using the target mapping shard index as the array subscript, the target table entry corresponding to that index can be directly accessed. This target table entry contains at least two fields: a location indicator field and an address field. The location indicator field encodes information representing the current storage state of the corresponding mapping shard, while the address field provides the location information required to access the mapping shard, such as its index in memory or its physical address in NAND.

[0031] In some preferred embodiments, each entry of the secondary mapping table includes the location indication field and the address field; wherein, when the value of the location indication field is a preset first value, the address field points to the cache unit in the primary mapping table cache that stores the mapping fragment; when the value of the location indication field is a preset second value, the address field points to the compression node that stores the compressed mapping data; when the value of the location indication field is a preset third value, the address field points to the storage address of the mapping fragment in the NAND, and the preset third value is used to indicate that the mapping fragment is not loaded into memory and is stored in the NAND.

[0032] In practice, the secondary mapping table is designed as a resident memory data structure. Its core function is to provide a status record and location entry for each mapping shard index. Each mapping shard index corresponds to a unique table entry, which consists of a location indicator field and an address field. The location indicator field uses a multi-value encoding method, with different preset values ​​representing the three different states of the corresponding mapping shard. The content of the address field is assigned different interpretations based on the value of the location indicator field, together forming a complete unit of location information.

[0033] Furthermore, when the location indicator field has a preset first value, this value has a specific semantic meaning, indicating that the corresponding mapped slice has been read from the NAND flash memory through a certain loading mechanism and stored in the first-level mapping table cache in memory in its uncompressed raw format. Uncompressed format means listing the correspondence between all logical addresses and physical addresses within the mapped slice, forming a linear array. At this point, the address field is interpreted as an index or pointer to a specific cache unit in the first-level mapping table cache. Each cache unit in the first-level mapping table cache has a fixed size, just large enough to hold a complete uncompressed mapped slice. Using this index or pointer, the specific cache location storing the mapped slice can be located in constant time, thus providing a basis for subsequent physical address readings.

[0034] Furthermore, when the location indicator field has a preset second value, this value carries another semantic meaning: it indicates that the corresponding mapped fragment has also been loaded into memory, but after verification, it meets the compression conditions and is therefore converted to a compressed format for storage. The compressed format refers to summarizing the address mapping relationships that would otherwise need to be listed one by one using three values: the starting logical address, the starting physical address, and the number of consecutive elements. In this case, the address field is interpreted as an index or pointer to a compressed node. A compressed node is a data structure in memory specifically used to store these triples; each compressed node corresponds to a compressed mapped fragment. Compressed nodes are organized in a list, and this index or pointer uniquely identifies a compressed node, from which compressed mapping data is read for subsequent address calculations.

[0035] Furthermore, when the location indicator field has a preset third value, this value has a third semantic meaning, indicating that the corresponding mapped slice is not currently residing in memory, and its complete content is still stored in the mapped storage area of ​​the NAND flash memory. The mapped storage area is a region in the NAND specifically allocated for storing a complete mapping table backup. At this time, the address field is interpreted as pointing to the physical address in the NAND where the mapped slice is stored. This physical address is usually encoded in the form of blocks and pages, and is used by the firmware to initiate a NAND read operation when the mapped slice needs to be loaded, moving the data from the NAND to memory.

[0036] In this embodiment of the invention, through the above definition, each entry in the secondary mapping table forms a complete, self-describing state record unit. When the hardware acceleration engine queries the secondary mapping table, it only needs to read the value of the location indicator field to determine whether the current mapped fragment is in a non-compressed memory state, a compressed memory state, or a NAND unloaded state, and correctly interpret and use the content of the address field based on this state. This design makes the secondary mapping table the information hub of the entire mapping management system, providing the hardware acceleration engine with a unified and clear query interface, and also providing accurate basis for firmware to perform mapping loading and state transitions.

[0037] S3, if the value of the location indication field is a preset first value, then the physical address corresponding to the target logical address is read from the first-level mapping table cache according to the address field; wherein, the preset first value is used to indicate that the mapping shard corresponding to the target mapping shard index is stored in the first-level mapping table cache in an uncompressed format.

[0038] In practice, if the location indicator field has a preset first value, the physical address corresponding to the target logical address is read from the first-level mapping table cache based on the address field. The preset first value indicates that the mapping shard corresponding to the target mapping shard index has been loaded into memory and is stored in the first-level mapping table cache in an uncompressed linear list format.

[0039] Furthermore, the Level 1 mapping table cache is a dedicated area in memory used to store recently accessed mapping slices stored in an uncompressed format. The Level 1 mapping table cache is organized as an array of multiple cache units, each the same size as a mapping slice. Internally, it stores the physical addresses corresponding to each logical address covered by that mapping slice in a linear list. The physical address is the actual location of user data in the NAND storage medium, used for subsequent data access operations. When the address field value is a preset first value, the address field is interpreted as an index pointing to a specific cache unit in the Level 1 mapping table cache.

[0040] Furthermore, after determining the target cache unit based on the index, it is also necessary to determine the offset of the target logical address within that cache unit. This offset is obtained by calculating the difference between the target logical address and the starting address of its corresponding mapped fragment, specifically by taking the remainder of the target logical address divided by the number of logical addresses contained in each mapped fragment. Using this offset as an index, the physical address corresponding to the target logical address can be retrieved by accessing the linear table of the target cache unit.

[0041] In some preferred embodiments, the step of reading the physical address corresponding to the target logical address from the first-level mapping table cache according to the address field includes: determining the target cache unit in the first-level mapping table cache according to the address field; and reading the physical address corresponding to the offset of the target logical address in the target mapping segment from the target cache unit.

[0042] In practice, the target cache unit in the first-level mapping table cache is determined based on the address field. Specifically, when the hardware acceleration engine queries the second-level mapping table and finds that the value of the location indicator field is a preset first value, it means that the target mapping fragment is stored in the first-level mapping table cache in an uncompressed format. At this time, the address field stores an index value pointing to the first-level mapping table cache. The first-level mapping table cache is designed as an array structure, where each element of the array is called a cache unit. The size of each cache unit is fixed and equal to the data size of a mapping fragment.

[0043] For example, if each mapping segment contains 1024 logical address mappings, and each logical address corresponds to a physical address occupying four bytes, then the size of each cache unit is 4096 bytes. The index value in the address field is precisely the subscript of this array. By combining this index value with the base address of the first-level mapping table cache, the starting address of the target cache unit in memory can be calculated, thus uniquely identifying the cache unit. The input to this step is the index value in the address field, and the output is the starting address or identifier of the target cache unit.

[0044] Further, based on the offset of the target logical address within the target mapped fragment, the physical address corresponding to the offset is read from the target cache unit. Specifically, each mapped fragment covers a continuous logical address range, the size of which is a predefined fixed value, denoted as the fragment size. The target logical address belongs to the range covered by the target mapped fragment, so the offset of the target logical address within the target mapped fragment can be obtained by calculating the difference between the target logical address and the starting address of this range. The starting address of the range is calculated by multiplying the target mapped fragment index by the fragment size. The offset is calculated by subtracting the starting address of the range from the target logical address, or equivalently, by taking the remainder of the target logical address divided by the fragment size. This offset is an integer between zero and the fragment size minus one, directly corresponding to the storage location of the physical address mapped by the target logical address within the cache unit. The target cache unit stores the physical addresses corresponding to all logical addresses within the mapped fragment consecutively in ascending order of offset.

[0045] Therefore, using this offset as an index, by adding the offset multiplied by the number of bytes per physical address to the starting address of the target cache unit, the location of the target physical address in memory can be calculated, and its value can be read. The input to this step is the starting address of the target cache unit and the offset of the target logical address, and the output is the physical address that uniquely corresponds to the target logical address.

[0046] This embodiment achieves efficient access to the first-level mapping table cache by decomposing the physical address acquisition process into two steps: cache unit location and intra-chip offset indexing. The cache unit location step utilizes the index information pre-stored in the address field, which is a direct addressing method. Access is performed through array subscripts, avoiding the overhead of full search or hash lookup in the cache, ensuring that the location operation is completed in constant time. Furthermore, the intra-chip offset indexing step utilizes the linear characteristics of the data arrangement within the mapping fragment. After obtaining the offset through simple arithmetic operations, array access can be performed in constant time, also exhibiting deterministic low latency. This two-step access mechanism fully utilizes the data organization structure of the first-level mapping table cache, making the time complexity of the physical address read operation O(1), independent of the size of the cache unit. Furthermore, this mechanism clarifies the mathematical relationship between the target logical address and the target cache unit. Regardless of how the logical address range covered by the mapping fragment changes, as long as the target logical address is given, the corresponding mapping fragment index and intra-chip offset can be accurately calculated through unified division and modulo operations, ensuring the correctness and universality of the access logic.

[0047] S4, if the value of the location indication field is a preset second value, then the compressed mapping data is obtained from the compressed node according to the address field, and the physical address corresponding to the target logical address is calculated according to the compressed mapping data and the target logical address; wherein, the preset second value is used to indicate that the mapping fragment corresponding to the target mapping fragment index is stored in the compressed node in a compressed format.

[0048] In practice, if the value of the location indication field is a preset second value, then the compression mapping data is obtained from the compression node according to the address field, and the physical address corresponding to the target logical address is calculated according to the compression mapping data and the target logical address.

[0049] Furthermore, the preset second value indicates that the mapping fragment corresponding to the target mapping fragment index has been loaded into memory and is stored in a compressed format in the compressed node. A compressed node is a data structure in memory used to store compressed format mapping fragments; each compressed node stores one compressed mapping data unit. The compressed mapping data is described in the form of a triple, which includes at least the starting logical address, the starting physical address, and the number of consecutive occurrences. The starting logical address records the first logical address corresponding to this continuous mapping, the starting physical address records the physical address mapped to by this starting logical address, and the number of consecutive occurrences records how many consecutive logical addresses correspond to consecutive physical addresses starting from the starting logical address.

[0050] Furthermore, when the address field value is the preset second value, the content of the address field is interpreted as an index pointing to a specific compressed node in the compressed node list. The compressed node list is a data structure in memory used to organize all allocated compressed nodes, and the target compressed node can be uniquely identified through this index. After reading the compressed mapping data from the target compressed node, it is first determined whether the target logical address falls within a continuous interval starting from the starting logical address. If so, the difference between the target logical address and the starting logical address is calculated, and this difference is the step size of the target logical address relative to the starting position. Since the mapping relationship is continuous, the physical addresses must also be continuous. Therefore, the starting physical address is added to the above difference, and the result is the physical address corresponding to the target logical address.

[0051] In some preferred embodiments, the step of obtaining compressed mapping data from the compressed node based on the address field, and calculating the physical address corresponding to the target logical address based on the compressed mapping data and the target logical address, includes: determining the target compressed node based on the address field; reading compressed mapping data from the target compressed node, the compressed mapping data including a starting logical address, a starting physical address, and a consecutive number; and calculating the physical address corresponding to the target logical address based on the difference between the target logical address and the starting logical address, and the starting physical address.

[0052] In practice, the target compression node is determined based on the address field. Specifically, after the hardware acceleration engine queries the secondary mapping table and finds that the value of the location indicator field is a preset second value, it means that the target mapping fragment is stored in a compression node in compressed format. At this time, the address field stores an index value pointing to the compression node. The compression nodes are organized as a list, which can be in array or linked list form. Each element is a fixed-size data structure used to store a compressed mapping data unit. The index value in the address field is the key used to locate a specific element in this list. By using this index value as the list index or lookup key, a compression node can be uniquely identified; this node is the target compression node storing the compressed data of the target mapping fragment. The input to this step is the index value in the address field, and the output is the starting address or identifier of the target compression node.

[0053] Further, compressed mapping data is read from the target compressed node. This data includes the starting logical address, the starting physical address, and the number of consecutive addresses. Specifically, each compressed node stores three key fields according to a predefined format. The starting logical address field records the value of the first logical address corresponding to this consecutive mapping. The starting physical address field records the value of the physical address mapped to the starting logical address. The number of consecutive addresses records how many consecutive logical addresses correspond to consecutive physical addresses starting from the starting logical address. These three fields together form a complete triple, describing a consecutive address mapping relationship. The read operation extracts the values ​​of these three fields from the target compressed node as the basis for subsequent calculations. The input to this step is the target compressed node, and the output is compressed mapping data containing the starting logical address, the starting physical address, and the number of consecutive addresses.

[0054] Further, based on the difference between the target logical address and the starting logical address, and the starting physical address, the physical address corresponding to the target logical address is calculated. Specifically, after obtaining the compressed mapping data, a validity check is first performed to confirm whether the target logical address falls within the interval described by this compressed node. The method for this check is to examine whether the target logical address is greater than or equal to the starting logical address and less than the sum of the starting logical address and the number of consecutive addresses. If the target logical address is within this interval, the difference between the target logical address and the starting logical address is calculated. This difference represents the offset step number of the target logical address relative to the starting position. Since the premise of compressed mapping is that the logical addresses are consecutive and the corresponding physical addresses are also consecutive, starting from the starting physical address, for each additional logical address step, the physical address also increases by a fixed step size, which is usually the size of a physical page. Therefore, since the physical address itself is a linearly increasing integer, the starting physical address can be directly added to the difference, and the result is the physical address corresponding to the target logical address. For example, if the starting logical address is A, the starting physical address is B, the consecutive number is C, and the target logical address is X, and X is within the range of A to A + C - one, then the target physical address is equal to B + X - A. The input to this step is the compressed mapping data and the target logical address, and the output is the physical address corresponding to the target logical address.

[0055] This embodiment defines compressed mapping data as a triplet consisting of a starting logical address, a starting physical address, and a consecutive number of elements. It replaces linear lookup with arithmetic operations, achieving efficient parsing of the compressed mapping. This design fully leverages the inherent patterns of continuous address mapping, simplifying the calculation process by performing a single subtraction and addition operation instead of traversing or looking up information that would otherwise require table lookup. Furthermore, for hardware implementation, the arithmetic unit is a fundamental and efficient component, capable of performing subtraction and addition operations within a single clock cycle, exhibiting low latency and high determinism without introducing complex logic circuits or state machines. Moreover, this embodiment clarifies the mathematical relationship between the target logical address and the starting logical address stored in the compressed node, ensuring the correctness of the calculation result through interval judgment. Calculation is only performed when the target logical address falls within a valid interval, preventing errors caused by out-of-bounds access. Furthermore, in this way, the hardware acceleration engine can process compressed mapping with efficiency comparable to that of uncompressed mapping, ensuring that the introduction of compression technology does not negatively impact read performance, achieving a dual optimization of memory saving and access speed.

[0056] S5, submit the physical address to the read / write processing module to initiate access to user data.

[0057] In practice, the physical address is submitted to the read / write processing module to initiate access to user data. Upon receiving the physical address, the read / write processing module assembles a NAND access command based on that address, initiates a read operation on the NAND storage medium, and retrieves the user data stored at that physical address. The retrieved data is then processed and returned to the host, completing the read request.

[0058] This invention enables the hardware acceleration path to accurately distinguish between two different storage formats of mapped fragments in memory by defining preset first and second values ​​in the location indicator field of the secondary mapping table. When the location indicator field is the preset first value, the hardware can directly read the physical address from the linear secondary mapping table cache. This direct indexing method utilizes the efficient access characteristics of linear lists, with a constant time complexity for the read operation and deterministic low latency. Furthermore, when the location indicator field is the preset second value, the hardware can identify that the mapped fragment is stored in a compressed format and obtain the physical address through a dedicated calculation path by performing simple arithmetic operations based on the triplet data in the compressed node. This calculation method avoids the context switching and complex parsing overhead caused by leaving compressed mapping to software processing, making the access latency of compressed mapping on the same order of magnitude as that of uncompressed mapping. Thus, regardless of whether the mapped fragment exists in memory in an uncompressed or compressed format, the hardware acceleration engine can effectively process it, thereby significantly expanding the coverage of hardware acceleration. Furthermore, for devices with limited memory resources, the introduction of compression mapping is intended to improve memory utilization. However, if it cannot be accelerated by hardware, the resulting memory savings will be offset by the performance loss from software processing. This embodiment provides hardware-level computing capabilities for compression mapping, enabling the memory savings from compression mapping to be directly converted into accelerated access hit rates, thereby improving the device's random read performance.

[0059] In some preferred embodiments, the method further includes: if the value of the location indication field is a preset third value, then loading the mapping fragment corresponding to the target mapping fragment index from the NAND according to the address field; determining whether the loaded mapping fragment meets a preset compression condition; if the compression condition is met, then allocating a compression node from a preset list of idle compression nodes, converting the mapping fragment into compressed mapping data and storing it in the allocated compression node, and updating the target entry to: the location indication field is set to the preset second value, and the address field points to the allocated compression node; if the compression condition is not met, then allocating a cache unit from the first-level mapping table cache, storing the mapping fragment in the allocated cache unit, and updating the target entry to: the location indication field is set to the preset first value, and the address field points to the allocated cache unit.

[0060] In practice, if the location indicator field has a preset third value, the mapping fragment corresponding to the target mapping fragment index is loaded from the NAND flash memory based on the address field. Specifically, when the hardware acceleration engine queries the secondary mapping table and finds that the location indicator field has a preset third value, it indicates that the target mapping fragment is not currently residing in any cache area of ​​memory, and its complete data exists only in the mapped storage area of ​​the NAND flash memory. At this time, the address field stores the physical storage address of the mapping fragment in the NAND flash memory, which is usually composed of the target block number and the target page number. Further, the hardware acceleration engine reports this situation to the firmware mapping processing module and passes the target logical address and the NAND address obtained from the address field to the module. After receiving this information, the firmware mapping processing module constructs a read command based on the NAND address, initiates a read operation through the NAND controller, and reads the mapping fragment data stored at the specified location in the NAND flash memory into a temporary buffer in memory. The input to this step is the NAND address in the address field, and the output is the mapping fragment data loaded into the temporary buffer.

[0061] Further, it is determined whether the loaded mapping fragments meet the compression conditions. Specifically, after the mapping fragment data is successfully loaded into the memory buffer, the firmware mapping processing module scans and analyzes its contents to determine whether the address mapping relationship described by the mapping fragment has compressible characteristics. The compression condition refers to whether the physical addresses corresponding to multiple consecutive logical addresses in the mapping fragment are also arranged consecutively. The method of judgment is to traverse each entry in the mapping fragment. For several consecutive entries starting from the starting logical address, check whether their physical addresses increase sequentially with a fixed step size. Further, if within the entire mapping fragment, a consecutive interval of logical addresses corresponds to consecutive physical addresses, then this mapping satisfies the compression condition. For example, if the logical addresses in the mapping fragment range from L to L+K, and their corresponding physical addresses are from P to P+K, then the compression condition is met; conversely, if the physical addresses jump, are out of order, or are repeated, then the compression condition is not met. The input to this step is the mapping fragment data in the temporary buffer, and the output is a Boolean judgment result, i.e., whether the compression condition is met.

[0062] Further, if the compression conditions are met, a compression node is allocated from the list of idle compression nodes. The mapped fragments are converted into compressed mapping data and stored in the allocated compression node. The target entry is then updated, with the position indicator field set to a preset second value and the address field pointing to the allocated compression node. Specifically, when the judgment result indicates that the compression conditions are met, the firmware mapping processing module performs a compression storage operation. First, a node is retrieved from the list of idle compression nodes constructed during system initialization. The list of idle compression nodes is a linked list, where each element represents a currently unused compression node. The retrieval operation typically involves removing a node from the head of the linked list and marking it as allocated. Next, compressed mapping data is constructed based on the contents of the mapped fragments in the temporary buffer, i.e., determining the starting logical address, starting physical address, and number of consecutive mappings for this continuous mapping, and these three values ​​are written to the allocated compression node according to a predefined format. Finally, the target entry in the secondary mapping table is updated, modifying its position indicator field to a preset second value and its address field to an index pointing to this newly allocated compression node. The input for this step is the mapped fragment data that meets the compression conditions, and the output is the updated target entry of the secondary mapping table and a new compressed node with the data written to it.

[0063] Further, if the compression condition is not met, a cache unit is allocated from the first-level mapping table cache, the mapping fragment is stored in the allocated cache unit, and the target entry is updated so that the position indicator field is set to a preset first value and the address field points to the allocated cache unit. Specifically, when the judgment result is that the compression condition is not met, the firmware mapping processing module performs uncompressed storage operations. First, a free cache unit is allocated from the management structure of the first-level mapping table cache. The first-level mapping table cache usually adopts a cache-like management method, such as using the least recently used algorithm to select a replaceable cache unit, or maintaining a list of free cache units. Further, the complete mapping fragment data in the temporary buffer is copied item by item to the allocated cache unit. Further, the target entry in the second-level mapping table is updated, modifying the value of its position indicator field to a preset first value and modifying the value of its address field to point to the index of this newly allocated cache unit. The input of this step is the mapping fragment data that does not meet the compression condition, and the output is the updated second-level mapping table target entry and a new cache unit with written data.

[0064] This embodiment achieves dynamic optimization and adaptive selection of the storage format of mapped fragments by introducing compression condition judgment during the mapping loading process. For mapped fragments that meet the compression conditions, they are converted into triplet form stored in the compressed node, requiring only three double-word storage spaces. Compared with the thousands of bytes required by the uncompressed format, the memory usage is reduced to less than one percent, thus significantly improving memory utilization efficiency. Furthermore, for mapped fragments that do not meet the compression conditions, they are still stored in the first-level mapping table cache in the uncompressed format, preserving the convenience of linear access and avoiding the additional computational overhead caused by forced compression. This dynamic judgment and format conversion mechanism allows limited memory resources to be optimally allocated according to the actual characteristics of the mapped data, maximizing the number of mapped fragments that can reside in memory and ensuring that each mapping exists in the format most suitable for its own characteristics. Furthermore, by updating the target entry in the second-level mapping table, the index of the newly allocated cache unit or compressed node is associated with a preset first or second value, so that subsequent access to the mapped fragment can be completed directly through the hardware acceleration path. This mechanism forms a complete closed loop from missing mappings to mapping loading, and then to accelerated mapping, ensuring that every mapping loading operation contributes to the improvement of subsequent access performance, and realizing a positive cycle in which system performance grows in sync with the improvement of memory resource utilization.

[0065] In some preferred embodiments, the method further includes: during the system initialization phase, constructing the first-level mapping table cache, the second-level mapping table, the compressed node list, and the idle compressed node list in memory; wherein the compressed node list is used to store allocated compressed nodes, and the idle compressed node list is used to store unallocated compressed nodes.

[0066] In practice, during the system initialization phase, a first-level mapping table cache, a second-level mapping table, a compressed node list, and an idle compressed node list are constructed in memory. The compressed node list stores allocated compressed nodes, while the idle compressed node list stores unallocated compressed nodes.

[0067] Specifically, during the initialization process after system power-on or reset, the memory management module allocates several contiguous or discrete address spaces in specific areas of memory based on pre-configured system parameters. These spaces are used to construct the core data structures required for subsequent operation. The size and location of these data structures are determined during system design, and memory reservation and formatting are completed during the initialization phase.

[0068] Furthermore, the first-level mapping table cache is constructed as an array of fixed-size cache units. The size of each cache unit strictly matches the size of a mapping slice to ensure that an uncompressed mapping slice can be stored completely. The total number of cache units determines how many uncompressed mapping slices the system can cache simultaneously, and this number is set based on a trade-off between memory capacity and performance requirements.

[0069] Furthermore, the secondary mapping table is constructed as an array with the same number of elements as the total number of mapped slices in the system. Each element is an entry, containing a location indicator field and an address field. During initialization, all entries are set to default values. Specifically, the location indicator field is set to a preset third value, indicating that initially, all mapped slices are not loaded into memory; the address field is set to the factory-preset physical address of the corresponding mapped slice in the NAND mapped storage area. In this way, the secondary mapping table has complete mapped slice location capabilities after initialization.

[0070] Furthermore, the list of compressed nodes is constructed as an array, where each element is a compressed node data structure used to store a triplet of compressed mapping data. The total number of compressed nodes determines how many compressed mapping fragments can reside in memory simultaneously.

[0071] Furthermore, the list of idle compressed nodes is constructed as a linked list data structure. During initialization, all compressed nodes are added to the list of idle compressed nodes sequentially, with each node in the linked list pointing to a compressed node, indicating that all these compressed nodes are currently in an idle and available state. The list of idle compressed nodes is typically constructed by reserving a link pointer field in each compressed node, chaining these nodes together into a singly linked list.

[0072] Through the above initialization operations, the system completes the preparation of all necessary data structures during the startup phase. Subsequently, when the firmware mapping processing module needs to allocate a compression node, it simply retrieves a node from the head of the free compression node list and removes it from the linked list; when a compression node needs to be released, it is re-attached to the head of the free compression node list. The compression node list itself does not need to be explicitly maintained; allocated compression nodes can be accessed through the address field of the secondary mapping table.

[0073] This embodiment provides a stable memory resource foundation for the entire mapping management mechanism by pre-constructing a first-level mapping table cache, a second-level mapping table, a compressed node list, and an idle compressed node list during the system initialization phase, minimizing runtime resource management overhead. The pre-construction of the first-level and second-level mapping table caches ensures that the hardware acceleration engine can directly access data structures with uniform format and fixed addresses during queries, avoiding the uncertainty and performance fluctuations caused by dynamic memory allocation at runtime. Furthermore, the separate design of the compressed node list and the idle compressed node list enables lock-free and efficient management of compressed node resources. The idle compressed node list uses a linked list format, allowing the allocation and release of compressed nodes to be completed simply by modifying the head pointer of the linked list, achieving constant-time complexity and avoiding complex resource lookup and defragmentation processes. This approach of completing data structure construction during system initialization, by pre-emptively addressing resource preparation overhead, allows runtime mapping loading and access operations to focus on core logic without intervening in memory management details, thereby improving the overall efficiency and stability of the system and providing assurance for storage applications with high real-time requirements.

[0074] In some preferred embodiments, the read request is initiated by the host. Before receiving the read request for the target logical address, the read request is divided into at least one logical address according to a preset mapping unit size by a command preprocessing acceleration engine. The at least one logical address includes the target logical address.

[0075] In practice, the read request is initiated by the host. Before responding to the read request for the target logical address, the process also includes dividing the read request into at least one logical address according to a preset mapping unit size. The at least one logical address includes the target logical address.

[0076] Specifically, data access between the host and storage device is performed in units of logical addresses. When the host needs to read data, it sends a read command to the storage device. This command contains two key parameters: the starting logical address and the number of logical addresses to be read. The starting logical block address identifies the starting position of this access, while the number of logical blocks indicates the length of the data to be accessed. However, the mapping management within the storage device is based on fixed-size logical address units, each corresponding to a minimum access granularity, such as four kilobytes of user data. A single read command from the host may span multiple such minimum units.

[0077] Therefore, a command preprocessing unit is set up at the front end of the command processing. This command preprocessing unit receives the read command issued by the host, parses it, and obtains the starting logical address and the read length. Based on the preset mapping unit size (i.e., the number of logical addresses covered by each mapping fragment) and the data block size corresponding to each logical address unit, the command preprocessing unit breaks down the continuous read command into a series of independent read requests. Specifically, the decomposition process is as follows: First, based on the starting logical address, the first logical address to be accessed is determined. Further, the total number of logical addresses to be accessed is calculated based on the read length. For each offset from zero to this number minus one, an independent read request is generated, each read request carrying a unique logical address equal to the starting logical address plus the offset. These logical addresses are the smallest processing units for subsequent mapping queries and physical address retrieval operations. For example, if the read command requires the data length to be read to span three smallest units, it will be split into three read requests, each corresponding to three consecutive logical addresses. In the resulting logical address sequence after segmentation, each logical address will be used as the target logical address and enter the hardware acceleration processing flow described in Example 1.

[0078] Through the steps of this embodiment, the read commands initiated by the host are standardized into read request units that match the granularity of mapping management, providing a unified input format for subsequent mapping queries based on logical addresses. After the splitting operation is completed, the generated list of logical addresses is fed into the processing pipeline one by one.

[0079] In some preferred embodiments, the method further includes: if a write request for a target logical address is received, submitting the write request to the read / write processing module to initiate the writing of user data.

[0080] In practice, when the host needs to write data, it sends a write command to the storage device. The write command includes the starting logical address, the length of the data to be written, and the data content itself. Unlike the processing logic of read requests, the essence of a write operation is to allocate storage space for the newly written data and establish a new mapping relationship between logical addresses and physical addresses. This process involves the allocation of physical blocks, checking the erase status, the actual writing of data, and updating the mapping table. These operations cannot be completed through simple hardware queries and calculations; they must rely on the complex management logic of the firmware.

[0081] Therefore, the processing paths for write requests and read requests are intentionally separated. When the command preprocessing unit recognizes that the current processing is a write command, it does not send the logical address after the write command is segmented to the hardware acceleration engine for mapping lookup. Instead, the write request is directly submitted to the read / write processing module. The read / write processing module is a hardware-software co-processing interface responsible for passing upper-layer requests to the firmware processing module. Further, upon receiving a write request, the firmware processing module performs the following typical operations: First, based on the current wear and tear of the NAND media and the free block status, it allocates one or more free physical pages for the target logical address; then, it writes the data provided by the host to these physical pages through the NAND controller; after the write is complete, the firmware updates the corresponding mapping relationship, that is, it records the correspondence between the logical address and the physical address in the first-level mapping table cache or compressed node in memory, and ensures that the status information in the second-level mapping table is updated synchronously; finally, the firmware returns a write completion status to the host. Throughout the entire write operation, the hardware acceleration engine does not participate in mapping lookup; its lookup path only serves read requests.

[0082] This embodiment clarifies the processing path for write requests, distinguishing it from the hardware acceleration path for read requests, thus forming a complete read / write processing flow. Write requests serve as input, are forwarded by the read / write processing module, and are ultimately physically written to the data and have their mapping relationships established by the firmware.

[0083] Please see Figure 2 , Figure 2 This is a schematic block diagram of a computer device provided in an embodiment of this application. The computer device 500 can be a terminal or a server, wherein the server can be a standalone server or a server cluster composed of multiple servers.

[0084] The computer device 500 includes a processor 502, a memory, and a network interface 505 connected via a system bus 501. The memory may include a non-volatile storage medium 503 and internal memory 504.

[0085] The non-volatile storage medium 503 may store an operating system 5031 and a computer program 5032. When the computer program 5032 is executed, it causes the processor 502 to execute a hardware-accelerated method that supports map table compression.

[0086] The processor 502 provides computing and control capabilities to support the operation of the entire computer device 500.

[0087] The internal memory 504 provides an environment for the execution of the computer program 5032 in the non-volatile storage medium 503. When the computer program 5032 is executed by the processor 502, the processor 502 can execute a hardware acceleration method that supports mapping table compression.

[0088] The network interface 505 is used for network communication with other devices. Those skilled in the art will understand that the above structure is merely a block diagram of a portion of the structure related to the present application and does not constitute a limitation on the computer device 500 to which the present application is applied. A specific computer device 500 may include more or fewer components than shown in the figures, or combine certain components, or have different component arrangements.

[0089] The processor 502 is used to run a computer program 5032 stored in a memory to implement the steps of a hardware acceleration method supporting mapping table compression provided in any of the above method embodiments.

[0090] It should be understood that in the embodiments of this application, the processor 502 may be a central processing unit (CPU), or it may be other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor may be a microprocessor or any conventional processor.

[0091] It will be understood by those skilled in the art that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program may be stored in a storage medium, which is a computer-readable storage medium. The computer program is executed by at least one processor in the computer system to implement the process steps of the embodiments of the above methods.

[0092] Therefore, the present invention also provides a storage medium. This storage medium can be a computer-readable storage medium. The storage medium stores a computer program. When executed by a processor, the computer program causes the processor to perform the steps of a hardware-accelerated method supporting mapping table compression provided in any of the above method embodiments.

[0093] The storage medium is a physical, non-transient storage medium, such as a USB flash drive, external hard drive, read-only memory (ROM), magnetic disk, or optical disk, or any other physical storage medium capable of storing program code. The computer-readable storage medium can be non-volatile or volatile.

[0094] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementations should not be considered beyond the scope of this invention.

[0095] In the several embodiments provided by this invention, it should be understood that the disclosed apparatus and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative. For example, the division of each unit is merely a logical functional division, and there may be other division methods in actual implementation. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed.

[0096] The steps in the method of this invention can be adjusted, merged, or reduced in order according to actual needs. The units in the device of this invention can be merged, divided, or reduced according to actual needs. Furthermore, the functional units in the various embodiments of this invention can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0097] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a storage medium. Based on this understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, a terminal, or a network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present invention.

[0098] In the above embodiments, the descriptions of each embodiment have different focuses. For parts that are not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0099] Obviously, those skilled in the art can make various modifications and variations to this invention without departing from its spirit and scope. Since these modifications and variations fall within the scope of the claims and their equivalents, this invention also intends to include these modifications and variations.

[0100] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the technical scope disclosed in the present invention, and these modifications or substitutions should all be covered within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A hardware acceleration method supporting mapping table compression, characterized in that, Applied to hardware acceleration engines, including: If a read request for a target logical address is received, the corresponding target mapping shard index is determined based on the target logical address; The target table entry corresponding to the target mapping shard index is obtained by querying the resident secondary mapping table according to the target mapping shard index. The target table entry includes a location indication field and an address field. If the value of the location indication field is a preset first value, then the physical address corresponding to the target logical address is read from the first-level mapping table cache according to the address field; wherein, the preset first value is used to indicate that the mapping shard corresponding to the target mapping shard index is stored in the first-level mapping table cache in an uncompressed format; If the value of the location indication field is a preset second value, then compressed mapping data is obtained from the compressed node according to the address field, and the physical address corresponding to the target logical address is calculated according to the compressed mapping data and the target logical address; wherein, the preset second value is used to indicate that the mapping fragment corresponding to the target mapping fragment index is stored in the compressed node in a compressed format; The physical address is submitted to the read / write processing module to initiate access to user data.

2. The hardware acceleration method supporting mapping table compression according to claim 1, characterized in that, Each entry in the secondary mapping table includes a location indication field and an address field; wherein, when the value of the location indication field is a preset first value, the address field points to the cache unit in the primary mapping table cache that stores the mapping fragment; when the value of the location indication field is a preset second value, the address field points to the compression node that stores the compressed mapping data; when the value of the location indication field is a preset third value, the address field points to the storage address of the mapping fragment in the NAND, and the preset third value is used to indicate that the mapping fragment is not loaded into memory and is stored in the NAND.

3. The hardware acceleration method supporting mapping table compression according to claim 1, characterized in that, The step of reading the physical address corresponding to the target logical address from the first-level mapping table cache based on the address field includes: The target cache unit in the first-level mapping table cache is determined based on the address field; Based on the offset of the target logical address within the target mapping segment, the physical address corresponding to the offset is read from the target cache unit.

4. The hardware acceleration method supporting mapping table compression according to claim 1, characterized in that, The step of obtaining compression mapping data from the compression node based on the address field, and calculating the physical address corresponding to the target logical address based on the compression mapping data and the target logical address, includes: The target compression node is determined based on the address field; Read compression mapping data from the target compression node, the compression mapping data including the starting logical address, the starting physical address, and the number of consecutive elements; The physical address corresponding to the target logical address is calculated based on the difference between the target logical address and the starting logical address, and the starting physical address.

5. The hardware acceleration method supporting mapping table compression according to claim 2, characterized in that, Also includes: If the value of the location indication field is a preset third value, then the mapping fragment corresponding to the target mapping fragment index is loaded from the NAND according to the address field; Determine whether the loaded mapping fragments meet the preset compression conditions; If the compression conditions are met, a compression node is allocated from the preset list of idle compression nodes. The mapped fragment is converted into compressed mapping data and stored in the allocated compression node. The target entry is updated to: the location indication field is set to the preset second value, and the address field points to the allocated compression node. If the compression conditions are not met, a cache unit is allocated from the first-level mapping table cache, the mapping fragment is stored in the allocated cache unit, and the target table entry is updated to: the location indication field is set to the preset first value, and the address field points to the allocated cache unit.

6. The hardware acceleration method supporting mapping table compression according to claim 5, characterized in that, Also includes: During the system initialization phase, the first-level mapping table cache, the second-level mapping table, the compressed node list, and the idle compressed node list are constructed in memory; wherein, the compressed node list is used to store the allocated compressed nodes, and the idle compressed node list is used to store the unallocated compressed nodes.

7. The hardware acceleration method supporting mapping table compression according to claim 1, characterized in that, The read request is initiated by the host. Before receiving the read request for the target logical address, the read request is divided into at least one logical address according to a preset mapping unit size by the command preprocessing acceleration engine. The at least one logical address includes the target logical address.

8. The hardware acceleration method supporting mapping table compression according to claim 1, characterized in that, Also includes: If a write request for the target logical address is received, the write request is submitted to the read / write processing module to initiate the writing of user data.

9. A computer device, characterized in that, The computer device includes a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the method as described in any one of claims 1-8.

10. A computer-readable storage medium, characterized in that, The storage medium stores a computer program that, when executed by a processor, can implement the method as described in any one of claims 1-8.

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